Verilog and Net Delay

Citation:	Hisashi Sasaki, "A Formal Semantics on Net Delay in Verilog-HDL". In Proceedings of Asia Pacific Conference on Chip Design Languages (APCHDL'99), Fukuoka, Japan, 6-8 October 1999, 100--106.
Summary:	An extension of the Verilog-HDL paper giving semantics for net delays in Verilog-HDL using ASMs.
Subjects:	VHDL
Download:	PostScript, PDF, Compressed PostScript
Notes:	See the original Verilog-HDL paper.

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