VHDL and Verilog

Citation:	Hisashi Sasaki, "A Formal Semantics for Verilog-VHDL Simulation Interoperability by Abstract State Machine", Proceedings of DATE'99 (Design, Automation and Test in Europe), ICM Munich, Germany, March 9-12, 1999.
Summary:	A formal semantics for Verilog-HDL and VHDL focusing on the simulation model. The semantics presented is faithful to the language reference manual and is expected to become a first step towards semantic interoperability analysis on multi-semantic domains such as Verilog-AMS and VHDL-AMS.
Subjects:	VHDL
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Abstract State Machines