4765 CSE Building, 2260 Howard Avenue, Ann Arbor, MI 48109-2121, USA
mazum@eecs.umich.edu +1 (734) 763-2107 +1 (734) 763-8094

• Resume: [PDF version]
  • Publications: Books [Coauthored] ; List of Other Publications [pdf]
    
  • Research Accomplishments : [Text Form] [Bullet Form]
    
    Descriptions of Research Projects:
    • Semiconductor Memory Systems (NSF, ARO, DEC)
    • Quantum Tunneling Circuits and CAD Tools (DARPA, ONR, NSF)
    • VLSI Circuit Optimization Techniques (IBM, GM, DEC, BNR)
    • Bio-Inspired Computing (ARO, DEC, NSF)
    • Reliable VLSI Systems Design (NSF, IBM, DEC)
    • Plasmonics and THz Bio-Sensing (AFOSR, NSF, ARO)
    • Quantum Physics and VLSI Synergies (DARPA, ONR, TI, NEC)
    • EM Theory and VLSI Synergies (AFOSR, NSF)
    • Innovative VLSI Chip and System Design (HRL, KG, NL, NSF, DARPA, SM)
    • VLSI Complexity Issues (NSF)
    
    Names of Sponsors of Above Research Projects
    (1) National Science Foundation (NSF), (2) Defense Advanced Research Projects Agency (DARPA), (3) Office of Naval Research (ONR), (4) Army Research Office (ARO), (5) Air Force Office of Scientific Research (AFOSR), (6) State of Michigan (SM),  (7) Nippon Electric Company (NEC), (8) Bell Northern Reserach Laboratory (BNR), (9) General Motors (GM), (9) Digital Equipment Corporation (DEC), (10) International Business Machines (IBM), (11) NanoLogic (NL), (12) Korean Government Tera and Nanoelectronics Research (KG), (13) Texas Instruments (TI), (14) Hughes Research Lab (HRL)
    
    
  • Teaching

  Undergrad Courses Taught:

  Sophomore Level: EECS 270: Digital Logic Design (taught 17 times)
  Junior Level:EECS 312: Digital Integrated Circuit Design (taught 2 times)
  Senior Level: EECS 427: VLSI Design (taught 6 times)

Regular Graduate Courses Taught:

EECS 570: Parallel Architectures (taught 2 times)
EECS 579: Digital System Testing (taught 2 times)

New Graduates Courses Developed:

EECS 527: VLSI Layout Automation (taught 10 times)
EECS 598-2: Nanocircuits and Nanoarchitectures (taught 1 time)
EECS 598-6: Ultra-Low-Power CMOS Design (taught 1 time)

On-line Courses Developed for Practicing Engineers:

NTU-Walden Univ. Distant Learning Course on Logic Design

Integration of Research with Teaching:

VLSI Courseware Developed and Distributed:

1) Cell Placement Algorithms [pdf]
2) VLSI Routing Algorithms [pdf]
3) Gate Matrix Algorithms [pdf]

Advanced Books Written for Practicing Engineers:

1) Genetic Algorithms for VLSI Design [pdf]
2) Ultra-High Density Memory Testing [pdf]
3) Reliability of Semiconductor Memories [pdf]


STEM Education and K-12 Maths Software Developed:

MathGuru

• Teaching Evaluations: [Numerical Evaluations] [Student Comments]

(1) [Double-bit ECC in Giga-bit DRAM Chips],  (2)  [RTD Modeling Technique], (3)  [Full-Chip Thermal Modeling for CMOS],  (4)  [RTD Circuit Design Techniques] , (5)  [VLSI Standard Cell Placement Algorithms], (6)  [Quantum SPICE Simulator],  (7)  [Parallel Parametric Testing of DRAM Chips], (8)  [Optimal Tapering of Transistors in CMOS Circuits], (9)  [VLSI Interconnect Modeling Using Differential Quadrature Method],  (10) [Electromagnetic Coupling of VLSI Interconnect], (11) [Active Terahertz Switch Using Liquid Crystal], (12) [Terahertz Spoof Surface Plasmon Polariton], (13) [Terahertz Active Switch Based on Waveguide-Cavity-Waveguide], (14) [Plasmonic Nanowire], (15) [Plasmonic Nanoparticle Chain], (16)  [Gate Leakage current Modeling for Nanoscale CMOS FET], (17)  [Quantum Dot Modeling], (18)  [Parallel Genetic Algorithm for VLSI Cell Placement], (19) [Quantum Dot Architectures for Motion Detection], (20)  [Parallel Testing of Semiconductor Memories], (21)  [Built-in Self-Testing of CAM Memories], (22)  [Built-in Self-Repairable Memory Compiler], (23) [Self Writing in Memristor Crossbar Memory], (24)[Memristor-Based Position Detector], (25)  [RTD-based Keeper Design for Domino Logic with Improved Noise Performance], (26)  [Quadtree Datastructure for VLSI and Image Processing], (27) [Genetic Algorithm for VLSI Cell Placement],  (28) [Self-Repair Technique for Memories], (29)  [Self-Repair Technique for VLSI Processor Arrays], (30)  [Multivalued Adder Design Using RTD's], (31)  [RTD-based Low-Power and High-Speed Memory System], (32) [Evaluation of On-Chip Parallel Processing Circuits], (33)  [VLSI Layout Technique for On-Chip Parallel Processing], (34) [Unified Wire Routing Algorithms for VLSI Layout]

Cataloging of Journal Publications

1. Semiconductor Memory Systems - Papers: 14, 15, 16, 19, 20, 22, 28, 30, 81, 96, 36

2. Quantum Tunneling Circuits and CAD Tools - Papers: 39, 40, 33, 38, 48, 49, 97, 101

3. VLSI Circuit Optimization Techniques - Papers: 79, 80, 84, 37, 74

4. Bio-Inspired Computing - Papers: 57, 62, 64, 69, 93, 92

5. Reliable VLSI Systems Design - Papers: 28, 24, 27, 31, 34, 26, 23, 75, 77, 78

6 .Plasmonics and THz Bio-Sensing: 86, 88, 89, 90, 91, 98

7. Quantum Physics and VLSI Synergies - Papers: 40, 50, 84, 85, 92, 93, 95, 100, 87, 101

8. EM Theory and VLSI Synergies - Papers: 73, 82, 83, 72, 91, 98

9. Innovative VLSI Chip and System Design - Papers: 29, 46, 58, 67, 32, 18, 59

10.VLSI Complexity Issues - Papers: 60, 61, 63, 43, 66

** Mazumder's Master Thesis on Multicore Interconnection and Layout

** Commercial Impact of Research on Memory Systems

 Books

1. Genetic Algorithms for VLSI Design, Layout & Test Automation (Hardcover) by Pinaki Mazumder and Elizabeth Rudnick [pdf]
2. Testing and Testable Design of High-Density Random-Access Memories (Hardcover) by Pinaki Mazumder and Kanad Chakraborty [pdf]
3. Fault Tolerance and Reliability Techniques for High-Density Random-Access Memories (Hardcover) by Kanad Chakraborty and Pinaki Mazumder [pdf]