PINAKI MAZUMDER[1]
Room Number: 4765, Computer Science and Engineering
Building, Department of Electrical Engineering and Computer Science, 2260
Hayward Avenue, University of Michigan, Ann Arbor, MI 48109-2121.
Phone: 734-763-2107 (Office), and Fax: 734-763-8094. E-Mail: mazum@eecs.umich.edu
Please see Mazumder’s homepage at http://www.eecs.umich.edu/~mazum
Immigration Status: US Citizen
since 1995.
I. Educational Qualification
Ph.D. in Computer Engineering University of Illinois, Urbana-Champaign 1988
M. Sc. in Computer Science University of Alberta, Edmonton, Canada 1985
B.S. in Electrical Engineering Indian Institute of Science, Bangalore, India 1976
I also received a degree in B.Sc. Physics Honors
securing the first rank in Gauhati University, India amongst estimated 100,000
students in all disciplines of liberal arts and basic sciences.
II. Work Experience
US Government (National Science
Foundation):
2007-2008 Program
Director for Emerging Models and Technologies Program (funding areas: Nanoelectronics,
Quantum Computing, and Biologically Inspired Computing with an annual budget of
$18 Million) in the Directorate for Computer and Information and Science and
Engineering, National Science Foundation, Arlington, Virginia.
2009 Program
Director in Electrical, Communications and Cyber Systems Division (funding
areas: Quantum, Molecular and High
Performance Computing, Adaptive Intelligent Systems, Electronic and Photonic
Devices, and Major Research Instrumentation) of the Engineering Directorate at
National Science Foundation.
Academic Teaching and Research:
1998- to date Tenured Professor, Division of Computer Science and
Engineering, Department of Electrical Engineering and Computer Science,
University of Michigan, Ann Arbor, USA.
1996-1997 Research
Fellow, Division of Electrical and Computer Engineering, Department of
Electrical Engineering and Computer Science, University of California, Berkeley,
USA.
1996-1997 Visiting
Associate Professor, Department of Computer Science and Engineering, Stanford
University, Palo Alto, California, USA.
1997 Visiting Professor, NTT
Research Laboratories, Atsugi-shi, Japan.
1992-1998 Tenured
Associate Professor, Division of Computer Science and Engineering, Department
of Electrical Engineering and Computer Science, University of Michigan, Ann
Arbor, USA.
1987-1992 Assistant
Professor, Division of Computer Science and Engineering, Department of
Electrical Engineering and Computer Science, University of Michigan, Ann Arbor,
USA.
1985-1987 Research
Assistant, University of Illinois at Urbana-Champaign, USA.
1982-1984 Teaching
Assistant at University of Alberta, Edmonton, Canada.
1974-1975 Research
Assistant at Indian Institute of Science, Bangalore, India.
Industrial Research and Development:
1985, 1986 Member of Technical Staff, AT&T
Bell Laboratories, Indian Hill, Chicago.
1976-1982 Senior
R&D Engineer, Bharat Electronics Ltd., Bangalore, India.
III. Major Fields of Research
1) VLSI design, testing and layout automation; 2)
Nanoelectronics and nanomagnetics: multiscale modeling, simulation tools,
circuits and architectures; 3) Terahertz technology and applications in signal
processing, computing and communications.
IV. Awards and Recognitions
V. Research Funding
Pending Proposals:
3.
Ultra-Low-Power
Bio-inspired Nanoelectronics for Navigation in Autonomous Insect-Scale Robots, Air
Force Office of Scientific Research, $790,000 (PI)
VI. Committees and Professional Activities
VII. Professional Experience
Details
of My Professional Accomplishments
US Government
at National Science Foundation (3
years)
In 2007 and 2008, I worked as the lead Program Director for Emerging
Models and Technologies (EMT) program in the Division of Computing and Communication
Foundations (having nearly $140 Million annual budget) of the
Directorate for Computer and Information and Science and Engineering, National
Science Foundation, Arlington, Virginia. My mandate was to manage research
grants in Nanoelectronic Modeling and Systems, Quantum Computing, and
Biologically Inspired Computing for which I had an operating annual budget of
about $18 Million. Additionally, I participated in several NSF crosscutting
programs such as Cyber-Enabled Discovery and Innovation (CDI), Expeditions in
Computing, Major Research Instrumentation (MRI), Computing Research Infrastructure
(CRI) and Cyber Physical Systems (CPS). In 2009, I worked as a Program Director
in the Engineering Directorate where I managed research in three broad areas: Adaptive
Intelligent Systems (Machine Learning), Quantum, Molecular and High-Performance
Modeling, and Electronic and Photonic Devices. During these three years, I interacted
with several program managers and administrators of NSF, DARPA, ARO, ONR, and
AFOSR to help launch national-level major research initiatives. I consider that
serving the US government for a stint of three years has provided me an
exceptional opportunity to acquire a vast amount of knowledge in various fields
of science and engineering, to network with numerous researchers around the
nation, and to gain divergent administrative experience.
Teaching Experience (29 years)
Since 1988, I have been teaching at the
Department of Electrical Engineering and Computer Science of the University of
Michigan, Ann Arbor, Michigan.
Graduate
courses developed and taught: 1) VLSI
System Design, 2) Optimization and Synthesis of VLSI Layout, 3) Testing of
Digital Circuits and Systems, 4) Advanced Computer Architectures, 5) Nanocircuits
and Nanoarchitectures, 6) Ultra-Low-Power Subthreshold CMOS Circuits, and 7)
Terahertz Technology and Applications.
Undergraduate
courses upgraded and taught: 1)
Introduction to Digital Logic Design (sophomore level), 2) Digital Integrated
Circuit Design (junior level), and 3) VLSI System Design (senior level).
Industrial Experience (6.5 years)
After my baccalaureate degrees in Physics
and Electrical Engineering, I worked for six years (1976-1982) as a Senior
R&D Engineer at Bharat Electronics Ltd. (BEL) in its Integrated Circuits
Division. I designed several bipolar and CMOS analog and digital integrated
circuits for consumer electronic systems.
I was associated with the following chip development projects: i) Raster-scan vertical deflection system
microchip for TV display, ii) Sync processing and horizontal deflection system
microchip for TV display, iii) Video and audio IF stage IC’s for vestigial-AM
and FM signal detection in TV receiver, iv) High-gain audio amplifier microchip
for TV audio stage, v) Tape Recorder IC with automatic gain adjustments, vi)
Hearing-aid IC, vii) Analog clock driver IC, and viii) LCD and AC Plasma
display drive IC’s. Several million commercial chips were fabricated based on
these designs.
After finishing my MSc degree in Computer
Science and while working towards my PhD degree in Electrical and Computer
Engineering, I worked during the summers of 1985 and 1986 as a Member of
Technical Staff at AT&T Bell Laboratories. I was one of the two engineers
who started the Bell Laboratory Cones/Spruce project - a new behavioral
synthesis and layout automation tool for rapid prototyping of digital circuits.
The main contribution of this effort was to demonstrate how a restricted
version of C language could be used to model digital hardware much before commercial
hardware description language (HDL) software tools like Verilog and System C were
designed.
Research Accomplishments:
In
1984, when I started my MS thesis at University of Alberta in the field of
VLSI, I was inspired by the local (Edmonton, Canada) hockey legend, Wayne
Gretzky whose famous quote (“A good
hockey player plays where the puck is. A great hockey player plays where the
puck is going to be”) defined the compass of my research work for the next
28 years as explained below. In Evolutionary CMOS research, I solved numerous
use-inspired research problems that were 10 to15 years ahead of their time and
eventually Moore’s Law has vindicated the practical merits of my research by
impacting the memory and FPGA industry as pointed out below. In Revolutionary
emerging technologies such as quantum tunneling devices, THz plasmonic devices
(in THz regime), ionic devices (as non-volatile memories), and electron spin
based devices (as ultra-low-power nonvolatile memories) I have made sustained
impact for the past 23 years by collaborating with multiple leading researchers
in universities and companies. In my research career, I have endeavored to
emulate the Vannevar Bush model of
triad synergy between University, Industry and Government establishments that
was conceived at the aftermath of the Second World War to challenge academics
to undertake enterprising and leadership role for catalyzing innovations,
accelerated economic growth, and sustained US leadership in science and
engineering.
VIII. Publications
Summary
of Significant Publications
Books: 9; Journal
Publications: 105; Reviewed Conference Papers: 179; Book Chapters: 6; US
Patents: 12.
A. Books
1.
P. Mazumder and K. Chakraborty, “Testing and Testable Design of Random-Access
Memories”, Kluwer Academic Publishers, 1996 (428 pages).
2.
P. Mazumder and E. Rudnick, “Genetic Algorithms for VLSI Layout and Test
Automation”, Prentice Hall, 1999 (460 pages).
3.
K. Chakraborty and P. Mazumder, ”Fault Tolerance and Reliability
Aspects of Random-Access Memories,” Prentice Hall, 2002. (440
pages).
4.
P. Mazumder, “Introduction to Digital Systems”, Video Book on DVD, produced at MGM
Studio (Orlando, Florida), Laureate Education, Inc., 2005.
5.
P. Mazumder, “Handbook of VLSI Routing Techniques: Serial and Parallel Models”, Tshinghua
University Press, 2017.
6.
R. Rajasuman (Editor) and P. Mazumder (Editor), “Semiconductor
Memories: Testing and Reliability”, Computer Science Press, May
1998.
7.
R. J. Lomax (Editor) and P. Mazumder (Editor), “Great Lakes
Symposium on VLSI, 1999”, Computer Science Press, March 1999.
8.
P. Mazumder, “Principle of Digital Logic Design”, Pan
Stanford Publishing, 2017.
9.
P. Mazumder and K. Shahookar, “MathGuru Tutorial” for K-12 Education Software.
B. Reviewed
Journal Publications
EVOLUTIONARY TECHNOLGY (CMOS)
CMOS MEMORY
TESTING & RELIABILITY
10. P. Mazumder, J. H. Patel and W. K.
Fuchs, “Methodologies for Testing Embedded Content-Addressable Memories”, IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems,
Jan. 1988, pp. 11-20.
11. P. Mazumder, “Parallel Testing of
Parametric Faults in a Three-Dimensional Dynamic Random-Access Memory”, IEEE
Journal of Solid-State Circuits, Vol. 23, No. 4, Aug. 1988, pp.
933-942.
12. P. Mazumder and J. H. Patel, “Parallel
Testing of Pattern-Sensitive Faults in Random-Access Memory”, IEEE
Transactions on Computers, Vol. 38, No 3, Mar. 1989, pp. 394-404.
13. P. Mazumder and J. H. Patel, “An
Efficient Built-In Self-Testing Algorithm for Random-Access Memory”, IEEE
Transactions on Industrial Electronics (Special Issue on
Testing) Vol. 36, No. 3, May 1989, pp. 394-407.
14. J. S. Yih and P. Mazumder,
“Circuit Behavior Modeling and Compact Testing Performance Evaluation”, IEEE
Journal of Solid-State Circuits, Vol. 26, No. 1, Jan. 1991, pp. 62-65.
15. P. Mazumder and J. H. Patel, “A
Comprehensive Study of Random Testing for Embedded RAM’s Using Markov Chains”, Journal
of Electronic Testing: Theory and Applications, Vol. 3 No. 4, Nov.
1992, 235-250.
16. S. Mohan and P. Mazumder,
“Analytical and Simulation Studies of Failure Modes in SRAM’s Using
High-Electron Mobility Transistors”, IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems, Vol. 12, No. 12, Dec.
1993, pp. 1885-1896.
17. P. Mazumder and J. P. Hayes, “Testing
and Improving the Testability of Multi-megabit Memories”, IEEE Design and
Test of Computers, Mar. 1993, pp. 6-7.
18. K. Chakraborty and P.
Mazumder, “Technology and Layout Related Testing in Static Random-Access
Memories”, Journal of Electronic Testing: Theory and Applications,
Aug. 1994.
19. P. Mazumder, J. H. Patel and J. A.
Abraham, “A Reconfigurable Parallel Signature Analyzer for Concurrent Error
Correction in Dynamic Random-Access Memory”, IEEE Journal of Solid-State
Circuits, Vol. 25, No. 3, Jun. 1990, pp. 866-870.
20. P. Mazumder and J. Yih, “Restructuring
of Square Processor Arrays by Built-in Self-Repair Circuit,” IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems,
Vol. 12, No. 9, Sept. 1993, pp. 1255-1265.
21. P. Mazumder, “A New On-Chip ECC Circuit
for Correcting Soft Errors in DRAM’s with Trench Capacitors,” IEEE
Journal of Solid-State Circuits, Vol. 27, No. 11, Nov. 1992, pp.
1623-1633.
22. R. Venkateswaran, P.
Mazumder and K. G. Shin, “On Restructuring of Hexagonal Arrays,” IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems,
Vol. 11, No. 12, Dec. 1992, pp. 1574-1585.
23. P. Mazumder and J. Yih, “A New Built-in
Self-Repair Approach to VLSI Memory Yield Enhancement by Using Neural-Type
Circuits,” IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems, Vol. 12, No. 1, Jan. 1993, pp. 124-136.
24. P. Mazumder, “Design of a
Fault-Tolerant Three-Dimensional Dynamic Random-Access Memory with On-Chip
Error-Correcting Circuit,” IEEE Transactions on Computers, Vol.
42, No. 12, Dec. 1993, pp. 1453-1468.
25. M.D. Smith and P.
Mazumder, “Analysis and Design of Hopfield-type Network for Built-in
Self-Repair of Memories,” IEEE Transactions on Computers, Vol.
45, No. 1, Jan. 1996, pp. 109-115.
26. K. Chakraborty and P.
Mazumder, “New March Tests for Multi-port RAM Devices,” JETTA:
Journal on Electronic Testing: Theory and Applications, Vol. 16, No. 4,
Aug. 2000, pp. 389-396.
27. A. F. Gonzalez, M.
Bhattacharya, S. Kulkarni, and P. Mazumder, ”CMOS Implementation of a
Multiple-Valued Logic Signed-Digit Adder Based on Negative
Differential-Resistance Devices,” IEEE Journal of Solid-State Circuits,
Vol. 36, No. 6, June 2001, pp. 924-932.
CMOS VLSI LAYOUT AUTOMATION
28. K. Shahookar and P.
Mazumder, “A Genetic Approach to Standard Cell Placement with Meta-Genetic
Parameter Optimization,” IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, Vol. 9, No. 5, May 1990, pp.
500-511.
29. R. Venkateswaran and P.
Mazumder, “Hexagonal Array Machine for Multi-Layer Wire Routing,” IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems,
Vol. 9, No. 10, Oct. 1990, pp. 1096-1112.
30. J. Yih and P. Mazumder,
“A Neural Network Design for Circuit Partitioning,” IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems, Vol.
9, No. 12, Dec. 1990, pp. 1265-1271.
31. K. Shahookar and P.
Mazumder, “VLSI Cell Placement Techniques,” ACM Computing Surveys,
Vol. 23, No. 2, June 1991, pp. 143-220.
32. K. Shahookar and P.
Mazumder, Japanese translation of VLSI Cell Placement Techniques, Bit:
Computer Science ‘91, Kyoritsu Shuppan Co., Ltd., Tokyo,
Japan, 1991.
33. P. Mazumder, “Decomposition Strategies
for Quad-tree Data Structure,” Journal of Computer Vision, Graphics, and
Image Processing, Academic Press, June 1987, pp. 258-274.
34. H. M. Chan, P. Mazumder
and K. Shahookar, “Macro-Cell and Module Placement by Genetic Optimization with
Bit-Map Represented Crossover Operators,” Integration, the International
VLSI Journal, Dec. 1991, pp. 49-77.
35. P. Mazumder, “Layout Optimization for
Yield Enhancement in On-Chip VLSI/WSI Parallel Processing,” IEE
Proceedings-E: Computers and Digital Techniques. Vol. 139, No.
1, Jan. 1992, pp. 21-28.
36. S. Mohan and P. Mazumder,
“WOLVERINES: A Distributed Standard Cell Placement Tool,” IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems,
Vol. 12, No. 9, Sept. 1993, pp. 1312-1326.
37. K. Shahookar, W. Khamisani, P.
Mazumder, S.M. Reddy, “Genetic Beam Search for Gate Matrix Placement,” IEE
Proceedings-E: Computers and Digital Techniques, Vol. 141, No.
2, Mar. 1994, pp. 123-128.
38. R. Venkateswaran and P.
Mazumder, “DA Techniques for PLD and FPGA Based Systems,” Integration,
the International VLSI Journal, Vol. 17, Dec. 1994, pp. 191-240.
39. R. Venkateswaran and P.
Mazumder, “CHiRPS: A General-area Parallel Multi-layer Routing System,” IEE
Proceedings-E: Computers and Digital Techniques, Vol. 142, No.
3, May 1995, pp. 208-214.
40. P. Mazumder and J. Tartar, “Planar
Topologies for Tree Representation,” Congressus Numerantium, Vol.
46, May 1985, pp. 173-186.
41. H. Esbensen and P.
Mazumder, “Viking: Macro-cell Placement by Genetic Algorithm,” IEE
Proceedings-E: Computers and Digital Techniques.
CMOS VLSI SYSTEM DESIGN ISSUES
42. L. Ding, D. Blaauw and P.
Mazumder, ”Accurate Estimation of Crosstalk Using Effective Coupling
Capacitance,” IEEE Transactions on Computer-Aided Design of
Integrated Systems, Vol. 22, No.5, May 2003, pp.627-634.
43. Q.W. Xu, Z. Li, P.
Mazumder and J. Mao, “Time-domain Modeling of High-speed Interconnects by
Modified Method of Characteristics,” IEEE Transactions on Microwave
Theory and Techniques, Vol. 48, No. 2, Feb. 2000, pp. 323-327.
44. Q.W. Xu and P. Mazumder,
”Modeling of Lossy Multiconductor Transmission Lines,” IEEE Transactions
on Microwave Theory and Techniques, Vol. 50, No. 10, pp 2233-2246, Oct.
2002.
45. Q.W. Xu and P. Mazumder,
“Equivalent-Circuit Interconnect Modeling Based on the Fifth-Order Differential
Quadrature Methods,” IEEE Transactions on VLSI Systems,
Vol.11, No.6, Dec. 2003, pp.1068-1079.
46. K. Chakrabaorty, M.
Bhattacharya, S. Kulkarni, A. Gupta and P. Mazumder, “BISRAMGEN: A
Built-In Self-Repairable SRAM and DRAM Compiler,” IEEE Transactions on
VLSI Systems, Vol. 9, No. 2, Apr. 2001, pp. 352-364.
47. A. Gupta, K. Chakraborty and
P. Mazumder, ”FTROM: A Silicon Compiler for Fault-Tolerant ROMs, ” Integration,
the International VLSI Journal, Vol. 26, No. 1-2, Dec. 1998.
48. L. Ding and P. Mazumder,
”Simultaneous Switching Noise Analysis Using Application Specific Device
Modeling,” IEEE Transactions on VLSI Systems. Vol.11,
No.6, Dec.2003, pp.1146-1152.
49. A. F. Gonzalez and P.
Mazumder, “Redundant Arithmetic: Algorithms and Implementations,” INTEGRATION,
the International VLSI Journal, Vol. 30, Dec. 2000, pp. 13-53.
50. L. Ding and P. Mazumder,
”On Optimal Tapering of FET Chains in High-Speed CMOS Circuits”, IEEE
Transactions on Circuits and Systems, Vol. 48, No. 12, Dec. 2001, pp.
1099-1109.
51. L. Ding and P. Mazumder, “On Circuit techniques to Improve Noise Immunity of CMOS Dynamic Logic,” IEEE Transactions on VLSI Systems, Vol. 12, No. 9, pp. 910-925, Sept. 2004.
52. Q.W. Xu and P. Mazumder,
“Efficient Modeling of Transmission Lines with Electromagnetic Wave Coupling
by Using the Finite Difference Quadrature Method”, IEEE Transactions on VLSI Systems, Vol. 15, No. 12, Dec. 2007,
pp. 1289-1302.
53. P. Mazumder, “Evaluation of On-Chip
Static Interconnection Networks,” IEEE Transactions on Computers,
C-36, Mar. 1987, pp. 365-369.
54. B. Wang and P. Mazumder,
"Accelerated Chip-level Thermal Analysis Using Multilayer Green's Function,"
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
Vol. 26, No. 2, Feb. 2007, pp. 325-244.
55. R. Venkateswaran and P.
Mazumder, “Design of a Coprocessor for Accelerating Maze Routing in VLSI
and PCB Layouts,” IEEE Transactions on VLSI Systems, Mar.
1993, Vol. 1, No. 1, pp. 1-14.
56. P. Mazumder, “An Economical Design of
Programmable Seven Segments to Decimal Decoder,” Electronic Design News,
Apr. 1987, pp. 222-224, (Design Ideas Prize Winner).
57. P. Mazumder, “Satellite Communications
versus Submarine Cables for Long Distance Links,” IETE Journal - A
Special Issue on TV Communication in India, 1976 (Best Student Paper
Award Winner).
REVOLUTIONARY TECHNOLOGIES
QUANTUM TUNNELING DEVICES & SYSTEMS
58. J. P. Sun, G. I. Haddad, P.
Mazumder and J. Schulman, “Resonant Tunneling Diodes: Device and Modeling,”
Proceedings of the IEEE, Apr. 1998, pp. 641-663.
59. P. Mazumder, S. Kulkarni, G. I. Haddad,
and J. P. Sun, “Digital Applications of Quantum Tunneling Devices,” Proceedings
of the IEEE, Apr. 1998, pp. 664-688.
60. L. Ding and P. Mazumder,
“Noise-Tolerant Quantum MOS Circuits Using Resonant Tunneling Devices,” IEEE
Trans. on Nanotechnology, Mar. 2004, pp. 134-146.
61. A. Seabaugh and P.
Mazumder, ”Quantum Devices and Their Applications,” Proceedings of
the IEEE, Vol. 7, No. 4, April 1999.
62. T. Ueymura and P. Mazumder, ”Design and
Analysis of Resonant-Tunneling-Diode (RTD) Based High Performance Memory
System,” IEICE Transactions on Electronics (Special Issue
on Integrated Electronics and New System Paradigms), Vol. E82-C, No. 9, Sept.
1999.
63. M. Bhattacharya and P.
Mazumder, ”Analysis and Simulation of RTD and HBT Based Threshold Gate
Logic,” IEEE Trans. on Circuits and Systems II, Vol. 47, No. 10,
Oct. 2000, pp. 1080-1085.
64. M. Bhattacharya and P.
Mazumder, ”Augmentation of SPICE for simulation of RTD Based Circuits,” IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems,
Vol. 20, No. 1, Jan, 2001, pp. 39-50.
65. A. F. Gonzalez and P.
Mazumder, ”Multiple-Valued Signed-Digit Adder Using Negative
Differential-Resistance Devices,” IEEE Transactions on Computers,
Vol. 47, No. 9, Sept. 1998, pp. 947-959.
66. S. Mohan, P. Mazumder,
G. I. Haddad, R. Mains, and J. P. Sun, Ultra-fast Pipelined Adders Using
Resonant Tunneling Transistors, IEE Electronics Letters, Vol.
27, No. 10, May 1991, pp. 830-831.
67. G. I. Haddad and P.
Mazumder, ”Tunneling Devices and Their Applications in
High-Functionality/Speed Digital Circuits,” Journal of Solid State
Electronics, Vol. 41, No. 10, Oct. 1997, pp. 1515-1524.
68. W. H. Lee and P. Mazumder, “Color Image Processing Using Multi-Peak RTD’s”, ACM Journal of Emerging Technologies in Computing Systems, Vol. 9 No. 3, September 2013 (20 pages).
69. S. Mohan, P. Mazumder
and G. I. Haddad, “A Sub-nanosecond 32-bit Multiplier Using Negative
Differential Resistance Devices,” IEE Electronics Letters, Oct.
1991, Vol. 27, No. 21, pp. 1929-1931.
70. S. Mohan, P. Mazumder,
G.I. Haddad and W. L. Chen, “Pico Second Pipelined Adder Using Three-Terminal
NDR Devices,” IEE Proceedings-E: Computers and Digital Techniques,
Vol. 141, No. 2, Mar. 1994, pp. 104-110.
71. S. Mohan, P. Mazumder,
G. I. Haddad, R. Mains, and S. Sung, “Logic Design Based on Negative
Differential Resistance Characteristics of Quantum Electronic Devices,” IEE
Proceedings-G: Electronic Devices, Vol. 140, No. 6, Dec. 1993,
pp. 383-391.
72. E. Chan, S. Mohan, P.
Mazumder and G. I. Haddad, “Compact Multiple-valued Multiplexers Using
Negative Differential Resistance,” IEEE Journal of Solid-State Circuits,
Vol. 31, No. 8, Aug. 1996, pp. 1151-1156.
73. E. Chan, M. Bhattacharya and
P. Mazumder, “Mask Programmable Multi-Valued Logic Gate Arrays Using
Resonant Tunneling Devices,” IEE Proceedings-E: Computers and Digital
Techniques, Vol. 143, No. 5, Oct. 1996, pp. 289-294.
74. S. Mohan, J.P. Sun, P.
Mazumder and G. I. Haddad, “Device and Circuit Models for Resonant
Tunneling Devices for Circuit Simulation,” IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems, Vol.
140, No. 6, June 1995, pp. 653-662.
75. P. Mazumder, J.P. Sun, S. Mohan and
G.I. Haddad, “DC and Transient Simulation of Resonant Tunneling Devices in
NDR-SPICE,” Institute of Physics, No. 141, Sept. 1994, pp.
867-872.
76. P. Fay, P. Mazumder,
et al., ”Digital Integrated Circuit Based on Monolithically Integrated
In-AlAs/InGaAs/InP HEMT’s and InAs/AlSb/GaSb Resonant Interband Tunneling
Diodes,” Electronics Letters, Vol. 37, No. 12, June 2001, pp.
758-759.
77. H. Zhang, P. Mazumder,
L. Ding, and K. Yang, “Performance Modeling of Resonant Tunneling Random-Access
Memories,” IEEE Transactions on
Nanotechnology, July 2005, pp.
472-480.
NANOELECTRONIC DEVICES & CIRCUITS
78. M.
Rajagopalan and P. Mazumder, “Tunneling through Finite Quantum Dot Super-lattices”
AJSE
(Springer), Vol. 39, No. 3, pp. 1863-1879 (Invited).
79. W.H. Lee and P. Mazumder,
"Motion Detection by Quantum Dots Based Velocity-Tuned Filter", IEEE
Transactions on Nanotechnology, Vol. 7, No. 3, May 2008, pp. 357-362.
80. Y. Yilmaz
and P. Mazumder, “Image Processing by a Programmable Grid Compromising
Quantum-Dots and Memristor,” IEEE
Transactions on Nanotechnology, Vol.12, No.6, pp. 879-887, November
2013.
81. J. P. Sun, W. Wang, N. Gu
and P. Mazumder, “Gate Current and Capacitance Models of Nanoscale
MOSFETs,” IEEE Transactions on Electron Devices, Vol. 53, No. 12, Dec. 2006, pp. 2950-57.
82. Ebong, I and P. Mazumder,
"Self-Controlled Writing and Erasing in a Memristor Crossbar Memory,"
IEEE
Transactions
on Nanotechnology, Vol.10, No.6, pp.1454-1463, Nov. 2011.
83. S.
Duan, X. Hu, L. Wang, C. Li, and P. Mazumder, “Memristor-Based RRAM with
Applications” Science China Information Sciences. 2012, 55(6):
1446–1460.
84.
S. Duan, X. Hu, L. Wang, and P. Mazumder, “Memristive Cellular
Neural/Nonlinear Network: Design, Analysis and Applications”, IEEE
Transactions on Neural Networks and Learning Systems, Vol. 26, No. 6,
July 2014, pp. 1202-1213.
85.
M. Erementchouk. P. Mazumder,
M. Khan and M. Leuenberger, “Weyl
Fermions in the Presence of Matrix Potential Barrier: Application to Graphene
and Topological Insulators,” Journal of Physics on Condensed Matter,
2016.
86. P. Mazumder, S. R. Li and I. Ebong,
“Tunneling Based Cellular Nonlinear Network Architectures for Image
Processing”, IEEE Transactions on VLSI, Vol. 17, No. 4, pp. 487-495, April
2009.
87. W. Wang, N. Gu, J.P. Sun, and P. Mazumder,
“Gate Current Modeling of High-K
Stack Nanoscale MOSFETs,” Solid-State Electronics, vol. 50,
pp. 1489-94, Oct. 2006.
88. S. H. Jo, T. Chang, I. Ebong, B. B. Bhadviya, P.
Mazumder and W. Lu, “Nanoscale Memristor Device as Synapse in Neuromorphic
Systems,” Nano Letters Journal, Vol. 10, No. 3, 5 pages, March 2010.
89. I. Ebong, and P. Mazumder, "Memristor based STDP Learning Network for Position Detection," Proceedings of the IEEE, Vol. 100, No. 6, pp. 2050—2060, June 2012.
90. P. Mazumder, S. Kang, and R. Waser, “Device, Model, and Applications of the Fourth circuit element,” Proceedings of the IEEE, June 2012.
91. P. Mazumder, D Hu, I. Ebong, X. Zhang, Z. Xu, and S. Ferrari, “Digital Implementation of a Spiking Neural Network Capable of Spike-Timing Dependent Plasticity,” Integration – VLSI Journal, Vol. 54, pp. 109-117, 2016.
92. N. Zheng and P. Mazumder, “An Efficient Eligible Error Locator Polynomial Searching Algorithm and Hardware Architecture for One-Pass Chase BCH Code Decoding,” IEEE Transactions on Circuits and Systems of Integrated Circuits II, to appear in 2016.
93. N. Zheng and P. Mazumder, “Hardware-Friendly Actor-Critic Reinforcement Learning Through Modulation of Spiking-Timing Dependent Plasticity,” IEEE Transactions on Computers, to appear in 2016.
NANOMAGNETIC MEMORY & SYSTEMS
94.
M. Barangi
and P. Mazumder, “Straintronics-based Random-Access Memory as Universal
Data Storage Devices,” IEEE Transactions on Magnetics, Vo. 51,
No. 5, May 2015.
95.
Y. Yilmaz and P. Mazumder,
“Nonvolatile Nanopipelining Logic Using Multiferroic Single-Domain
Nanomagnets,” IEEE Transactions on
Very Large Scale Integration (VLSI) Systems, Vol.21, No.7, pp.1181-1188,
July 2013.
96.
M. Barangi and P. Mazumder,
“Straintronics: A Leap Toward Ultimate Energy Efficiency of Magnetic
Random-Access Memories”, IEEE Nanotechnology Magazine, Vol.
9, No. 3, Sept. 2015, pp. 15-24.
97.
M. Barangi and P. Mazumder, “Straintronics-based
True Random Number Generator for High-Speed and Energy-Limited Applications,” IEEE Transactions on Magnetics, DOI 10.1109/ TMAG.
2015.2478398.
98.
M. Barangi and P. Mazumder, “Effect of Temperature Variations and Thermal Noise
on the Static and Dynamic Behavior of Straintronics Devices,” Applied Physics Letters, 2015.
99.
M. Barangi and P. Mazumder,
“Straintronics-Based Magnetic Tunneling Junction: Dynamic and Static Behavior
Analysis and Material Investigation,” Applied
Physics Letters, 2014.
100.
M. Barangi, M. Erementchoulk and P.
Mazumder, “Towards
developing a compact model for magnetization switching in straintronics
magnetic random access memory devices," Applied Physics
Letters, 2016.
TERAHERTZ TECHONOGY &
APPLICATIONS
101.
X. Zhao, K. Song and P. Mazumder, “Analysis of Doubly Corrugated
Spoof Surface Plasmon Polariton (DC-SSPP) THz Waveguiding Structure with
Narrow-band Transmission,” IEEE Transactions on Terahertz Science and Technology,
Vol. 1, May 2012, pp. 345-354.
102.
K. Song and P. Mazumder, “Nonlinear
Spoof Surface Plasmon Polariton Phenomena based on Conductor Metamaterials”, Photonics
and Nanostructures - Fundamentals and Applications, Volume 10, Issue 4,
October 2012, Pages 674–679.
103.
K. Song and P. Mazumder, “Design
of Highly Selective Metamaterials for Sensing Platforms,” IEEE Transactions on Sensors, Vol.
3, No. 9, pp. 3377-3385, 2013.
104.
M. Aghadjani and P. Mazumder, “Terahertz
Switch Based on Waveguide-Cavity-Waveguide Comprising Cylindrical Spoof Surface
Plasmon Polariton (C-SSPP),” IEEE
Transactions on Electron Devices, Vol. 62, No. 4, March 2015, pp. 1312-1318.
105.
K. Song and P. Mazumder, “One Dimensional Periodic Surface
Plasmon Photonic Crystal Slab (SPPCS) for a Nano-Photodiode”, IEEE Transactions on Nanotechnology, Vol. 9, No. 4, pp. 470-473, July 2010.
106.
K. Song and P. Mazumder, “Active Terahertz (THz) Spoof Surface Plasmon
Polariton (SSPP) Switch Comprising the Perfect Conductor
Meta-Material,” IEEE
Transactions on Electron Devices, Vol. 56, 2792-2799, 2009.
107.
K. Song and P. Mazumder, “Equivalent Circuit Modeling of
Non-Radiative
Surface Plasmon (SP) Energy Transfer along the Metallic Nanowire
(MNW)”, IEEE Transactions on Nanotechnology, Vol. 10, No. 1, pp. 111-120, January 2011.
108.
K. Song and P. Mazumder, “An Equivalent Circuit Modeling
of a Metallic Nanoparticle Plasmon Wire,” IEEE Transactions on Nanotechnology, Vol. 8, No. 3, pp. 412-418, May 2009.
109.
K. Song and P. Mazumder, “Dynamic
Terahertz Spoof Surface Plasmon Polariton Switch based on Resonance and
Absorption”, IEEE Transactions on Electron Devices, 58 (7), 2172-76, July 2011.
110.
Z. Xu and P. Mazumder, “THz Beam
Steering with Doped GaAs Phase Modulator and a Design of Spatial-Resolved
High-Speed THz Analog-to-Digital Convertor,” IEEE Transaction on Electron Devices, Vol. 61, No. 6, June 2014,
pp. 2195-2202.
111.
M. Aghadjani and P. Mazumder,
“THz Polarizer Controller based on Cylindrical Spoof Surface Plasmon Polariton
(C-SSPP),” IEEE Transaction on
Terahertz Science and Technology, Vol. 5, No. 4, July 2015, pp.
556-563.
112.
X. Zhao and P. Mazumder, “Bio-Sensing
by Mach-Zehnder Interferometer Comprising Doubly-Corrugated Spoofed Surface
Plasmon Polariton (DC-SSPP) Waveguide,” IEEE Transactions on Terahertz Science and
Technology, Vol. 2, July 2012, pp. 460-466.
113. Y. Yilmaz and P. Mazumder, “EM Based 1-bit Full Adder
Using Periodically Corrugated Metamaterial Structures,” IEEE Transactions on Nanotechnology (to
appear).
114. M. Aghadjani, M. Erementchouk and P.
Mazumder, “Spoof Surface Plasmon Polariton Beam Splitter,” IEEE Transaction on Terahertz Science and Technology, Oct. 2016.
115.
M. Erementchoulk, S. R. Joy, and P. Mazumder, “Electrodynamics
of Spoof Plasmons in Periodically Corrugated Waveguides,” Proceedings of Royal Society A,
Nov. 2016.
116.
J. Kim and P. Mazumder, “Novel Robust 12T SRAM Cell for
Improving Write Margin in Ultra-Low Power Applications,” Integration – VLSI Journal.
Journal Papers under Review
117. J. Kim, N. Zheng, Y. Yilmaz, and P. Mazumder, “A 2.4 GHz ISM-Band 6.1 µW 10-bit Wireless Sensor Node Chip Design for Ultra-low-voltage Bio-signal Sensing Applications with On/Off Keying Modulation in 65nm CMOS”, IEEE Trans. on Biomedical Engineering.
118. X. Guo, S. He. And P. Mazumder, “Comparative Study of Different Sense Amplifier Topologies with Monte Carlo Simulation,” Integration – VLSI Journal.
119.
N. Zheng and P.
Mazumder, “Modeling Static Noise Margin Variation in Subthreshold SRAM Cells,” IEEE
Transactions on Circuits and Systems.
120. N. Talati and P. Mazumder, “Resistive Memory Architectures and Programming Techniques,” Integration – VLSI Journal.
121. N. Zheng and P. Mazumder, “Baseband Processing Techniques for Low Power Wake-up Receiver,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
C. Book Chapters
122.
K. Shahookar and P. Mazumder, “Standard Cell Placement and the
Genetic Algorithm”, Book chapter in “Advances in Computer-Aided Engineering
Design, Vol. II”, I. N. Hajj (editor), Jai Press, Greenwich,
Connecticut, 1990, pp. 159-234.
123.
W. K. Fuchs, M. F. Chang, S. Y. Kuo, P. Mazumder and C. B.
Stunkel, “The Impact of Parallel Architecture Granularity on Yield”, Book
chapter in “Designing for Yield,” Moore, Strowjas and Maly (editors), Adam Hilger Publisher,
1988.
124.
P. Mazumder, “Design of a Fault-Tolerant DRAM with New On-Chip ECC”, Book Chapter
in “Defects and Fault Tolerance in VLSI Systems”, I. Koren (editor), Plenum
Press, 1989.
125.
H. Chan and P. Mazumder, “A Systolic Architecture for High-Speed
Hyper-graph Partitioning Using a Genetic Algorithm”, Book Chapter in “Progress
in Evolutionary Computation”, Vol. 956, Springer- Verlag,
Heildelberg, 1995, pp. 109-126.
D. Reviewed Archival Conference Publications
Generally these conferences have acceptance ratio between 15% and 35% and
they require rigorous review of full paper before the decision on a paper is
made. The conference publications are pertaining to work performed under
various sponsored research program as indicated below.
126.
P. Mazumder, J. H. Patel and W. K. Fuchs, “Design and Algorithms for Parallel
Testing of Random-Access and Content-Addressable Memory,” Proceedings
ACM/IEEE 24th Design Automation Conference, Florida, Jun. 1987,
pp. 688-694 (nominated for the Best Paper Award).
127.
P. Mazumder, “Evaluation of Three Interconnection Networks for CMOS VLSI
Implementation,” Proceedings IEEE International Conference on Parallel
Processing, St. Charles, Illinois, Aug. 1986, pp. 200-207.
128. P. Mazumder and J. H. Patel,
“Methodologies for Testing Embedded Content-Addressable Memories,” Proceedings
IEEE 17th International Symposium on Fault-Tolerant Computing, Jul.
1987, Pittsburgh, Pennsylvania, pp. 270-275.
129.
P. Mazumder, “A Novel Universal Seven-Segment-to-Decimal Decoder,” Proceedings
IEEE 6th Biennia University, Government and Industry Microelectronics (UGIM)
Conference, Alabama, Jun. 1985.
130.
P. Mazumder and J. H. Patel, “An Efficient Built-In Self-Testing Algorithm for
Random-Access Memory,” Proceedings IEEE International Test Conference,
Sep. 1987, pp. 1072-1077.
131.
P. Mazumder and J. H. Patel, “A Novel Fault-Tolerant Design of Testable Dynamic
Random-Access Memory,” Proceedings IEEE International Conference on
Computer Design, New York, Oct. 1987, pp. 306-309.
132.
P. Mazumder and J. Tartar, “Planar Topologies for Tree Representation,” Proceedings
14th Annual Conference on Numerical Mathematics and Computing Science,
Winnipeg, Canada, Sep. 1984.
133.
P. Mazumder “On-Chip Double-Error-Correction Coding Circuit for Three-Dimensional
DRAM’s,” Proceedings IEEE International Test Conference, Sep.
1988, Washington, pp. 279-288.
134.
P. Mazumder, “A New Strategy for Oct-tree Representation of Three-Dimensional
Objects,” Proceedings IEEE Conference on Computer Vision and Pattern
Recognition, Jun. 1988, Ann Arbor, pp. 270-275.
135.
P. Mazumder, “An Efficient Design of Embedded Memories for Random Pattern
Testability,” Proceedings IEEE International Conference on Wafer Scale
Integration, Jan. 1989, San Francisco, pp. 230-237.
136.
P. Mazumder and J. H. Patel, “Parallel Testing of Parametric Faults in DRAM”, Fifth
Conference on Advanced Research in Very Large Scale Systems, Massachusetts
Institute of Technology, 1988.
137.
P. Mazumder and J. Yih, “Fault-Diagnosis and Self-Repairing of Embedded Memories
by Using Electronic Neural Network,” Proceedings IEEE 19th Fault-Tolerant
Computing Symposium, Chicago, Jun. 1989, pp. 270-277.
138.
J. Yih and P. Mazumder, “A Neural Network Design for Circuit
Partitioning,” Proceedings ACM/IEEE 26th Design-Automation
Conference, Las Vegas, Jun. 1989, pp. 406-411.
139.
R. Venkateswaran and P. Mazumder, “Hexagonal Array Machine for
Multi-Layer Wire Routing,” Proceedings IEEE International Conference on
Computer-Aided Design, Nov. 1989.
140.
K. Shahookar and P. Mazumder, “A Genetic Approach to Standard
Cell Placement with Meta-Genetic Parameter Optimization,” Proceedings
IEEE European Design Automation Conference, Glasgow, England,
Mar. 1990, pp. 370-378.
141.
R. B. Panwar and P. Mazumder, “A Parallel Karmarkar Algorithm
Implemented on Orthogonal Tree Networks,” Proceedings International
Parallel Processing Conference, Aug. 1990, Vol. 3., pp. 270-273.
142.
P. Mazumder and J. Yih, “Built-In Self-Repair Techniques for Yield Enhancement of
Embedded Memories,” Proceedings IEEE International Test Conference,
Sep. 1990, pp. 833-841.
143.
S. Mohan and P. Mazumder, “Wolverine: A Distributed Standard
Cell Placement Tool,” Proceedings IEEE European Design Automation Conference,
Hamburg, Germany, Sep. 1992.
144.
R. Venkateswaran, P. Mazumder and K. G. Shin, “On Restructuring
of Hexagonal Processor Arrays,” IEEE Intl. Conf. on Defect
and Fault Tolerance in VLSI Systems, Pittsburgh, Nov. 1991.
145.
P. Mazumder and J. Yih, “Processor Array Self-Reconfiguration by Neural Networks,”
IEEE Intl. Wafer Scale Integration, Jan.
1992.
146.
S. Mohan and P. Mazumder, “Fault Characterization and Testing of
GaAs Static Random-Access Memories using High-Electron Mobility Transistors,” Proceedings
on IEEE International Test Conference, Nashville, Oct.
1991, pp. 665-674.
147.
K. Shahookar, P. Mazumder and S. M. Reddy, “Gate Matrix
Placement by Genetic Algorithm Combined with Beam Search,” Proceedings on
IEEE International VLSI Conference, Jan. 1993.
148.
P. Mazumder, “An Integrated Built-in Self-Testing and Self-Repair of Hexagonal
Arrays,” Proceedings On IEEE International Test Conference, Baltimore,
Sep. 1992.
149.
W.L. Chen, G.I. Haddad, G.O. Munns, S. Mohan and P. Mazumder,
“InP-Based Quantum Effect Devices: Device Fabrication and Application in
Digital Circuits,” Proceedings on International Electron Device and
Material Symposium, Taipei, Taiwan, Nov. 1992.
150.
K. Shahookar and P. Mazumder, “Genetic Min-cut Partitioning,” Proceedings
on IEEE International VLSI Conference, New Delhi, India, 1995.
151.
H. Esbensen and P. Mazumder, “SAGA: Unification of Genetic
Algorithm with Simulated Annealing and Its Application to Macro-Cell
Placement,” Proceedings on IEEE International VLSI Conference,
Calcutta, India, Jan. 1994.
152.
H. Esbensen and P. Mazumder, “A Genetic Algorithm for the
Steiner Routing Problem in a Graph,” Proceedings on European Design
Automation Conference, Paris, Mar. 1994.
153.
E. Chan, S. Mohan, P. Mazumder and G. I. Haddad, “Multi-valued
Multiplexer Design Using Resonant Tunneling Devices and Heterojunction Bipolar
Transistors,” Proceedings on Government Microcircuits Application
Conference, San Diego, Nov. 1994.
154.
S. Mohan, P. Mazumder and G. I. Haddad, “NDR SPICE: A Circuit
Simulator for Resonant Tunneling Devices,” Proceedings on IEEE
International Compound Semiconductors Conference, San Diego,
Sep. 1994.
155.
M.D. Smith and P. Mazumder, “Analysis and Design of
Hopfield-type Network for Built-in Self-repair of Memories,” Proceedings
on Government Microcircuit Application Conference, San Diego,
Nov. 1994.
156.
E. Chan, P. Mazumder and G.I. Haddad, “Mask Programmable
Multi-Valued Logic Gate Arrays Using RTD’s and HBT’s,” Proceedings on
Government Microcircuit Applications Conference, Orlando, Mar.
1996.
157.
S. Mohan, P. Mazumder and G. I. Haddad, “A New Circuit Simulator
for Negative Resistance Devices,” Proceedings on IEEE Intl. Electron
Devices Meeting, Dec. 1994.
158.
H. Chan and P. Mazumder, “Genetic Algorithms and Graph
Partitioning,” Proceedings on AAAI Conference, Sydney, Australia,
Nov. 1994.
159.
P. Mazumder, K. Saluja and M. Franklin, “Technology Testing of DRAM’s,” Proceedings
on IEEE Memory Testing Symposium, San Jose, Aug. 1995.
160.
S. Kulkarni, P. Mazumder and G.I. Haddad, “31-bit Parallel
Correlators Using RTD’s and HBT’s,” Proceedings on IEEE
Nanoelectronic and Micro-mechanics Conference, Houston, Nov.
1995.
161.
S. Kulkarni, P. Mazumder and G.I. Haddad, “An FPGA
Implementation of a 31-bit Correlators Design,” Proceedings on IEEE
International VLSI 1996 Conference, Jan. 1996.
162.
K. Chakraborty and P. Mazumder, “An Efficient, Bus-layout Based
Method for Early Diagnosis of Bussed Driver Shorts in Printed Circuit Boards,” Proceedings
on International Conference on Computer-Aided Design, Santa
Clara, Nov. 1996.
163.
A. Gonzalez and P. Mazumder, “High-speed Signed-digit Adder
Using RTD’s and MOSFET’s,” Proceedings on Government Microcircuits
Applications Conference, Las Vegas, Mar. 1997.
164.
G.I. Haddad and P. Mazumder, “Resonant Tunneling Devices and
Their Applications,” Proceedings on IEEE Symposium of Heterostructure
Devices, Sapporo, Japan, Aug. 1996. (Invited)
165.
P. Mazumder, “Multi-valued Logic Design Using HBT’s and RTD’s,” Proceedings
on Frontiers in Electronics, Tenerife, Spain, Jan. 1997. (Invited).
166.
K. Chakraborty and P. Mazumder, “Efficient Marching Algorithms
for Testing Multi-port Memories at the Board Level,” Proceedings on IEEE
European Design and Test Conference, Mar. 1997, Paris, France.
167.
P. Mazumder, “Parallel VLSI-Routing Models for Polymorphic Processors Array
(embedded tutorial),” Proceedings on IEEE International VLSI Conference,
Hyderabad, India, Jan. 1997.
168.
P. Mazumder, “Ultra-fast Circuits and Systems Using Quantum Devices,” Proceedings
on Frontiers in Electronics, Tenerife, Spain, Jan. 1997. (Invited)
169.
P. Mazumder and G.I. Haddad, “Digital Applications of NDR Devices” Proceedings
on IEEE Advanced Heterostructure Devices, Kona, Hawaii, Dec.
1996. (Invited)
170.
P. Mazumder, “Genetic Algorithms for Standard and Macro-cell Placement”
Proceedings on INFORMS, San Diego, May 1997. (Invited).
171.
P. Mazumder, “Ultra-fast Circuit Design Using Quantum Electronic Devices,” Proceedings
On European Circuit Theory and Design Conference, Budapest,
Hungary, Aug. 1997. (Invited)
172.
A. Gonzalez and P. Mazumder, “Multi-valued Signed Digit Adder
Using RTD and CMOS,” Proceedings On Advanced Research in VLSI Conference,
Ann Arbor, Sep. 1997.
173.
P. Mazumder, M. Bhattacharya, S. Kulkarni, and A. Gonzalez, “Design and Simulation
of Resonant Tunneling Diode Circuits,” Proceedings on IEEE International
VLSI Conference, Chennai, India, Jan. 1998.
174.
S. Kulkarni and P. Mazumder, “Full Adder Circuit Design Using
RTD’s and MOSFET’s,” Proceedings On Govt. Microcircuit Applications
Conference, Arlington, Mar. 1998.
175.
P. Mazumder, “Quantum Electronic Circuit Design,” Proc on Quantum Functional
Devices, Washington D.C., Nov. 1997. (Invited)
176.
P. Mazumder, “Testing and Testable Design of SRAM’s and DRAM’s,” Proceedings
on Intel Test Symposium, Santa Clara, Mar. 1997. (Invited)
177.
P. Mazumder and A. Seabaugh, “Quantum Electronic Devices: Principles, fabrication
and Applications,” Government Microcircuit Applications Conference,
Arlington, Washington D.C., Mar. 1998. (Invited)
178.
M. Bhattacharya and P. Mazumder, “Noise Margin of Threshold
Logic Gates for Resonant Tunneling Diodes,” Proceedings on IEEE 8th Great
Lakes Symposium on VLSI, Lafayette, Feb. 1998.
179.
P. Mazumder, “Built-in self-repair of VLSI Chips Using Neural-type Adaptive
Circuits,” Proceedings on SPIE (Application of Neural Networks, Fuzzy
Systems, and Evolutionary Computations in Electronic CAD), July 1998. (Invited)
180.
P. Mazumder, “Failure Modes in Deep Sub-micron CMOS Memories, “ Proceedings
on IEEE VLSI Test Symposium, Monterey, Mar. 1998 (Invited).
181.
K. Chakraborty, A. Gupta, M. Bhattacharya, S. Kulkarni, and P.
Mazumder, ”A Physical Design Tool for Built-In Self-Repairable Static
RAM’s,” Proceedings of IEEE Design and Test Automation in Europe,
Munich, Germany, 1999.
182.
A. Gupta, K. Chakraborty and P. Mazumder, ‘ FTROM: A Silicon
Compiler for Fault-Tolerant ROMs,’ Proceedings of IEEE International
Symposium on Defects and Fault Tolerance, Austin, 1998.
183.
N. Deb, J. Xiong, M. Bhattacharya, S. Kulkarni, and P. Mazumder,
”Switching Speed and Power Consumption of Bistable Q-MOS circuits,” in Third
IEEE Silicon Nanoelectronics Symposium, Hawaii, June 1998.
184.
C. H. Lin, K. Yang, A. F. Gonzalez, J. R. East, P. Mazumder, and
G. I. Haddad, ”InP-Based High Speed Digital Logic Gates Using an RTD/HBT
Structure,” in International Conference on Indium Phosphide and Related
Materials, Lausane, Switzerland, 1999.
185.
T. Ueymura and P. Mazumder, ”Analysis and Simulation of Sense
Amplifier Using RTD’s,” Proceedings On IEEE 9th Great Lakes Symposium on
VLSI, Ann Arbor, 1999.
186.
C. H. Lin, K. Yang, M. Bhattacharya, S. Wang, X. Zhang, J. R. East, P.
Mazumder, and G. I. Haddad,
”Monolithically Integrated InP-based Minority Logic Gate using an
RTD/HBT Heterostructure,” Proceedings on International Conference on InP
and Related Materials, Tsukuba, Japan, 1998.
187.
S. Kulkarni and P. Mazumder, ”Prospects for Quantum MOS Digital
Logic,” in Proceedings on European Conference on Circuit Theory and
Design, 1999. (Invited)
188.
S. Kulkarni and P. Mazumder, ”Full Adder circuit Design Using
RTD’s and MOSFET’s,” Proceedings On Government Microcircuits Applications
Conference, Washington D.C., 1998.
189.
P. Mazumder, M. Bhattacharya, S. Kulkarni, and A. Gonzalez, ”Design and Simulation
of Resonant Tunneling Diode Circuits,” Proceedings on IEEE International
VLSI Conference, 1998, India.
190.
P. Fay, G.H. Bernstein, D. Chow, J. Schulman, P. Mazumder, W.
Willamson and B. Gilbert, ”Integration of InAs/AlSb/GaSb Resonant Interband
Tunneling Diodes with Heterostructure Field-Effect Transistors for
Ultra-High-Speed Digital Circuit Applications,” Proceedings on IEEE 9th
Great Lakes Symposium on VLSI, Ann Arbor, 1999.
191.
P. Mazumder and M. Bhattacharya, ”Quantum Spice Simulator Design,” in Proceedings
on European Conference on Circuit Theory and Design, 1999 (Invited).
192.
A. Gonzalez and P. Mazumder, ”Multi-valued Signed Digit Adder
Using Quantum Electronic Devices”, Proceedings on Advanced Research on
VLSI Conference, Sept. 1997, Ann Arbor, pp. 96-113.
193.
A. F. Gonzalez, M. Bhattacharya, C. H. Lin, P. Mazumder, J. R.
East, and G. I. Haddad, “High-Speed Digital Circuits Using Resonant-Tunneling
Diodes and Heterojunction Bipolar Transistors,” Proceedings of the
Government Microcircuit Applications Conference, March 2000.
194.
M. Bhattacharya, S. Kulkarni, A. F. Gonzalez, and P. Mazumder,
“A Prototyping Technique for Large-Scale RTD-CMOS Circuits,” Proceedings
of the International Symposium on Circuits and Systems, Geneva,
Switzerland, May 2000.
195.
A. F. Gonzalez, M. Bhattacharya, S. Kulkarni, and P. Mazumder,
“Standard CMOS Implementation of a Multiple-Valued Logic Signed-Digit Adder
Based on Negative Differential-Resistance Devices,” 30th IEEE
International Symposium on Multiple-Valued Logic, May 2000.
196.
Q.W. Xu and P. Mazumder, “Modeling of Lossy Multiconductor
Transmission Lines by Modified Method of Characteristics,” IEEE
International VLSI Conference, Bangalore, India, 2001, pp. 359-364.
197.
M. Bhattacharya, P. Mazumder, and R. J. Lomax, ”FDTLM
Electromagnetic Field Simulation of High-Speed III-V HBT Digital Logic Gates,” IEEE
International VLSI Conference, Bangalore, India, 2001, pp. 470-474.
198.
Q.W. Xu, P. Mazumder, et al., “Modeling of Lossy Multiconductor
Transmission Lines by Differential Quadrature Method,” IEEE International
VLSI Conference, Bangalore, India, 2001, pp. 327-332.
199.
S. Kulkarni, M. Bhattacharya, A. Gonzalez, and P. Mazumder,
”250-MHz, 32-Bit Quantum MOS Correlators Prototype”, Proceedings on IEEE
International Conference on Circuits and Systems, Sept. 2001,
pp. 1501-1504.
200.
Lin, C. H., Yang K., A. Gonzalez, J. East, P. Mazumder, G.
Haddad, D. Chow, L.Warren, J. Roth, and S. Thomas, ”Fabrication and
Characterization of RTD-HBT Inverter”, High-Performance Devices, 2000
IEEE Cornell Conference, Aug. 2000.
201.
S. Kulkarni and P. Mazumder, ”Edge Triggered Flip-Flop Circuit
Based on Resonant-Tunneling Diodes and MOSFET’s,” European Conference on
Circuits: Theory and Design, Aug. 2001. (Invited)
202.
L. Ding, P. Mazumder and N. Srinivas, “A Low Power Dual-line
Static Edge Triggered Flip-flop,” Proceedings of the IEEE International
Symposium on Circuits and Systems, Sydney, May 2001, pp. 645-648.
203.
Q.W. Xu and P. Mazumder, “Efficient and Passive Modeling of
Transmission Lines by Differential Quadrature Method,” Proceedings of the
IEEE Design, Automation and Test in Europe, March 26-29, 2001,
pp. 437-444.
204.
Q.W. Xu, L. Ding and P. Mazumder, “Efficient Macro-modeling for
On-Chip Interconnect Loads,” IEEE International VLSI Conference,
Jan. 2002, pp. 561-566.
205.
P. Fay, P. Mazumder, et al., “A Flip-Flop Based on Monolithic
Integration of InAs/AlSb/GaSb RITD’s and InAlAs/InGaAs/InP HEMTs,” Proceedings
on IEEE Device Research Conference, June 2001.
206.
Q.W. Xu and P. Mazumder, “Low-Order Pole/Zero Modeling for
Estimation of RC Delays of On-Chip Interconnects,” Proceedings on IEEE
Design, Automation and Test in Europe, Paris, Mar. 2002, pp. 820-825.
207.
L. Ding and P. Mazumder, ”On Optimal Tapering of FET Chains in
High-Speed CMOS Circuits”, Proceedings on IEEE Design, Automation and
Test in Europe, Paris, Mar. 2002, pp. 708-713.
208.
Q.W. Xu and P. Mazumder, “Rational ABCD matrix of high-speed
interconnect using differential quadrature method,” Proceedings on
IEEE VLSI Conference, Jan. 2002, pp. 147-152.
209.
L. Ding, P. Mazumder and D. Blaauw, ”Crosstalk Noise Estimation
Using Effective Coupling Capacitance,” Proceedings on IEEE International
Symposium on Circuits and Systems, 2002.
210.
L. Ding and P. Mazumder, ”A New Modeling Technique for
Simultaneous Switching Noises”, Proceedings on IEEE International
Symposium on Circuits and Systems, Mar. 2002, pp. 1038-43.
211.
Q. W. Xu and P. Mazumder, “Novel Interconnect Modeling by Using
High-order Compact Finite Difference Methods,” Proceedings on IEEE Great
Lakes VLSI Conference, Apr. 2002.
212.
T. Ueymura, and P. Mazumder,
“Rise Time Analysis of RTD Based Mono-stable to Bi-stable Transition Circuits,”
Proceedings on IEEE International Symposium on Circuits and
Systems, May 2002.
213.
Q.W. Xu and P. Mazumder, “Novel Macro-modeling for On-Chip
RC/RLC Interconnects,” Proceedings on IEEE International Symposium
on Circuits and Systems, May 2002.
214.
L. Ding and P. Mazumder, ”A Simplified MOSFET Model for
Analyzing DSM Circuits,” Proceedings on IEEE International
Symposium on Circuits and Systems, May 2002.
215.
L. Ding, P. Mazumder and D. Blaauw, ”Accurate Estimation of
Crosstalk Using Effective Coupling Capacitance,” Proceedings on IEEE
International Conference on Computer-Aided Design, Nov. 2002.
216.
A. F. Gonzalez and P. Mazumder, “Comparative Study of Bistable
Logic Circuits built with Resonant-Tunneling Diodes,” Proceedings on International
IEEE VLSI Conference, 2003.
217.
L. Ding and P. Mazumder, ”The Impact of Bit-line Coupling and
Ground Bounce on CMOS SRAM” Proceedings on IEEE VLSI Conference,
2003.
218.
Q.W. Xu and P. Mazumder, “Efficient Interconnect Modeling by
Finite Difference Quadrature Methods,” Proceedings on IEEE
International Symposium on Circuits and Systems, May 2003.
219.
H. Zhang, P. Mazumder, L. Ding, and K. Yang, “Analysis and
Simulation of Tunneling SRAM,” Proceedings on IEEE International
Symposium on Circuits and Systems, May 2003.
220.
B. Wang and P. Mazumder, “Novel Subgridding Method for Improving
Speed of Full Chip Simulation,” Proceedings on IEEE International
Symposium on Circuits and Systems, May 2003.
221.
Q. Xu and P. Mazumder, “Modeling of Transmission Lines with EM
Wave Coupling by Finite Difference Quadrature Methods,” Proceedings of
the European Circuit Conference: Theory and Design, Krakow, Poland,
2003.
222.
L. Ding and P. Mazumder, “Noise-Tolerant Quantum MOS Circuits
Using Resonant Tunneling Devices,” Proceedings of the European Circuit
Conference: Theory and Design, Krakow, Poland, 2003.
223.
L. Ding and P. Mazumder, “Modeling Cell Noise Transfer
Characteristic for Dynamic Noise Analysis,” Proceedings on IEEE Design Automation and Testing
Conference in Europe (DATE),
May 2003.
224.
L. Ding and P. Mazumder, “Dynamic Noise Margin: Definitions and
Model,” Proceedings on IEEE
International Conference on VLSI Design, pp. 1001-1006, Jan.2004.
225.
Q. Xu and P. Mazumder, “Modeling of Transmission Lines with EM
Wave Noises,” Proceedings on IEEE/ACM
Great Lakes Symposium on VLSI, Boston, 2004.
226.
L. Ding and P. Mazumder, “A Novel Technique to Improve Noise
Tolerance of Dynamic Logic Circuits,” Proceedings on IEEE/ACM Design Automation Conference, San
Diego, June 2004.
227.
H. Zhang, P. Mazumder and K. Young, “Resonant Tunneling Diode
Based QMOS Edge Triggered Flip-Flop Design,” Proceedings on IEEE
International Symposium on Circuits and Systems, Vancouver, 2004.
228.
S. R. Li, P. Mazumder, and L. O. Chua, “On the Implementation of
RTD-based Cellular Neural Network,” Proceedings on IEEE International
Symposium on Circuits and Systems, Vancouver, 2004.
229.
P. Mazumder, “Design of
Mesoscopic and Nanoscale Cellular Nonlinear Networks Using RTD’s,” Proceedings
on IEEE International Conference on Cellular Neural Networks, Budapest,
Hungary, July 2004. (Invited)
230.
B. Wang and P. Mazumder, “Fast Thermal Analysis for VLSI
Circuits via Semi Analytical Green’s Functions in Multi-layer 3-D Integrated
Circuits,” Proceedings on IEEE International Symposium on Circuits
and Systems, Vancouver, 2004.
231.
B. Wang and P. Mazumder, “On
Optimality of Adiabatic Switching in MOS Energy-Recovery Circuit,” IEEE International Symposium on Low Power Design,
July 2004, pp. 236-239.
232.
P. Mazumder and B. Wang, “Effects of High-Power EM Pulses on Digital Integrated
Circuits”, Proceedings on IEEE AP-S International Symposium and USNC/URSI
National Radio Science Meeting, Monterey, June 2004. (Invited).
233.
H. Zhang, P. Mazumder, and K. Young, “Multi-valued Address
Stretchable Decoder Design for Giga-bit Random-Access Memories,” Proceedings
on IEEE Conference on Nanotechnology, 2004.
234.
S. R. Li, and P. Mazumder, “Compact Cellular Neural/Nonlinear Networks Based on
Resonant Tunneling Diode,” Proceedings on IEEE Conference on Nanotechnology,
August 2004, pp. 164-167.
235. L. Ding and P. Mazumder, "A Novel Application of Resonant Tunneling Devices in High Performance Digital Circuits," Proceedings of IEEE Conference on Nanotechnology (NANO-03), Aug. 2003.
236. Q. Xu and P. Mazumder, "Efficient Modeling of transmission lines by the Finite Difference Quadrature Method," Proceedings of IEEE International Symposium on Circuits and Systems, May 2003.
237. L. Ding and P. Mazumder, "The Impact of Bit-line Coupling and Ground Bounce on CMOS SRAM Performance," Proceedings of IEEE International Conference on VLSI Design, Jan. 2003.
238. L. Ding and P. Mazumder, "Modeling Cell Noise Transfer Characteristic for Dynamic Noise Analysis," Proceedings of IEEE Design Automation and Test Conference in Europe (DATE), March 2003.
239.
H. Zhang; P. Mazumder; L.Ding; and K. Yang, “Performance modeling of resonant tunneling based RAMs,”
Proceedings of the IEEE International Symposium on Circuits and Systems,
Bangkok May 2003.
240. L. Ding and P. Mazumder, "Improving Dynamic CMOS Circuit Noise Tolerance Using Resonant Tunneling Devices," Proceedings of European Conference on Circuit Theory and Design, Sept. 2003
241. Q. Xu and P. Mazumder, "Modeling of transmission lines with EM wave coupling by the Finite Difference Quadrature Method," Proceedings of IEEE International Symposium on Circuits and Systems, May 2003
242. A. Gonzalez and P. Mazumder, “Comparison between Bistable and MOBILE RTD based Circuits,” Proceedings on IEEE International Conference on VLSI Design, Jan. 2003.
243. B. Wang and P. Mazumder, “Novel Subgridding Method for Improving Speed of Full Chip Simulation,” Proceedings on IEEE International Symposium on Circuits and Systems, May 2003.
244. Q. W. Xu and P. Mazumder, “Modeling of Transmission Lines with EM Wave Coupling by Finite Difference Quadrature Methods", Proceedings of European Conference on Circuits: Theory and Design, Sept. 2003.
245. L. Ding and P. Mazumder, "Dynamic Noise Margin: Definitions and Model," Proceedings of IEEE International Conference on VLSI Design, pp. 1001-1006, Jan. 2004.
246. Q. Xu, and P. Mazumder, "Modeling of transmission lines with EM wave noises," Proceedings of Great Lakes Symposium on VLSI, April 2004.
247. H. Zhang; P. Mazumder, and K.Yang; “Resonant Tunneling Diode Based QMOS Edge Triggered Flip-Flop Design,” Proceedings of IEEE International Symposium on Circuits and Systems, May 2004.
248. S.R. Li, P. Mazumder and L.O Chua, "On the Implementation of RTD-based Cellular Nonlinear Network", Proceedings of IEEE International Symposium on Circuits and Systems, May 2004.
249. B. Wang and P. Mazumder, “Multivariate Normal Based Statistical Timing Analysis Using Global Projection and Local Expansion,” Proceedings of IEEE International Conference on VLSI Design, Jan. 2005, pp. 380-385.
250. H. Zhang and Mazumder, P, “Design of a New Sense Amplifier Flip-flop with Improved Power-Delay-Product” Proceedings of IEEE International Symposium on Circuits and Systems, May 2005, pp. 1262-1265.
251. B. Wang and P. Mazumder, “EM Wave Coupling Noise Modeling Based on Chebyshev Approximation and Exact Moment Formulation,” Proceedings of IEEE Design Automation and Test Conference in Europe (DATE), March 2005, pp. 976-981.
252. S.R. Li, P. Mazumder and K. Yang, “On the Functional Failure and Switching Time Analysis of MOBILE Circuitry,” Proceedings of IEEE International Symposium on Circuits and Systems, May 2005, pp 2531 - 2534.
253. B. Wang and P. Mazumder, “Integrating Lumped Networks into Full Wave TLM/FDTD Methods Using Passive Discrete Circuit Models.” Proceedings of IEEE International Symposium on Circuits and Systems, May 2005, pp. 1948-1951.
254. B. Wang and P. Mazumder,
“A logarithmic complexity algorithm for full chip thermal analysis using
multi-layer Green’s function,” Proceedings of Design, Automation and Test
in Europe (DATE), Mar. 2006.
255. B. Wang and P. Mazumder,
“Optimization of Circuit Trajectories: an Auxiliary Network Approach,” Proceedings
of the 11th
Asia
and South Pacific Design Automation Conference (ASP-DAC), Jan.
2006, pp.416-421.
256. B. Wang and P. Mazumder,
“Bounding Power Supply Noise Induced Path Delay Variation by a Relaxation
Approach,” Proceedings of the 19th International Conference on
VLSI Design, Jan. 2006, pp.349-354.
257. W. H. Lee and Mazumder, P.,
“New Logic Circuits Consisting of
Quantum Dots and CMOS,” Proceedings of the 2005 European
Conference on Circuit Theory and Design, 2005. Volume 2, 28 Aug.-2
Sept. 2005 pp.135 -138.
258.
W. H. Lee and Mazumder, P.,“A New Velocity Tuned Filter
Using Nanoelectronic Architecture,” Proceedings on IEEE Conference on
Nanotechnology, Cincinnati, July 2006.
259.
P. Mazumder, “Application of Quantum Dots in Nanoelectronics and
Plasmonics,”
Proceedings on IEEE Conference on Nanotechnology, Cincinnati,
July 2006.
260.
P. Mazumder, “Mesoscopic and Nanoscale Quantum Tunneling Based Systems,” Government Microcircuit
Applications Conference, Orlando, Florida., 2007.
261.
W. H. Lee and Mazumder, P., “Parallel
Processing Based Power Reduction in a 256 State Viterbi Decoder,” Proceedings
of IEEE 17th
International Conference on Application-specific Systems, Architectures and
Processors (ASAP'06), 2006, pp. 182-185.
262.
P. Mazumder, “Biologically Inspired Algorithms for Micro and Nanoelectronics
Design,” Proceedings of the Biologically Inspired Computing – Theory and
Applications, Zheng Zhou, China, Sept. 2007.
263.
K. Song and P. Mazumder, “Surface Plasmon Dynamics of a Metallic
Nanoparticle,” Proceedings on IEEE Conference on Nanotechnology, Hong Kong,
Aug. 2007.
264.
W.H. Lee and Mazumder, P.,“Color Extraction and Shift
with Quantum Dot Array,” Proceedings on IEEE Conference on Nanotechnology, Hong Kong,
Aug. 2007.
265.
P. Mazumder, “Quantum Tunneling Based Systems,” High Performance Computing
– HPC Nano, Reno, Nov. 2007.
266.
K. Song and P. Mazumder,
“Modeling of Metallic Nano Particles for SPICE-Compatible Equivalent Circuit,” Proceedings
of Nanoelectronic Devices for Defense and Security Conference, Crystal
City, June 2007.
267.
P. Mazumder, “Emerging Technologies for Information and Signal Processing,” Proceedings
of the VLSI Conference, Hyderabad, Jan. 2008.
268.
K. Song and P. Mazumder, “The Guiding Mechanism of Nonradiative
Surface Plasmon (SP) Energy Transfer along the Metallic Nanowire,” Proceedings on IEEE Conference on
Nanotechnology, Dallas, Aug. 2008.
269.
W. Wang, N. Gu,
J.P. Sun, and P. Mazumder,, “Modeling of High-k Gate Stack of Tunnel Barrier in
Nonvolatile Memory MOS Structure”, Proceedings on IEEE Conference on Nanotechnology,
Dallas, Aug. 2008.
270. K. Song and P. Mazumder,
“Active Tera Hertz
(THz) Spoof Surface Plasmon Polariton (SSPP) Switch Comprising the
Perfect Conductor Meta-Material,” Proceedings on IEEE Conference on Nantechonolog, Genoa, Italy, Aug. 2009.
271.
K. Song and P. Mazumder,
“THz Dynamic Switch Design using Spoof Surface Plasmon Polariton,” Proceedings
of Nanoelectronics Devices for Defense and Security Conference, Fort
Lauderdale, Sept. 2009.
272.
B. Wang and P. Mazumder, “An Accurate
Interconnect Thermal Model using Equivalent Transmission Line Circuit,” Proceedings on Design Automation and Test
Engineering, Nice, France, April 2009.
273.
P. Mazumder, “Disruptive Technologies and Neuromorphic
Architectures,” Proceedings on GLS-VLSI Conference,
Mar. 2009. (Invited)
274.
I.
Ebong, and P. Mazumder, "Memristor based STDP Learning Network for
Position Detection," 2010
International Conference on Microelectronics (ICM), Cairo, Egypt, pp.
292-295, Dec. 2010.
275.
P. Mazumder,
“Disruptive Technologies and Neuromorphic Architectures,” Proceedings on CMOS Emerging Technologies Conference, Whistler,
Canada, June 2009.
276.
I. Ebong, D. Deshpande, Y. Yilmaz, and P.
Mazumder, "Multi-purpose Neuroarchitecture with Memristors," Proceedings on IEEE Conference
on Nanotechnology, Aug 2011.
277.
K. Song and P.Mazumder, “Spoof Surface
Plasmon Polariton Devices for GHz ~ THz System”, Proceedings on IEEE Conference on Nanotechnology, Aug 2011.
278.
Y. Yilmaz and P. Mazumder, “Nanopipelining
of NML Using Multiferroic Single-Domain Nanomagnets”, Proceedings on IEEE Conference on Nanotechnology, Aug 2011.
279.
I. Ebong and P. Mazumder, “Adaptive
Reading, Writing and Erasing in a Memristor Crossbar Memory,” Proceedings on Nano DDS Conference, New York, August 2011.
280.
X. Zhao, K. Song and P. Mazumder,
“Doubly Corrugated Spoof Surface Plasmon Polariton (DC-SSPP) Structure with
Frequency Selective transmission,” Proceedings
on Nano DDS Conference, New York, August 2011.
281.
Y. Yalcin and P. Mazumder,
“Multi-level Cell Design for Memristor Crossbar,” Proceedings on
International Symposium on Electronic System Design, Cochin, India,
Dec. 2011.
282.
H. Liu, Y. Yalcin and P. Mazumder, “Subthreshold
Asynchronous Circuits with Straintronics-Based Nonvolatile Latch in Ultra-Low
Energy Systems,” Proceedings on
Subthreshold Microelectronics Conference, MIT Lincoln Laboratory,
Boston, Sept. 2012.
283.
Y. Yalcin and P. Mazumder,
“Programmable Quantum-Dot and Memristor Based Architecture for Image
Processing,” Proceedings on IEEE Conference on Nanotechnology, Aug
2012.
284.
I. Ebong and P. Mazumder,
"Self-Healing Memory Array Design using Memristors," Proceedings
on IEEE Conference on Nanotechnology, Aug 2012.
285.
X. Zhao and P. Mazumder,
“Doubly-Corrugated Spoofed Surface Plasmon Polariton Mach- Zehnder
Interferometer (DC-SSPP MZI) Structure and Its Sensing Applications,”
Proceedings on IEEE Conference on Nanotechnology, Aug
2012.
286.
P. Mazumder, “Versatile Applications
of Memristors,” Proceedings on
International Symposium on Cellular
Neural Networks, Torino, Italy, August 2012 (Invited Plenary Talk).
287.
P. Mazumder, “Beyond Moore’s
Law Technologies and Architectures,” Proceedings
on International Symposium on
Electronic System Design, Kolkata, Dec. 2012 (Invited Banquet Talk).
288.
K. S. Chong, M. Barangi, J. Kim, J. S. Chang,
P. Mazumder, "Ultra Low-Power Filter Bank for Hearing Aid Speech
Processor", Proceedings on
IEEE Subthreshold Microelectronics
Conference, Boston, October, 2012.
289.
J. Kim, K. Chong, J. S. Chang,
and P. Mazumder, “A 250mV Sub-threshold Asynchronous 8051 Microcontroller with
a Novel 16T SRAM Cell for Improved Reliability in 40nm CMOS,” Proceedings on Great Lakes Symposium on VLSI, Paris, pp. 83-88, 2013.
290.
N. Zheng, M.
Aghadjani, K. Song and P. Mazumder,
“Metamaterial Sensor Platforms for Terahertz DNA Sensing,” Proceedings on IEEE
Conference on Nanotechnology, Beijing, China, pp. 315-320, 2013
291.
X. Zhao, and P.
Mazumder, “Spoofed Surface Plasmon Polariton (SSPP) Gap Structure for High
Sensitivity Bio-Sensing in THz,” Proceedings of IEEE Conference on Nanotechnology, Beijing, China.
292.
J.
Shah, M. Barangi, and P. Mazumder, “Memristor Crossbar Memory for Hybrid Ultra
Low Power Hearing Aid Speech Processor,” Proceedings of IEEE Conference on Nanotechnology, Beijing, China.
293.
N. Zheng, J. Kim and P.
Mazumder, “Low-Power Reconfigurable CMOS Power Amplifier for Wireless Sensor
Network Application”, IEEE International Symposium on Circuits and
Systems (ISCAS), Melbourne, Australia, June 2014.
294.
D. Hu, X.
Zhang, Z. Xu, S. Ferrari and P. Mazumder, “Digital Implementation of a Spiking
Neural Network (SNN) Capable of Spike-Timing-Dependent Plasticity (STDP) Learning,” IEEE Conference on Nanotechnology, Toronto, Canada, 2014.
295.
I. Ebong and P. Mazumder, “Iterative Architecture for
Value Iteration using Memristors,” IEEE
Conference on Nanotechnology, Toronto,
Canada, 2014
296.
Z. Xu, and P. Mazumder, “Spatial-Resolved High-Speed THz
Analog-to-Digital Convertor Comprising Phase Modulated Beam Steering
Architecture,” IEEE Conference on Nanotechnology, Toronto, Canada, 2014.
297.
A. Bhat, J. S. Chang and P. Mazumder, “Spin-Torque
Nano-Oscillator Based Correlator,” IEEE
Conference on Nanotechnology, Toronto, Canada,
2014.
298.
M. Aghadjani and P. Mazumder, “Dynamic Terahertz Switch
Based on Waveguide-Cavity-Waveguide (WCW) Structure” IEEE Conference on Nanotechnology, Toronto, Canada, 2014.
299.
Y. Yilmaz and P. Mazumder, “EM Based 1-bit Full Adder
Using Periodically Corrugated Metamaterial Structures,” IEEE Conference on Nanotechnology, Rome, Italy, 2015.
300.
M. Barangi, M. Aghadjani and P. Mazumder, “Design and Analysis of a Terahertz SSPP
Switch Using Piezoelectric Materials,” IEEE
Conference on Nanotechnology, Rome, Italy, 2015.
301.
M. Barangi and P. Mazumder, “Analysis, modeling, and
applications of the straintronics devices for the future spin-based integrated
circuits,” IEEE VLSI Conference, Kolkata, India, 2016.
302.
M. Barangi and P. Mazumder, “Modeling of temperature
dependency of magnetization in straintronics memory devices,” SISPAD,
Washington DC, Sept. 2015.
303.
M. Barangi, and P. Mazumder, “Analysis, modeling, and applications of the
straintronics devices for the future spin-based integrated circuits,” IEEE Conference on Nanotechnology, Shendai, Japan, 2016.
304.
M. Aghadjani, M. Erementchoulk, and P. Mazumder, “THz
Analog to Digital Converter Using Single Sided Spoof Surface Plasmon Polariton
Waveguide,” IEEE Conference on Nanotechnology, Shendai, Japan,
2016.
E. Workshop Presentations
305.
P. Mazumder,
“Neuromorphic Applications of Memristors,” Memristor Symposium, University of California at Berkeley, Feb 2010. (See the oral presentation in
YouTube at http://www.youtube.com/watch?v=h7cX_m5IKxk).
306.
P. Mazumder,“Memristor Based Circuit Design,” DARPA Defense Science
Research Conference, Santa Clara, May. 2009.
(Invited)
307.
P. Mazumder, “Beyond CMOS and Evolutionary Architectures,” Memristor Symposium, University
of California at Berkeley, Nov. 2008.
(Invited)
308.
P. Mazumder, “Plasmonics
for Digital Logic Design,” SRC-NRI
Meeting, South bend, August 2010.
309.
P. Mazumder,“Quantum circuits and CAD tools design ,” Proceedings on SRC
Nanoelectronics Symposium , Aug. 2005.
(Invited)
310.
P. Mazumder, “Quantum
Tunneling Based Nanoscale Memories,” A-STAR
Research Laboratories workshop, Singapore, Oct. 2009.
311.
P. Mazumder, “CAD Tools Design for Surface Plasmon Polariton Based Systems”, AFOSR
MURI Review, November 2007, Boston.
312.
P. Mazumder, ”Q-MOS Circuit Design Techniques and Future Prospects of Q-MOS,” SRC
Nanoelectronic Workshop, Dec. 1999. Raytheon-TI, Dallas, Apr. 1998. (Invited).
313.
P. Mazumder, “Visual Computing by Mesoscopic and Nanoscale Systems,” National
Nanoelectronics Initiative Workshop, Organized Jointly by NNCO, NSF,
ONR, AFOSR and DARPA, February 2004. (Invited)
314.
P. Mazumder, “Beyond Moore’s Law and CMOS Technology”, Technology Vision -- Mad
Scientist Conference, US Army, Norfolk, August 2008.
315.
P. Mazumder, “Plasmonics for Digital Logic Design,” SRC-NRI Meeting,
Southbend, June 2008.
316.
P. Mazumder, “Plasmonics based VLSI Interconnect Design” Air Force Office of Scientific
Research Review Meeting on Nanoelectronics, June 2008, Dayton.
317.
P. Mazumder, “Quantum Dot Based Cellular Image Processing: Theory and design,” IEEE
Workshop on Cellular Nonlinear Networks, July, Budapest, Hungary (Invited).
318.
P. Mazumder, “Design of a Fault-Tolerant DRAM with New On-Chip ECC,” IEEE
International Workshop on Defect and Fault Tolerance in VLSI Systems,
Oct. 1988, Springfield, Massachusetts.
319.
P. Mazumder, “A Test Methodology for Electronic Neural-Network Associative Memory,”
International Neural Network Society First Annual Meeting, Sep.
1988, Boston, Massachusetts.
320.
P. Mazumder, “Effects of HPEM and UWB Pulses on a System-on-a-Chip Digital
Circuits,” MURI Workshop on EM Effects on Electronic Circuits,
Chicago, November 2003.
321.
P. Mazumder, “Study of Signal integrity in VLSI Chips in Presence of High-Power
Electromagnetic Pulses, “MURI Workshop on EM Effects on Electronic
Circuits, Chicago, January 2003.
322.
P. Mazumder, “Hexagonal Mesh Architecture for Routing,” Office of Naval
Research Workshop, Washington, Nov. 1989.
323.
P. Mazumder, “Hexagonal Mesh Reconfiguration Algorithms,” Office of Naval
Research Workshop, Washington, Nov. 1990.
324.
P. Mazumder, “Ultra-fast Circuit Design with NDR Devices,” Advanced Research
Project Agency: Ultra Project, Santa Fe, Oct. 1993.
325.
P. Mazumder, “Ultra-fast Circuit Design with NDR Devices,” Advanced Research
Project Agency: Ultra Project, Santa Fe, Oct. 1994.
326.
P. Mazumder, “Built-in Self-repair using Electronic Neural Networks,” Advanced
Research Project Agency: Neural Network Project, San Diego, Nov.
1994.
327.
P. Mazumder, ”Ultra-fast Circuit Design with NDR Devices,” Defense Advanced
Research Project Agency, Estes Park, Colorado, 1998.
328.
P. Mazumder, ”Q-MOS Circuit Design,” Defense Advanced Research Project
Agency, Raytheon, Dallas, 1999.
329.
P. Mazumder, ”RTD Circuit Design,” Office of Naval Research, Ann
Arbor, 1998.
330.
P. Mazumder, ”Ultra-fast Circuit Design with NDR Devices,” Defense Advanced
Research Project Agency, Santa Fe, Oct. 1997.
331.
P. Mazumder, ”Q-MOS Circuit Design,” Defense Advanced Research Project
Agency, Raytheon-TI, Dallas, Apr. 1998.
332.
W. Wang, J. P. Sun, N. Gu, and P. Mazumder, “Gate Current Simulation of High-k Stack Nanoscale MOSFETs,”
IEEE
Computer Society Annual Symposium on VLSI, Brazil, 2007.
F. Technical Reports
333.
P. Mazumder and J. H. Patel, “Parallel Testing of Pattern-Sensitive Faults in
Random-Access Memory,” Technical Report CSG-56, Coordinated Science
Laboratory, Aug. 1986.
334.
P. Mazumder, “Networks and Embedding Aspects of Hyper-cellular Structures for
On-Chip Parallel Processing,” M. Sc. Thesis, Department of Computer Science,
University of Alberta, 1985.
335.
P. Mazumder and J. H. Patel, “Testable RAM Design,” SRC Corporate Research,
1986 Annual Report.
336.
P. Mazumder, “Testing and Fault-Tolerant Aspects of High-Density VLSI Memory,” Ph.D.
Thesis, Coordinated Science Laboratory, Aug. 1987.
337.
P. Mazumder “On-Chip Double-Error-Correction Coding Circuit for Three-Dimensional
DRAM’s,” CRL-TR-05-88, Technical Report, Department of Electrical
Engineering and Computer Science, University of Michigan, Ann Arbor, Apr.
1988.
338.
A. Chakravarthy and P. Mazumder, “Gate Matrix Layout Techniques,”
CSE-TR-12-90, Technical Report, Department of Electrical Engineering and
Computer Science, University of Michigan, Ann Arbor, 1990.
339.
R. Venkateswaran and P. Mazumder, “Hexagonal Array Machine for
Multi-Layer Wire Routing,” CSE-TR-52-90, Technical Report, Department of
Electrical Engineering and Computer Science, University of Michigan, Ann
Arbor, 1990.
340.
R. Venkateswaran and P. Mazumder, “On Restructuring of Hexagonal
Arrays,” CSE-TR-72-90, Technical Report, Department of Electrical
Engineering and Computer Science, University of Michigan, Ann Arbor, 1990.
341.
K. Shahookar and P. Mazumder, “VLSI Cell Placement Techniques,” CRL-TR-07-88,
Technical Report, Department of Electrical Engineering and Computer Science,
University of Michigan, Ann Arbor, Aug. 1988.
342.
P. Mazumder, “CPLA - A Software Tool That Automatically Generates ”C”-Model for
PLA’s,” Bell Laboratories Technical Memorandum, 55612-1A-262, Aug. 1985.
343.
P. Mazumder, “Placement Algorithms for CONES,” Bell Laboratories Technical
Memorandum, 55612-1F-210, Aug. 1986.
344.
P. Mazumder, “Automatic Integrated Circuit Synthesizer: Generates PLA Layout from
Behavioral Description Written in C Language,” Bell Laboratories Technical
Memorandum, 55612-1A-262, Aug. 1985.
Publications in Industry
(during 1976-1982)
Mixed Signal Analog and Digital VLSI Chip Design
Published over
fifteen technical papers and application ideas while working at the
Bharat Electronics Ltd. Topics included
All these articles were
published in BEL Application Notes and BEL Technical Report.
IX. Book Reviews
X. Patents and Inventions
1.
US Patent on Adaptive Reading and Writing of a
Resistive Memory, US Patent No. 9,111,613, awarded on Aug. 18, 2015,
(Inventors: P. Mazumder and E. Idong; Patent Assigned to Regents of University
of Michigan).
2. US Patent on High-Speed, Compact, Edge-Triggered
Flip-Flop Circuit Topologies Using NDR Diodes and FET’s, US Patent No.
6,323,709, awarded on Nov. 21, 2001, (Inventors: S. Kulkarni and P. Mazumder;
Patent Assigned to Regents of University of Michigan).
3. US and International Patents on Method and Apparatus
to Improve Noise Tolerance of Dynamic Circuits, US Patent No. 7,088,143,
awarded on Aug. 8, 2006, (Inventors: L. Ding and P. Mazumder; Patent Assigned
to Regents of University of Michigan).
4. US Patent on Digital Logic Design Using Negative
Differential Resistance Diodes and Field-Effect Transistors, US Patent No.
5903170, awarded on May 11, 1999, (Inventors: S. Kulkarni, P. Mazumder, G.
Haddad; Patent Assigned to Regents of University of Michigan).
5.
US Patent 8,842,948, issued on Sept. 23, 2014 on Dynamic Terahertz Switching Device Comprising
Sub-Wavelength Corrugated Waveguides and Cavity that Utilizes Resonance and
Absorption for Attaining On and Off States, (Inventors: P. Mazumder and K.
Song; Patent assigned to P. Mazumder).
6.
US Patent 8,837,036, issued on Sept. 16, 2014 on Dynamic Terahertz Switch Using Periodic Corrugated
Structures, (Inventors: P. Mazumder and K. Song; Patent assigned to P.
Mazumder).
7.
US Patent Provisional Application Filed on Memristor Crossbar
Memory for Hybrid Ultra Low Power Hearing Aid Speech Processor. (Inventors:
J. Shah, P. Mazumder and M. Barangi).
8.
US Patent Provisional Application (20150330838) Filed on Terahertz DNA Bio-Sensor Architecture
Having Doubly-Corrugated Spoofed Surface Plasmon Polariton Waveguide; (Inventors:
P. Mazumder, Z. Xu and K. Song).
9.
US Patent Provisional Application (20150323852)
Filed on
Terahertz Analog-to-Digital Converter Employing Active-Controlled Spoofed
Surface Plasmon Polariton Architecture; (Inventors: P.
Mazumder and Z. Xu).
10. US Patent Application (20160025625)
on Metamaterial
Sensors Platform for Terahertz Sensing, (Inventors: Z. Nan, K. Song, A. Mahdi
and P. Mazumder).
11. US
Patent on Static Random Access Memory Cell having Improved Write Margin for use
in Ultra-Low Power Application, International application number: PG/US
13/78262; (Inventors: P. Mazumder, Z. Nan and J. Kim).
12. US
Provisional Patent on Baseband Processing Techniques for Low Power Wake-up Receiver;
(Inventors: N. Zheng and P. Mazumder).
Registered
Inventions:
13. On-Chip Double-Bit Error-Correcting Code
for 3-D Dynamic Random-Access Memory, July 28, 1989 (Inventor: P. Mazumder).
14. Yield Improvement of VLSI Chips by Using
Electronic Neural Networks for Built-in Self-Repair, Feb. 15, 1990 (Inventor:
P. Mazumder).
15. A Zero-Delay Overhead Circuit Technique
for Built-in Self-Repair of Random-Access Memories, Oct 17, 1996 (Inventors: K.
Chakraborty and P. Mazumder).
16. Dual-Rail Static Pulse Clocked Flip-flop,
July 12, 2001 (Inventors: L. Ding and P.
Mazumder).
17. Circuit Simulator for Quantum and Resonant
Tunneling Devices, Sept. 21, 2001; (Inventors:
M. Bhattacharya and P. Mazumder).
18. Multivariate Normal Distribution Based on
Statistical Timing Analysis Algorithm for Digital VLSI Circuits, May 5, 2005
(Inventors: B. Wang and P. Mazumder).
19. Self-Healing Memory Design Using Low
Overhead Adaptive Circuit, March 8, 2010; (Inventors: P. Mazumder and E.
Idong).
20. Multi-Bit Memory Read Method for
Nonvolatile Memory, Dec 19, 2011; (Inventors: Y. Yilmaz and P. Mazumder)
21. 16 T Static Random Access Memory Cell
Design for Improved Performance in Asynchronous Digital Systems, Oct. 29, 2012
(Inventors: J. Kim and P. Mazumder).
22. EM Based Terahertz Logic Design, June 4,
2015 (Inventors: Y. Yilmaz and P. Mazumder)
XI. Software
Package Developed
After finishing
my MSc degree in Computer Science and while working towards my PhD degree in
Electrical and Computer Engineering, I worked during the summers of 1985 and
1986 as a Member of Technical Staff at AT&T Bell Laboratories. I was one of
the two engineers who started the Bell Laboratory Cones/Spruce project -
a new behavioral synthesis and layout automation tool for rapid prototyping of
digital circuits. The main contribution of this effort was to demonstrate how a
restricted version of C language could be used to model digital hardware much
before commercial hardware description language (HDL) software tools like
Verilog and System C were designed.
After joining the University of Michigan, I have assisted my doctoral
students in developing the following software packages that were written using
C and C++ languages.
XII. Consulting Activities
1. Served as Expert for the
US National Science Foundation, Arlington, Virginia.
2. Served as a member of Technical Advisory
Board for. Sequence Design Automation
(Santa Clara, CA), Silicon Value Inc. (Jerusalem, Israel), and Tioga Technology
(San Jose, CA).
3. Served as Technical Advisor and Expert Witness in 10 lawsuits involving DRAM, SRAM, Flash and FPGA.
(For details see Section XIII).
4. Served as Consultant in the
areas of SRAM self-healing circuits; radiation hardening and soft-error
problems in SRAM and FPGA’s; JTAG testing of FPGA’s; ultra-low-power CMOS
circuits; nanoelectronic circuits and simulation tools.
Legal Expert Services Rendered
Served as Technical Advisor and Expert Witness in
the following lawsuits between 1999 and now. My expert services involved (i)
Analysis of alleged patents; (ii) Producing prior art; (iii) Writing Expert
Reports for Invalidation of claims and Non-infringement of claims working for
Defendant, and Infringement claims working for Plaintiff; (iv) SPICE circuit
simulation of accused products; (v) VHDL and Verilog source code analysis; (vi)
Computer hardware testing. (vii) Testimony by deposition over 30 hours; and
(viii) Testimony in trial as invalidity and non-infringement expert.
Fields of Expertise for Expert Services
Consulting in Legal Cases performed in 2000-2015
i)
Posted CAS Method and Determination of CAS Latency in Synchronous DRAM
Samsung Electronics Co. v. NVIDIA Corporation (2015)
Law firm for Defendant: Latham &
Watkins
Type
of appointment: Testifying Expert for Defendant
Expert Work rendered for Defendant involved the following:
· Analyzing the alleged patent, US 6,262,938: Synchronous DRAM having posted CAS
latency and method for controlling CAS latency;
· Analyzing six prior art;
· Establishing non-infringement in accused NVIDIA products;
· Writing a 282-page Invalidity Expert Report
· Writing a 84-page Non-infringement Expert Report
· Writing a 20-page Damages Expert Report
· Giving testimony at deposition; Samsung dropped 4
claims based on my testimony
· Preparation for direct and cross-examination in mock trial
Outcome: Samsung lost in trial
ii)
DRAM Redundancy Techniques for Yield Improvement
Limestone
Memory Systems LLC v. Apple, Inc.
(2016)
Law firm for Defendant: Kenyon &
Kenyon, LLP
Type
of appointment: Testifying Expert for Inter
Partes Review (IPR)
Expert Work rendered for Petitioner involved the following:
· Analyzing the alleged patent, US 5,894,441: Semiconductor Memory Device with
Redundancy Circuit;
· Analyzing
Prior art;
·
Preparing
Declaration for IPR nearly 105 pages;
· Outcome: Defendant’s
Petition is under review by PTAB.
iii)
DRAM Flexible Redundancy Techniques for Yield
Improvement
Limestone
Memory Systems LLC v. Apple, Inc.
(2016)
Law firm for Defendant: Kenyon &
Kenyon, LLP
Type
of appointment: Testifying Expert for Inter
Partes Review (IPR)
Expert Work rendered for Petitioner involved the following:
· Analyzing the alleged patent, US 6,23,381: Semiconductor memory device with improved flexible
redundancy scheme;
· Analyzing
Prior art;
·
Preparing
Declaration for IPR nearly 90 pages;
· Outcome: Defendant’s
Petition is under review by PTAB.
iv)
Current and Voltage Sense Amplifiers for SRAM Progressive Semiconductor Solutions, LLC v. Marvell Semiconductor (2013)
Law firm for Defendant: Fish &
Richardson P.C.
Type of Appointment: Non-infringement
Expert for Defendant
Expert Work rendered for Defendant involved the following:
· Analyzing the alleged patents, US 6,473,349: Cascode Sense Amp
and Column Select Circuit and Method of Operation; and US 6,862,208: Memory Device with Sense amplifier and
Self-Timed Latch;
· Analyzing a group of accused products manufactured by
the Defendant for non-infringement of asserted claims;
· Studying Prior Art for Invalidation Contentions
· Preparation of draft for the non-infringement claim
Outcome: Case settled.
v)
FPGA Debugging and Testing through Boundary Scan
Circuits Intellitech
Corp. v. Xilinx and Lattice Semiconductor (2011)
Law
firm for Defendant: Kirkland & Ellis LLP
Type
of Appointment: Expert for Defendant
Expert Work rendered for Defendant involved the following:
· Analyzing the alleged patent, US 6,594,802: Method and Apparatus for Providing
Optimized Access to Circuits for Debug, Programming, and Test;
· Producing prior art;
· Establishing non-infringement in testing protocols
used in a group of Xilinx and Lattice Semiconductor FPGA products;
· Assisting in preparation of Invalidation Contentions;
·
Analyzing over
1000 lines of VHDL codes (open domain) used for Xilinx and Lattice
Semiconductor FPGA testing and reconfiguring
Outcome: Settlement and licensing arrangement.
vi)
DRAM Testing Methods and Circuits
Hyundai v.
Siemens (1999)
Type of appointment: Testifying Expert for
Plaintiff
Expert
Work rendered for Plaintiff involved
the following:
· Analyzing 5 European and US patents including 5,208,
776, a 293 page patent on DRAM;
·
Producing prior
art;
·
Preparing Expert
Report;
·
Testimony in Deposition
for trial;
·
Testimony in
trial.
Outcome in trial: Plaintiff won in trial and Defendant’s patent was
invalidated.
vii)
DRAM Cell and Voltage Pump Circuits
Mosaid
Technologies v. Samsung (2004)
Type of appointment: Consultant for Morgan
Lewis
Consulting
Work rendered involved the
following:
·
Performing SPICE
simulation of DRAM word-line timing circuits and Vpp pump circuits for all
types of defendant’s accused products that included two different types of
SDRAMs (synchronous memory chips), three types of DDR RAMs (fast double data
rate memory chips), one type of SGRAM (graphics RAM chip), and one type of
Rambus RAM (fast memory chip);
·
Demonstration of
SPICE simulation to attorneys.
viii)
Synchronous Link DRAM for Fast Memory Access and
Digital Locked Loop Implementation in SDRAM
Mosaid
Technologies v. Nanya Technology Corp. (2010)
Type of appointment: Consultant and Expert
for Defendant
Expert Work rendered for Defendant involved the following:
· Analyzing three different patents: US 7,299,330: High
Bandwidth Memory Interface; US 6,992,950: Delay Locked Loop Implementation in a
Synchronous DRAM; and US 5,903,511: Flexible DRAM Array;
· Producing prior
art;
· Non-infringement technical report.
Outcome: Case settled.
ix)
Texture Cache
Memory and Memory Controller in Graphics Chips
Advanced
Silicon Technologies v. NVIDIA Corp.
Law firm for Defendant: Latham &
Watkins
Type of appointment: Consultant and Expert
for Defendant
Expert Work rendered for Defendant involved the following:
·
Analyzing and
helping in preparation of Invalidity Contention charts for two different
patents: US
6339428 B1: Method and apparatus for compressed texture caching in a video
graphics system, and US
6546439 B1: High Bandwidth Memory
Interface; Method and system for improved data access
· Producing prior art
x)
Reliability
Testing of Display Driver Chips in CRT Monitor
Hyundai v. Princeton Graphics (2000)
Consulting
work for Defendant involved (i) Analyzing the complete drive circuits
for CRT based displays comprising several digital and analog ICs, high-voltage
devices, and passive components; (ii) Studying failures of the display monitor
under elevated temperatures; (iii) Writing the reliability report of display
drive of the CRT monitor.
Outcome:
Settled.
xi)
Hall-Effect
Magnetic Field Sensing and Amplification by Chopper Amplifier Chip
Consulting
work for Defendant involved (i) Analyzing the alleged patent; (ii)
Simulation of chopper amplifier for magnetic sensor; (iii) Producing prior art.
Outcome:
Settled.
XIII.
Teaching Accomplishments
i)
Received a letter of commendation from Dean of Engineering for
excellence in undergraduate teaching
ii)
Received a certificate of recognition from Vice Provost of Academic
Affairs and Vice Provost of International Affairs for global outreach
activities
Undergrad Courses Taught:
Regular Graduate Courses Taught:
New Graduates Courses Developed:
Sample
Lecture Slides | Course
Outline
Sample
Lecture Slides | Course
Outline
On-line Courses for Practicing Engineers:
Integration of Research with Teaching:
VLSI
Courseware Developed and Distributed:
Advanced
Books Written for Practicing Engineers:
STEM
Education and K-12 Math Software Developed:
Teaching Evaluations:
XIV. Student Theses Supervised
A. Ph.D. Theses Completed
1.
J. Yih, ”Built-In
Self-Repair of Embedded Memory and Logic Arrays,” 1990. Currently at IBM T.
J. Watson Research Center, Yorktown, New York
2.
K. Shahookar, ”Genetic Algorithms for CAD Layout Problems,” 1994. Currently at his
start-up company in Pakistan
3.
H. Esbensen, ”Application of Genetic Algorithms for Cell Placement and Routing
Problems,” 1994. Currently at Avant! Fremont, California
4.
V. Ramachandran, ”Parallel Architectures for Multilayer Wire Routing Problems,” 1994.
Currently at Cadence Design Systems, San Jose, California
5.
S. Mohan, ”Design of Ultra-fast Digital Circuits using Quantum Electronic Devices,”
Dec. 1994. Currently at Xilinx Corporation, Campbell, California
6.
K. Chakraborty, ”Built-In Self-Repairable RAM Compiler Design,” Mar. 1997. Currently
at Agere Design, Murray Hills, New Jersey
7.
M. Bhattacharya, ”Simulation and Emulation of Digital Integrated Circuits Containing
Resonant Tunneling Diodes,” Oct 1999. Currently at Avant! Fremont,
California
8.
S. Kulkarni, ”Quantum MOS Circuits and Systems,” Oct 1999. Working in IDT,
Atlanta, Georgia
9.
A. Gonzalez, ”Multiple-Valued Logic and High-Speed Digital Circuits Using Resonant Tunneling
Diodes,” June 2001. Currently at IDT, Atlanta, Georgia
10.
Li Ding, “Dynamic
Noise Analysis in Deep Sub-micron CMOS VLSI Systems,” Feb. 2004. Currently
at Synopsis, Sunnyvale, California
11.
Q. W. Xu, “Accurate Interconnect Modeling for Efficient Transient Simulation in
VLSI Chip Design,” May 2006, currently at Cadence Design Systems.
12.
B. Wang, “Accelerated
Chip-level Thermal Analysis Using Multilayer Green's Function," May
2008, currently at VmWare, California
13.
W. H. Lee, “Applications of Nanoelectronic Technology to Image Processors,
Velocity-Tuned Filters and Crossbar Memories”, Dec 2008, currently working
at Intel Corporation
14.
K. Song, “Applications
of Surface Plasmon Polariton Plasmonic Devices,” Aug. 2010, currently
working at Korea Institute of Machinery and Materials, Daejeon, Korea
15.
I. Ebong, “Training Memristors for Reliable Computation,”
Dec. 2012, currently working as a Technical Advisor for Leydig, Voit & Mayer, Ltd., Chicago
16.
X. Zhao, “Terahertz
Analog to Digital Converter Design,” (to be defended), currently working at
Apple Corporation
B. M.S. Theses/Projects Completed:
17. B.
Brighton, Pseudo-Random Testing for
Embedded Memories
18. K.
Quasim, Analog Circuit Testing
19. J.
Kapson, Parallel CAD Architecture
20.
D. Berryman, Parallel Processing for VLSI Routing
21.
M. Smith, Self-Repairable
Memory Array Using Digital Neural Circuit
22. E.
Chan, RTD-based Multi-valued Circuit
Design
23.
A. Arunachalam, Fine-Grained Parallel Routing
24.
A. Gonzalez, Multi-valued Adder Design Using CMOS and RTD
25.
A. Gupta, Self-Repairable
ROM Generator
26.
J. Xiong, Quantum
MOS Circuit Design
27.
G. Mittal, Simultaneous Switching Noise Analysis in Embedded Memories
28.
V. Warraich, Web-based Applets Design for Digital Logic
29.
M. Kumshikar, Amorphous TFT-based Driver Logic Design for AMLCD Panel
30.
G. Shankar, Amorphous TFT-based Operational Amplifier Design for AMLCD Panel
31.
V. Ramachandran, Array Machine for VLSI Routing
32. S. Mohan, Parametric Testing for SRAM’s Using GaAs
High Electron Mobility Transistors
33. S. Kulkarni, CMOS and RTD-based Correlators Design
34. K. Shahookar, Genetic Algorithm for VLSI Placement
35. H. Chan, Macro-cell Placement Using Genetic Algorithm
36. L. Ding, Noises in Deep Sub-micron VLSI Chips
37.
Q. W. Xu, VLSI Interconnect
Modeling Using Differential Quadrature Method
38. B. Wang, 3-Dimensional Full Chip Simulation by
Transmission Line Matrix Method
39. H. Zhang, Ultra-fast RTD-based Circuit Design
40. S.R. Li, RTD-based Cellular Nonlinear Networks
41. D. Shi, Quantum Dot Based Image Processing
42. M. Rajagopal, Modeling of Resonant Tunneling Diodes
43. W. Lee, Image Processing Applications of Quantum Dots
44. E. Ibong, Subthreshold Low-power Operational Amplifier
Design
45. K. Song, Plasmonics Applications in VLSI
46. C. Ting, Modeling of Ionic Current through Memristors
47. Y. Yilmar, Straintronics Pipelined Adder Design
48. J. Qian, Green Function based Thermal Modeling
49.
H. Liu, Straintronics SRAM Design
50.
N. Zheng, Nanoscale Subthreshold
Mixed Signal Chip Design
51.
D. Hu, STDP based Learning Chip
Design
Number of Doctoral Students Currently Being
Supervised: 8.
C. Visiting
Scientists (International Outreach)
1. Dr. T. Ueymura,
NEC, Japan; 2. Prof. H. Choi, Hanyang University, South Korea; 3. Mr. H.
Esbensen, Aarhus University, Denmark.; 4. Dr. Q. W. Xu, China; 5. Dr. J. P. Sun, Shanghai Jiao Tong University,
China; 6. Prof. S. Duan, South East University, China; 7. Prof. Y. Yongbin,
University of Electronic Science and Technology, China; 8. Mr. T. Glotzner,
Germany.
D. Undergrad Thesis & Project Supervised
(International Outreach)
1. S.
Sayyaparaju (Indian Institute of Technology, Roorkee), 2. H. Biswas (Indian
Institute of Technology, Kanpur), 3. J. Induri (Indian Institute of Technology,
Roorkee), 4. S. Kallia (Indian Institute of Technology, Kharagpur), 5. S. Panda
(Indian Institute of Technology, Kahargpur), 6. A. Bhat (Birla Institute of
Technology and Science, Pilani), 7. J. Shah (Birla Institute of Technology and
Science, Pilani), and 8. N. Talati (Birla Institute of Technology and Science,
Goa).
XVI.
Technical Presentations (excluding conferences and workshops)
Formal Talks at Universities
Formal Visits to University
Laboratories
XVII. List of Courses Taken During M.Sc. (in
CS) and Ph.D. (in CE) Study
My
BS degrees were in Physics Honors and Electrical Engineering, while my MSc and
PhD degrees were in CS and CE, respectively. I took the following CS and CE
courses while doing my MSc and PhD:
1)
Analysis of Algorithms, 2) Artificial
Intelligence, 3) Computer Networks, 4) Computer Architecture, 5) Software
Engineering, 6) Local Area Networks, 7) Adaptive Systems, 8) VLSI Complexity
Theory, 9) Switching Theory and Digital Logic Design, 10) Parallel Computer
Architectures, 11) Minicomputer System Architectures, 12) VLSI Layout
Automation and Circuit Simulation, 13) VLSI System Design, 14) AI Based CAD for
VLSI, 15) Digital Testing and Fault Tolerance, and 16) Programming Languages.
Ph.D. Thesis Title: Testing and Fault-Tolerance Aspects of High-Density Random-Access
Memory, University of
Illinois at Urbana-Champaign, 1988. Synopsis: The
thesis introduced the “line-mode plurality testing technique” for high-density
DRAM and CAM chips. Based on this design-for-testability approach, fast parallel
testing algorithms were developed for testing a broad class of parametric and
pattern-sensitive faults. The resulting test procedures are significantly more
efficient than previous approaches due to test length optimization by applying the
chromatic plane ornamentation theory. In many embedded memory applications
where neither the input address and read/write lines are externally
controllable nor are the output lines directly observable, the proposed algorithms
can be adapted for implementing deterministic built-in self-test (BIST)
circuits by designing the read/write sequences through Hamiltonian tours on the
hypercube graph. Also, the thesis presented an extensive amount of Markov
modeling and probabilistic analysis in order to determine the lengths of
randomly applied test patterns for various classes of functional faults in
scattered and small embedded-memories where the proposed deterministic BIST
technique cannot be incorporated. Finally, the thesis addressed the improvement
of storage reliability by two orders of magnitude by introducing a new on-chip
error correcting (ECC) technique capable of correcting the double-bit errors
due to alpha particles striking between the 3-D vertically integrated trench
DRAM cells. The thesis also analyzed the limitations of popular types of
double-bit ECC techniques like the Projective Geometry Code in VLSI
applications. The research resulted in 6 archival journal papers, 6
conference papers, and several chapters in two books on
semiconductor memories coauthored by me.
NB:
Even though when the thesis was written in 1987 DRAM chip size was merely 1
Mega bit and the proposed “line-mode plurality testing technique” was not
necessary, the proposed method has been widely adopted by memory chip
manufacturers in Giga-bit DRAM chips in order to reduce the memory chip testing
time by a significant margin (nearly a thousand times).