Publications

For algorithmically-extracted metrics, please check out my Google Scholar page.

  • 2023

    FuNToM: Functional Modeling of RF Circuits Using a Neural Network Assisted Two-Port Analysis Method.

    Morteza Fayazi, Morteza Tavakoli Taba, Amirata Tabatabavakili, Ehsan Afshari, Ronald Dreslinski.

    International Conference on Computer-Aided Design (ICCAD) (IEEE ICCAD)

    [Paper] [BibTeX]

    AnGeL: Fully-Automated Analog Circuit Generator Using a Neural Network Assisted Semi-supervised Learning Approach.

    Morteza Fayazi, Morteza Tavakoli Taba, Ehsan Afshari, Ronald Dreslinski.

    IEEE Transactions on Circuits and Systems I: Regular Papers (IEEE TCAS-I)

    [Paper] [BibTeX]

    A Compact CMOS 363 GHz Autodyne FMCW Radar with 57 GHz Bandwidth for Dental Imaging.

    Morteza Tavakoli Taba, SM Hossein Naghavi, Morteza Fayazi, Ali Sadeghi, Mohammed Aseeri, Andreia Cathelin, Ehsan Afshari.

    IEEE Custom Integrated Circuits Conference (CICC)

    [Paper] [BibTeX]

  • 2022

    Tablext: A Combined Neural Network and Heuristic Based Table Extractor.

    Zach Colter, Morteza Fayazi, Zineb Benameur-El Youbi, Serafina Kamp, Shuyan Yu, Ronald Dreslinski.

    Elsevier Array

    [Paper] [BibTeX]

    A 507 GMACs/J 256-Core Domain Adaptive Systolic-Array-Processor for Wireless Communication and Linear-Algebra Kernels in 12nm FINFET.

    Kuan-Yu Chen, Chi-Sheng Yang, Yu-Hsiu Sun, Chien-Wei Tseng, Morteza Fayazi, Xin He, Siying Feng, Yufan Yue, Trevor Mudge, Ronald Dreslinski, Hun-Seok Kim, David Blaauw.

    IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

    [Paper] [BibTeX]

    FASCINET: A Fully Automated Single-Board Computer Generator Using Neural Networks.

    Morteza Fayazi, Zachary Colter, Zineb Benameur-El Youbi, Javad Bagherzadeh, Tutu Ajayi, Ronald Dreslinski.

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD)

    [Paper] [BibTeX]

    Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory.

    Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor Mudge, Chaitali Chakrabarti, David Blaauw, Ronald Dreslinski, Hun-Seok Kim.

    IEEE Journal of Solid-State Circuits (IEEE JSSC)

    [Paper] [BibTeX]

  • 2021

    Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm.

    Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor Mudge, Chaitali Chakrabarti, David Blaauw, Ronald Dreslinski, Hun-Seok Kim.

    Symposium on VLSI Circuits

    [Paper] [BibTeX]

    Applications of Artificial Intelligence on the Modeling and Optimization for Analog and Mixed-Signal Circuits: A Review.

    Morteza Fayazi, Zachary Colter, Ehsan Afshari, Ronald Dreslinski.

    IEEE Transactions on Circuits and Systems I: Regular Papers (IEEE TCAS-I)

    [Paper] [BibTeX]

    Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation.

    Tutu Ajayi, Sumanth Kamineni, Morteza Fayazi, Yaswanth K Cherivirala, Kyumin Kwon, Shourya Gupta, Wenbo Duan, Jeongsup Lee, Chien-Hen Chen, Mehdi Saligane, Dennis Sylvester, David Blaauw, Ronald Dreslinski Jr, Benton Calhoun, David D Wentzloff.

    VLSI-SoC: Design Trends: 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, Revised and Extended Selected Papers 28

    [Paper] [BibTeX]

  • 2020

    An Open-source Framework for Autonomous SoC Design with Analog Block Generation.

    Tutu Ajayi, Sumanth Kamineni, Yaswanth K Cherivirala, Morteza Fayazi, Kyumin Kwon, Mehdi Saligane, Shourya Gupta, Chien-Hen Chen, Dennis Sylvester, David Blaauw, Ronald Dreslinski, Benton Calhoun, David D Wentzloff.

    IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC)

    [Paper] [BibTeX]

    Fully Autonomous Mixed Signal SoC Design & Layout Generation Platform.

    Tutu Ajayi, Yaswanth Cherivirala, Kyumin Kwon, Sumanth Kamineni, Mehdi Saligane, Morteza Fayazi, Shourya Gupta, Chien-Hen Chen, Dennis Sylvester, David Blaauw, Ronald Dreslinski, Benton Calhoun, David Wentzloff.

    IEEE Hot Chips Symposium Poster (IEEE HCS)

    [Slides] [BibTeX]

  • 2019

    Fully-Autonomous SoC Synthesis using Customizable Cell-Based Synthesizable Analog Circuits.

    Ronald Dreslinski, David Wentzloff, Morteza Fayazi, Kyumin Kwon, David Blaauw, Dennis Sylvester, Benton Calhoun, Matteo Coltella, David Urquhart.

    GOMACTech

    [Paper] [BibTeX]

  • 2015

    A Simplified Approach to Two-Port Analysis in Feedback.

    Morteza Fayazi, Ali Fotowat, Zahra Kavehvash.

    To be submitted to IEEE Transaction on Education

    [Paper] [BibTeX]