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Graduate Student University of Michigan Ann Arbor Electrical Engineering and Computer Sciences 2260 Hayward St, Room 4861 Ann Arbor, MI 48105 Email: See the header of this page Curriculum Vitae (CV) (Last updated: October, 2010) Research Statement (Last updated: October, 2010) My online profiles: Linked-in, Facebook |
I completed my Ph.D. in the Electrical Engineering and Computer Science Department at the University of Michigan, Ann Arbor in April 2011. I was a part of the CCCP group lead by Prof. Scott Mahlke. Before joining Michigan, I got my Bachelor's degree in Computer Science and Engineering from the Indian Institute of Technology, Guwahati (2005).
I am presently working for Intel Labs (MRML) in Santa Clara, CA.
Computer Architecture and Compiler solutions for:
1. Fault Tolerance - reconfigurable architectures, soft error detection/recovery, cache reliability
2. Performance - single-thread performance using dynamic multicores
3. Energy-efficiency - accelerator design for energy reduction
4. Concurrency Bugs - data races, atomicity violation
My research statement provides a brief summary of my past and ongoing projects.
Ph.D. Computer Science and Engineering, Sep 2005 - Apr 2011
University of Michigan, Ann Arbor
Thesis title: Adaptive Architectures for Robust and Configurable Performance
Advisor: Scott Mahlke
M.S.E Computer Science and Engineering, Sep 2005 - Apr 2007
University of Michigan, Ann Arbor
GPA: 8.0 / 9.0
B.Tech. Computer Science and Engineering, July 2001 - May 2005
Indian Institute of Technology Guwahati
GPA: 9.5 / 10 (Institute Rank:1)
University of Michigan, 2006 - present
- Graduate Student Research Assistant, Department of EECS
- Design and evaluation of multicore architectures for reliability, performance and energy efficiency.
- A short description of my PhD research is available here.
Intel Corporation, Hudson, MA, Jun 2008 - Aug 2008
- Research Intern, Fault Aware Computing Technology Group
- Performed redundancy analysis in modern Intel architectures.
- Worked on techniques for salvaging processor resources.
NEC Laboratories America, Princeton, Jun 2007 - Aug 2007
- Research Intern, Systems and Architecture Group
- Proposed and implemented a novel hardware-assisted data race detection
technique.
University of Michigan, Sep 2006 - Dec 2006
- Graduate Student Instructor, Department of EECS
- Taught the undergraduate C++ data structures and algorithms course -- EECS 280.
Technical University of Munich, Germany May 2004 - Jul 2004
- Research Scholar, Insitute of Electronic Design Automation
- Designed a performance trade-off analysis and optimization tool for analog integrated circuits.
- Best Paper Award, International Conference on Computer Design, 2009
- Graduate Fellowship from the EECS Department, University of Michigan,
2005-6
- President of India Gold Medal, Indian Institute of Technology
Guwahati, 2005
- Institute Merit Scholarship, Indian Institute of Technology Guwahati,
2004
- Student Researcher Scholarship, Technical University of Munich, Germany,
2004
Bundled Execution of Recurring Traces for Energy-Efficient General Purpose Processing
Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott Mahlke and David August
International Symposium on Microarchitecture, 2011 (MICRO'11)
Low-cost, Fine-grained Transient Fault Recovery for Low-end Commodity Systems
Shuguang Feng, Shantanu Gupta, Amin Ansari, Scott Mahlke and David August
International Symposium on Microarchitecture, 2011 (MICRO'11)
Erasing Core Boundaries for Robust and Configurable Performance
Shantanu Gupta, Shuguang Feng, Amin Ansari and Scott Mahlke
To appear in the International Symposium on Microarchitecture, December 2010 (MICRO'10)
Necromancer: Enhancing System Throughput by Animating Dead Cores
Amin Ansari, Shuguang Feng, Shantanu Gupta and Scott Mahlke
International Symposium on Computer Architecture, June 2010 (ISCA'10)
Shoestring: Probabilistic Soft Error Reliability on the Cheap
Shuguang Feng, Shantanu Gupta, Amin Ansari, and Scott Mahlke
International Conference on Architectural Support for Programming Languages and Operating Systems, March 2010 (ASPLOS'10)
ZerehCache: Armoring Cache Architectures in High Defect Density Technologies
Amin Ansari, Shantanu Gupta, Shuguang Feng and Scott Mahlke
International Symposium on Microarchitecture, December 2009 (MICRO'09)
Adaptive Online Testing for Efficient Hard Fault Detection (ICCD'09)
Shantanu Gupta, Amin Ansari, Shuguang Feng and Scott Mahlke
International Conference on Computer Design, October 2009 (ICCD'09)
Best Paper Award
Architectural Core Salvaging in a Multi-Core Processor for Hard-Error Tolerance
Michael D. Powell, Arijit Biswas, Shantanu Gupta and Shubhendu S. Mukherjee
International Symposium on Computer Architecture, June 2009 (ISCA'09)
The StageNet Fabric for Constructing Resilient Multicore Systems
Shantanu Gupta, Shuguang Feng, Amin Ansari, Jason Blome and Scott Mahlke
International Symposium on Microarchitecture, November 2008 (MICRO'08)
Self-calibrating Online Wearout Detection
Jason Blome, Shuguang Feng, Shantanu Gupta, Scott Mahlke
International Symposium on Microarchitecture, December 2007 (MICRO'07)
Full list of publications is available here.