Summary of my research interests and past projects (PDF file)

Adaptive Architectures (2006-present): For my doctoral research, I am working on the design of adaptive architectures for robust and configurable performance. For robustness, I proposed a reconfigurable multicore architecture, called StageNet, that enables fine-grained isolation of broken components witin a chip multiprocessor. Specifically, my architecture allows cores within a group to lend/borrow their pipeline stages to each other, allowing them to salvage healthy components from otherwise broken cores. Building upon the StageNet fabric, I am currently working on designing a unified performance-reliability solution. Using a substrate very similar to StageNet, this new architecture provides capability to dynamically fuse cores together, achieving wider issue width.

I have also worked on several other projects as part of my doctoral research, summer internships and collaboration within U of Michigan:

  1. Utilizing dead cores in future multicore chips (with Amin Ansari, 2009-10, Michigan)
  2. Affordable mechanisms for soft error reliability (with Shuguang Feng, 2009-10, Michigan)
  3. Adaptive online testing for efficient hard fault detection (2009, U of Michigan)
  4. Highly defect and process variation tolerant cache architectures (with Amin Ansari, 2009, Michigan)
  5. Salvaging architectural resources in multicore chips (with Michael Powell, 2008, Intel)
  6. Multicore lifetime extension using introspective wearout-aware scheduling (with Shuguang Feng, 2008, Michigan)
  7. Software bug detection using lightweight Transactional Memory (TM) support (with Florin Sultan, Hari Cadambi, 2007, NEC)

Test pattern generation using SAT (2005): Automatic test pattern generation is a well studied research area. And over the years, PODEM and FAN have been accepted as the de-facto algorithms for this problem. But, these algorithms are limited to handling SSL fault model. With the growing reliability concerns, it is necessary to approach this problem in a more generic manner. In this work I suggested mapping of the test pattern generation problem to a single SAT (satisfiability) problem. Solving which would give us a minimal and complete set of test vectors. The method had a flexibility to support DSL (Double Stuck at Line) and higher fault models.

Even though this approach was very interesting, the running time and memory requirement of the SAT solver was prohibitively expensive making this technique impractical.

Scan chain architecture (2004): Scan chains are an essential component in VLSI testing process. Unfortunately, scanning in of test vectors is a very power hungry step. Majority of this power is dissipated as a result of the high switching activity in the scan chain flip-flops. In this work I proposed a novel architecture for the scan chain that involves optimal connection strategy between consecutive scan chain flip-flops, thereby, reducing the overall power dissipation.

Optimization (2004): Starting with my summer internship at Technical University of Munich, Germany, I got interested in the field of optimization and its potential to solve engineering problems. Over the time, I have learned both traditional as well as statistical techniques for optimization and applied them to a variety of problems. Some of the optimization techniques that I have used are Normal-Boundary Intersection, Recursive Knee approach and Genetic algorithms. Problems solved using these techniques: