Shantanu Gupta
Graduate Student
University of Michigan Ann Arbor
Electrical Engineering and Computer Sciences

2260 Hayward St, Room 4861
Ann Arbor, MI 48105

Email: See the header of this page

Curriculum Vitae (CV) (Last updated: October, 2010)
Research Statement (Last updated: October, 2010)

My online profiles: Linked-in, Facebook


I completed my Ph.D. in the Electrical Engineering and Computer Science Department at the University of Michigan, Ann Arbor in April 2011. I was a part of the CCCP group lead by Prof. Scott Mahlke. Before joining Michigan, I got my Bachelor's degree in Computer Science and Engineering from the Indian Institute of Technology, Guwahati (2005).

I am presently working for Intel Labs (MRML) in Santa Clara, CA.

Research Interests

Computer Architecture and Compiler solutions for:

1. Fault Tolerance - reconfigurable architectures, soft error detection/recovery, cache reliability
2. Performance - single-thread performance using dynamic multicores
3. Energy-efficiency - accelerator design for energy reduction
4. Concurrency Bugs - data races, atomicity violation

My research statement provides a brief summary of my past and ongoing projects.


Work Experience

University of Michigan, 2006 - present
- Graduate Student Research Assistant, Department of EECS
- Design and evaluation of multicore architectures for reliability, performance and energy efficiency.
- A short description of my PhD research is available here.

Intel Corporation, Hudson, MA, Jun 2008 - Aug 2008
- Research Intern, Fault Aware Computing Technology Group
- Performed redundancy analysis in modern Intel architectures.
- Worked on techniques for salvaging processor resources.

NEC Laboratories America, Princeton, Jun 2007 - Aug 2007
- Research Intern, Systems and Architecture Group
- Proposed and implemented a novel hardware-assisted data race detection technique.

University of Michigan, Sep 2006 - Dec 2006
- Graduate Student Instructor, Department of EECS
- Taught the undergraduate C++ data structures and algorithms course -- EECS 280.

Technical University of Munich, Germany May 2004 - Jul 2004
- Research Scholar, Insitute of Electronic Design Automation
- Designed a performance trade-off analysis and optimization tool for analog integrated circuits.


- Best Paper Award, International Conference on Computer Design, 2009
- Graduate Fellowship from the EECS Department, University of Michigan, 2005-6
- President of India Gold Medal, Indian Institute of Technology Guwahati, 2005
- Institute Merit Scholarship, Indian Institute of Technology Guwahati, 2004
- Student Researcher Scholarship, Technical University of Munich, Germany, 2004

Selected Publications

Full list of publications is available here.