Interests

I am currently interested in operating system/hardware interaction, specifically in the domain of high-performance networking and large scale bottleneck analysis to guide architectural improvements

Education

University of Michigan, Ann Arbor, MI
Advanced Computer Architecture Laboratory
Ph.D. in Computer Science and Engineering, expected February 2009
M.S. in Computer Science and Engineering, May 2005
Thesis: Full-System Critical Path Analysis and Performance Prediction
Advisors: Associate Professor Steven K. Reinhardt, Professor Trevor N. Mudge
GPA: 7.9/9.0 (A=8.0)

University of Texas, Austin, TX
B.S. in Electrical Engineering, May 2003
GPA: 3.6/4.0

Honors

Department of Energy High-Performance Computer Science Fellowship finalist, Spring 2005
First Year Fellowship, University of Michigan, Fall 2003 — Summer 2004
College Scholar, University of Texas, Spring 2003
University Honors, University of Texas: Fall 1999, Fall 2000, Fall 2001, Spring 2002, Spring 2003
Outstanding Intern Award, Compaq Computer Corporation, Summer 2000

Experience

• Investigating automated generation of dependence graphs to aid in performance debugging of large systems. This entails automatically extracting dependence information from interacting state machines such as those that govern all levels of a networking stack including: device, device driver, networking stack and application. Ultimately, this analysis will provide insight to systems on the scale of web server requests and responses, including low-level hardware interaction.
• Demonstrated the benefits of integrating a network interface controller(NIC) on a CPU die. Experimented with the level of integration, cache placement of data, and the Simple Integrated NIC (SINIC). SINIC provides CPU control of NIC tasks, without increasing CPU overhead, and allows for optimizations such as zero-copy receive.
• Illustrated how 3D-die stacking technology can be leveraged to provide a simple, high performance throughput processor (PicoServer) while consuming only one tenth the power of a standard design.
• Contributed extensively to the M5 full-system simulator including: NIC and disk device models, Linux OS support, I/O and memory interfaces, PCI device support, Alpha and SPARC platform models, SPARC ISA support, and memory system interfaces.
• Validated the M5 simulator against an Alpha DP264 based machine.
• Prepared draft of NSF proposal that was funded, “Full-System Critical Path Analysis.”

• Teaching Assistant for EECS 470, Computer Architecture.
• Course covers architecture and micro-architecture: out-of-order execution, performance measures, instruction sets, interrupts and exceptions, caches, and design in Verilog.
• Responsible for two discussion sections, the writing and grading labs and exam questions, and guiding project groups through their design of an out-of-order processor in synthesizable Verilog.

• Created a model of present and future Opteron on-chip north bridge architectures for performance analysis that is still in use today.
• Validated performance of model against actual system data.
• Evaluated the performance of future north bridge features in uni-processor and multi-processor systems.

• Participated in IBM's premier internship program.
• Contributed to a pattern matching ASIC architecture and software model.
• Co-inventor on six granted US patents and one US patents pending.
• Created a prototype intrusion detection system based on above ASIC and a network processor.

• Constructed a test bed to simulate external workload of a web cache server.
• Analyzed the internal workload of a web cache with hardware and software instrumentation.
• Wrote multiple utilities for SCO UnixWare, SCO Open Server, and Linux.
• Developed an online configuration capture and compare utility: Compaq Survey Utility for Linux.

Publications

Full-system Critical Path Analysis
A. G. Saidi, N. L. Binkert, S. K. Reinhardt, and T. N. Mudge
Eighth International Symposium on Performance Analysis of Systems and Software (ISPASS), pages 63–74, April 2008.

Analysis of Hardware Prefetching Across Virtual Page Boundaries
R. G. Dreslinski, A. G. Saidi, T. N. Mudge, and S. K. Reinhardt
Fourth International Conference on Computing Frontiers. May 2007

Integrated Network Interfaces for High-bandwidth TCP/IP
N. L. Binkert, A. G. Saidi, and S. K. Reinhardt
Twelfth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS XII), pages 315–324, Oct. 2006.

Picoserver: Using 3D Stacking Technology to Enable a Compact Energy Efficient Chip Multiprocesor
T. K. Gil, S. D'Souza, A. G. Saidi, N. L. Binkert, R. G. Dreslinski, S. K. Reinhardt, K. Flautner, and T. N. Mudge
Twelfth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS XII), pages 117–128, Oct. 2006.

The M5 simulator: Modeling Networked Systems
N. L. Binkert, R. G. Dreslinski, L. R. Hsu, K. T. Lim, A. G. Saidi, and S. K. Reinhardt
IEEE Micro Special issue on Architecture Simulation and Modeling. July/August 2006

Performance Validation of Network-intensive Workloads on a Full-System Simulator
A. G. Saidi, N. L. Binkert, L. R. Hsu, and S. K. Reinhardt
Workshop on Interaction between Operating System and Computer Architecture (IOSCA), pages 33–38, Oct. 2005.

Performance Analysis of System Overheads in TCP/IP Workloads
N. L. Binkert, L. R. Hsu, A. G. Saidi, R. G. Dreslinski, A. L. Schultz, and S. K. Reinhardt
Fourteenth Annual International Conference on Parallel Architecture sand Compilation Techniques (PACT), pages 218–228, Sept. 2005.

Sampling and Stability in TCP/IP Workloads
L. R. Hsu, A. G. Saidi, N. L. Binkert, and S. K. Reinhardt
First Annual Workshop on Modeling, Benchmarking, and Simulation (MoBS), pages 68–77, June 2005.

Analyzing NIC Overheads in Network-intensive Workloads
N. L. Binkert, L. R. Hsu, A. G. Saidi, R. G. Dreslinski, A. L. Schultz, and S. K. Reinhardt
Eighth Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW), pages 28–35, Feb. 2005.

Presentations

Full-system Critical Path Analysis
International Symposium on Performance Analysis of Systems and Software (ISPASS), March 2008

Full-system Critical Path Analysis
Poster session held in conjunction with the International Symposium on Architectural Support for Programming Languages and Operating Systems (ASPLOS-13)}, March 2008

Using the M5 Simulator
Tutorial held in conjunction with the International Symposium on Architectural Support for Programming Languages and Operating Systems (ASPLOS-13), March 2008

Picoserver: Using 3D Stacking Technology to Enable a Compact Energy Efficient Chip Multiprocessor
Invited talk at Intel China Research Center, September 2006

Using the M5 Simulator
Tutorial held in conjunction with the International Symposium on Computer Architecture (ISCA-33), June 2006.

Performance Validation of Network-intensive Workloads on a Full-system Simulator
Workshop on Interaction between Operating System and Computer Architecture (IOSCA), October 2005

The M5 Simulator
Invited talk at the Workshop on Interaction between Operating System and Computer Architecture (IOSCA), October 2005

Using the M5 Simulator
Tutorial held in conjunction with the International Symposium on Computer Architecture (ISCA-32), June 2005

Technical Reports

A Simple Integrated Network Interface for High-Bandwidth Servers
Nathan L. Binkert, Ali G. Saidi, and Steven K. Reinhardt
University of Michigan Technical Report CSE-TR-514-06, January 2006.

Performance Validation of Network-Intensive Workloads on a Full-System Simulator
Ali G. Saidi, Nathan L. Binkert, Lisa R. Hsu, and Steven K. Reinhardt
University of Michigan Technical Report CSE-TR-511-05, July 2005.

Analyzing NIC Overheads in Network-Intensive Workloads
Nathan L. Binkert, Lisa R. Hsu, Ali G. Saidi, Ronald G. Dreslinski, Andrew L. Schultz, and Steven K. Reinhardt
University of Michigan Technical Report CSE-TR-505-04, December 2004

Patents

Configurable bi-directional bus for communicating between autonomous units
US Patent number: 7,185,175; Applied for by: Kerry Kravec, Ali Saidi, Jan Slyfield, and Pascal Tannhof; Assignee: IBM

Method and apparatus for finding repeated substrings in pattern recognition
US Patent number: 7,103,750; Applied for by: Matthew Helsley, Kerry Kravec, Ali Saidi, Jan Slyfield, Pascal Tannhof; Assignee: IBM

Method and apparatus for imbedded pattern recognition using dual alternating pointers
US Patent Number: 7,227,994 Applied for by: Kerry Kravec, Ali Saidi, Jan Slyfield, Pascal Tannhof; Assignee: IBM

Parallel pattern detection engine
US Patent Number: 7,243,1652; Applied for by: Kerry Kravec, Ali Saidi, Jan Slyfield, and Pascal Tannhof; Assignee: IBM

Method and apparatus for performing fast closest match in pattern recognition
US Patent Number: 7,366,352; Applied for by: Kerry Kravec, Ali Saidi, Jan Slyfield, and Pascal Tannhof; Assignee: IBM

Software Accomplishments

M5 Simulator (C++/Python) – A full-system architectural simulator capable of booting multiple ISAs/OS combinations. Major contributions include: NIC and disk device models, Linux and Solaris OS support, I/O and memory interfaces, PCI device support, Alpha and SPARC platform models, SPARC ISA support, and memory system.

M5-AMD (C++/Python) – Adaptation of M5 simulator infrastructure to create statistical simulator used to quickly evaluate Opteron on-chip north-bridge architectures. Developed and validated all non-M5 infrastructure components.

Critical Path Analysis (Python) – Implementation for thesis to process annotations, create a dependence graph, locate the critical path, and provide various other analysis modes based on the collected data.

Verilog Processor Model (Verilog) – Created an out-of-order processor model in synthesizable Verilog that is capable of executing a subset of the Alpha ISA.

Compaq/HP Survey Utiity for Linux (C) – Online configuration capture and compare utility. Developed majority of utility.

Service & Leadership

Officer, Computer Science Engineering Gradutates, Summer 2006 – Spring 2008.
Principal maintainer, ACAL Lab Simulation Pool, Summer 2004 – Present.
Reading Group Coordinator, ACAL — University of Michigan, Spring 2004 – Spring 2005.
President, IEEE — The University of Texas at Austin, Fall 2002 – Spring 2003.
Officer, IEEE — The University of Texas at Austin, Fall 1999 – Spring 2003.
Member: IEEE, IEEE Computer Society, ACM, SIGARCH.