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Sensor Bus Labs DeviceNet and ControlNet Conformance Testing at The University of Michigan |
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General: DeviceNet Lab: ControlNet Lab: EtherNet/IP Lab: Other Pages:
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ct the DeviceNet connector for gold
pins. Gold pins are REQUIRED for Mini, Micro, and Open-Pluggable (Phoenix-style)
connectors!
Observe the CAN waveform (usually just the Duplicate MAC ID messages from the DUT) on an oscilloscope, and verify that the voltage levels are within the allowed ranges in the Test Specification. The signals must be clean, i.e. no ringing, large spikes, or sinusoidal oscillations. A hardcopy of the waveform is printed and saved. Note the current draw and DUT operation at 24V and 11V. The current being drawn from the power supply is noted and recorded - there is no pass/fail criteria. However, the DUT must operate within the range of the two voltages (i.e. the minimum operating voltage of the DUT must be less than 11V). The lab will observe the Dup MAC ID messages at 24V, then decrease the supply voltage to 11V, and the DUT must continue to operate and transmit the messages throughout the ramp down to 11V. Then, power is cycled to verify that the DUT can power-up with an initial voltage of 11V. The lab has a 64-node DeviceNet network operating at 500kbaud, with a maximum length (100 meters) of trunk cable. A picture of the network and a list of the devices is on the DeviceNet Lab Description page. For a slave DUT, the lab removes one device from the network, connects the DUT to the network at a position 100 meters from the scanner and power supply, and adds the DUT to the master's scan list. The network must remain stable, and the remainder of the tests are performed with the network in this configuration. For a master DUT, the lab's master is removed, the DUT is connected 100 meters away from the power supply, and the DUT is required to scan the network. In addition, the master must send and interpret meaningful data by implementing a logic program. Several nodes on the lab's network have outputs wired to inputs (one-for-one, point-to-point), and in simple terms, a PLC or logic program must send a 16-bit integer value to the output node, verify that the same value is being read at the input node, and then increment the value. This results in a binary counter. The following table displays which output bits are wired to which input bits on the lab's network:
The network must remain stable, and the remainder of the tests are performed with the DUT scanning the network and running the logic program. An EDS file must be provided with the DUT, and the file is checked for correctness using EDS File Validation Software. Contact the lab for further information on how to order the software. The lab generates a report of the testing and it is sent to the vendor. All test results remain confidential between the lab and the vendor. Page last updated on Wednesday, 02-Oct-2002 14:26:35 EDT
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