Estimated traffic on/off the chip for power analysis.
Proposed and studied architecture changes that boost both multi-core performance and power efficiency.
Drafted testplan for cache and fabric verification.
Developed workflow for multi-core. multi-chiplet fabric traffic testing and simulation.
Configured Arteris IP for non-conherent traffic.

Participated in the architectural design of a modern server-level RISC-V multicore CPU.
Developed in-house reconfigurable fabric performance model for heterogeneous multicore systems.
Designed configuration semantics to represent a wide range of farbric design options.

Coordinate and support officers to carry out their responsibilities.