Experience

  1. Platform Architect Intern

    Estimated traffic on/off the chip for power analysis.
    Proposed and studied architecture changes that boost both multi-core performance and power efficiency.
    Drafted testplan for cache and fabric verification.
    Developed workflow for multi-core. multi-chiplet fabric traffic testing and simulation.
    Configured Arteris IP for non-conherent traffic.
  2. Platform Architect Intern

    Participated in the architectural design of a modern server-level RISC-V multicore CPU.
    Developed in-house reconfigurable fabric performance model for heterogeneous multicore systems.
    Designed configuration semantics to represent a wide range of farbric design options.
  3. President and Social Chair

    Coordinate and support officers to carry out their responsibilities.

Education

  1. PhD in Computer Science and Engineering

    University of Michigan, Ann Arbor, MI
    Thesis on Streamlining Hihg-Performance Heterogeneous Hardware Design. Supervised by .
  2. Graduate Certificate in Innovation & Entrepreneurship

    University of Michigan, Ann Arbor, MI
  3. BSc in Computer Science with High Distinction

    University of Michigan, Ann Arbor, MI
    GPA: 3.9/4.0