Research ProfileYouTube video
- "High-Radix On-chip Networks with Low-Radix Routers"
- Animesh Jain, Ritesh Parikh and Valeria Bertacco
International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2014
- "DiAMOND: Distributed Alteration of Messages for On-Chip Network Debug"
- Rawan Abdel-Khalek and Valeria Bertacco
International Symposium on Networks-on-Chip (NoCs), Ferrara, Italy, September 2014
Best Paper Award Finalist
(2 finalists in conference)
- "Brisk and Limited-Impact NoC Routing Reconfiguration"
- Doowon Lee, Ritesh Parikh and Valeria Bertacco
Design Automation and Test in Europe (DATE), Dresden, Germany, March 2014
- "uDIREC: Unified Diagnosis and Reconfiguration for Frugal Bypass of NoC faults"
- Ritesh Parikh and Valeria Bertacco
International Symposium on Microarchitecture (MICRO), Davis, CA, December 2013
- "Hybrid Checking for Microarchitectural Validation of Processor Designs on Acceleration Platforms"
- Debapriya Chatterjee, Biruk Mammo, Doowon Lee, Raviv Gal, Ronny Morad, Amir Nahir, Avi Ziv and Valeria Bertacco
International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2013
Post-Silicon and Runtime Verification for Modern ProcessorsIlya Wagner and Valeria Bertacco
published by Springer, 2011.
Functional Design Error in Digital CircuitsKai-hui Chang, Igor Markov and Valeria Bertacco
published by Springer, 2008.
Scalable Hardware Verification with Symbolic SimulationValeria Bertacco
published by Springer, 2005.
- "Achieving Design Correctness (Finally!) with Runtime Checking" - 12/2013
- "Making System-Level Lemonade Out of Hardware Lemons" - 05/2013
- "Multi-core Processors: Will We Ever Get Them Right?" - 03/2013