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PacketGenie is a traffic generator designed to help Network-on-Chip (NoC) researchers analyze their network interconnect designs when running heterogeneous workloads. Researchers can use PacketGenie to generate traffic testbenches for the heterogeneous systems that they want to test, and then use the generated testbench on a cycle-accurate network simulator, such as BookSim, to test their interconnect designs.
Current release: PacketGenie
CrashTest is a fast, high-fidelity, flexible resiliency analysis system. Starting from a hardware description model of the design under analysis, CrashTest is capable of orchestrating and performing a comprehensive design resiliency analysis by examining how the design reacts to faults while running software applications.
A suite of Verilog designs of complex microprocessors with functional bugs. The majority of the bugs occur in complex corner cases of microprocessor operation and are inspired by publicly available errata from Intel, AMD, and other processor manufacturers. Free testbench distribution.
Download: Bug UnderGround
FunSAT is a human-computing inspired game to solve Boolean satisfiability problems. We have developed both single-player and multi-player versions of the game. If you like puzzle games, you will like playing FunSAT!
Play at: FunSAT 1.1
Inferno automatically infers the functionality of a hardware design using Verilog source code and simulation traces. It breaks up observed behavior into transactions and presents them as compact graphs to the user. Free software distribution.
Current release: Inferno
STACCATO is a software package that efficiently computes Disjoint Support Decompositions from BDDs. Disjoint Support Decompositions (DSDs) have many application purposes such as in the formal verification and logic synthesis domains. DSDs also provide a functional representation that is more descriptive than a standard BDD while requiring similar amounts of memory.
Current release: Staccato