College of Engineering  |  Department of Electrical Engineering and Computer Science  |  ECE Division













Contact Information:
Prof. J. Kanicki
University of Michigan
EECS Department
2307 EECS Bldg.
1301 Beal Ave
Ann Arbor, MI 48109-2122

Tel: (734) 936-0964 (Office)
Tel: (734) 936-0972
(Student office)
Tel: (734) 615-6363
(The Kanicki Lab)
Fax: (734) 615-2843
Email: Kanicki@eecs.umich.edu

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New a-Si:H TFT Structure with Recess Source/Drain Electrodes

Alex Kuo and Jerzy Kanicki

We introduced a novel amorphous silicon TFT structure. This structure consists of recess source/drain electrodes achieved by intentionally over-etching the source/drain (SID) molybdenum contacts. By introducing an intentional over-etch (2.5 kÅ) of the TFT contacts, we were able to reduce the off region current by one order of magnitude by diminishing the introduction of metal contaminants over the back channel during the RIE deck-channel etch process. This over-etch step minimizes the molybdenum contaminants in the back channel of the transistor. Under moderate gate bias (VGS < 20 V), which is common for most flat-panel display applications, the transistor suffers no electrical performance degradation. It is also expected that the IOFF value will be more uniform across a large area for such device. Moreover, the fabrication process of this recess source/drain contact TFT requires no additional photolithography step, and can be performed by simply extending the etching time of the source and drain metal contacts. This over-etch step should be performed after the S/D definition, and before the back channel etch process to conceal the molybdenum metal from the plasma in the RIE. The alternative solution could be to perform the over-etch step after the back channel definition. Additionally, this new TFT structure is expected to have faster a. c. response and lower feed-through voltages. This research is supported by Applied Materials Corporation.

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