• Publications
  • Technical Reports
  • Patents
to appear
2015
  • "DjiNN and Tonic: DNN as a Service and Its Implications For Future Warehouse Scale Computers", J. Hauswald, Y. Kang, M. A. Laurenzano, Q. Chen, C. Li, T. Mudge, R.G. Dreslinski, J. Mars, L. Tang. 42nd International Symposium on Computer Architecture (ISCA). [pdf]
  • "Sirius: An Open End-to-End Voice and Vision Personal Assistant and Its Implications for Future Warehouse Scale Computers", J. Hauswald, M. A. Laurenzano, Y. Zhang, C. Li, A. Rovinski, A. Khurana, R.G. Dreslinski, T. Mudge, V. Petrucci, L. Tang, J. Mars. 20th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). [pdf]
  • "A Study of Mobile Device Utilization", C. Gao, A. Gutierrez, M. Ranaj, R.G. Dreslinski, T. Mudge, C.-J. Wu. 2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). [pdf]
2014
  • "Hi-Rise: A High-Radix Switch for 3D Integration with Single-Cycle Arbitration", S. Jeloka, R. Das, R.G. Dreslinski, T. Mudge, D. Blaauw. The 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). [pdf]
  • "A Memory Rename Table to Reduce Energy and Improve Performance", J. Pusdesris, B. VanderSloot, T. Mudge. 2014 International Symposium on Low Power Electronics Design (ISLPED), August 2014, pp. 279-282. [Poster and text] [pdf]
  • "Evaluating Private vs. Shared Last-Level Caches for Energy Efficiency in Asymmetric Multi-Cores", A. Gutierrez, R.G. Dreslinski, T. Mudge. Fourteenth International Conference on Embedded Computer Systems: Architecture, Modeling and Simulation (SAMOS), July 2014, pp. 191-198. [pdf]
  • "VIX: Virtual Input Crossbar for Efficient Switch Allocation", S. Rao, S. Jeloka, R. Das, D. Blaauw, R. Dreslinski, T. Mudge. Fifty first Design Automation Conference (DAC), June 2014, pp. 1-6. [pdf]
  • "Quality-of-Service for a High-Radix Switch", N. Abeyratne, S. Jeloka, Y. Kang, D. Blaauw, R.G. Dreslinski, R. Das, T. Mudge. Fifty first Design Automation Conference (DAC), June 2014, pp. 1-6. [pdf]
  • "A Hybrid Approach to Offloading Mobile Image Classification", J. Hauswald, T. Manville, Q. Zheng, R.G. Dreslinski, C. Chakrabarti, T. Mudge. 2014 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), May 2014, pp. 8375-8379. [pdf]
  • "An Architecture for Low-Power High-Performance Embedded Computing", R.G. Dreslinski, Q. Zheng, R.P. Higgins, J. Hauswald, D. Blaauw, T. Mudge, C. Chakrabarti, J. Ballast, W. Snapp. Thirty ninth Annual GOMACTech Conference (GOMAC), April 2014, pp. 423-426. [pdf]
  • "Sources of Error in Full System Simulation", A. Gutierrez, J. Pusdesris, R. Dreslinski, T. Mudge, C. Sudanthi, C.D. Emmons, M. Hayenga, N. Paver. 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), March 2014, pp. 13-22. [Best Paper Award] [pdf]
  • "Integrated 3D-Stacked Server Designs for Increasing Physical Density of Key-Value Stores", A. Gutierrez, M. Cieslak, B. Giridhar, R. Dreslinski, L. Ceze, T. Mudge. Nineteenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2014, pp. 485-498. [pdf]
  • "A Study of Thread Level Parallelism on Mobile Devices", C. Gao, A. Gutierrez, R. G. Dreslinski, T. Mudge, K. Flautner, G. Blake. 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), March 2014, pp. 126-127. [Poster and text] [pdf]
2013
  • "Exploring DRAM Organizations for Energy-Efficient and Resilient Exascale Memories", B. Giridhar, M. Cieslak, D. Duggal, R. Dreslinski, H. Chen, R. Patti, B. Hold, C. Chakrabarti T. Mudge, D. Blaauw. Proc. of SC 13, Denver, Co, November 2013, 12pp. [pdf]
  • "Centip3De: A Many-Core Prototype Exploring 3D Integration and Near-Threshold Computing", R. G. Dreslinski, D. Fick, B. Giridhar, G. Kim, S. Seo, M. Fojtik, S. Satpathy, Y. Lee, D. Kim, N. Liu, M. Wieckowski, G. Chen, D. Sylvester, D. Blaauw, T. Mudge. Communications of the ACM (CACM), vol 56, no. 11, November 2013, pp.97-104. [pdf]
  • "Architecting an LTE Base Station with Graphics Processing Units", Q. Zheng, Y. Chen, R. Dreslinski, C. Chakrabarti, A. Anastasopoulos, S. Mahlke, T. Mudge. 2013 IEEE Workshop on Signal Processing Systems (SiPS 2013). October 2013, pp .219-224. [pdf]
  • "Limits of Parallelism and Bossting in Dim Silicon", N. Pinckney, R.G. Dreslinski, K. Sewell, D. Fick, T. Mudge, D. Sylvester, D. Blaauw. IEEE Micro. Sept.Oct 2013, pp. 30-37. [pdf]
  • "WiBench: An Open Source Kernal Suite for Benchmarking Wireless Systems", Q. Zheng, Y. Chen, R. Dreslinski, C. Chakrabarti, A. Anastasopoulos, S. Mahlke, T. Mudge. Proc. of the IEEE Int. Symposium on Workload Characterization (IISWC), September 2013, pp.123-132. [pdf]
  • "An Evaluation Methodology for Exascale Memory Systems", R. Dreslinski, B. Girdihar, M. Cieslak, Y. Kang, D. Blaauw, T. Mudge, J. Vetter, R. Schreiber. Workshop on Modeling & Simulation of Exascale Systems & Applications (MODSIM), Seattle, Wa., September 2013, [pdf]
  • "Parallelization Techniques for Implementing Trellis Algorithms on Graphics Processors", Q. Zheng, Y. Chen, R. Dreslinski, C. Chakrabarti, A. Anastasopoulos, S. Mahlke, T. Mudge. IEEE International Symposium on Circuits and Systems (ISCAS 2013), May 2013, pp. 1220-1223. [pdf]
  • "Centip3De: A 64-Core, 3D Stacked Near-Threshold System", R. Dreslinski, D. Fick, B. Giridhar, G. Kim, S. SEo, M. Fojtik, S. Satpathy, Y. Lee, D. Kim, N. Liu, M. Wieckowski, G. Chen, D. Sylvester, D. Blaauw, T. Mudge. Micro, IEEE, vol. 33, no.2, pp.8,16, March-April 2013. [pdf]
  • "Scaling Toward Kilo-Core Processors with Asymmetric High-Radix Topologies", N. Abeyratne, R. Das, Q. Li, K. Sewell, B. Giridhar, R. Dreslinski, D. Blaauw, T. Mudge. 19th IEEE International Symposium on High Performance Computer Architecture (HPCA 2013), February 2013, pp. 496-507. [pdf]
  • "Centip3De: A Cluster-Based NTC Architecture With 64 ARM Cortex-M3 Cores in 3D Stacked 130 nm CMOS" D. Fick, R. Dreslinski, B. Giridhar, G. Kim, S. Seo, M. Fojtik, S. Satpathy, Y. Lee, D. Kim, N. Liu, M. Wieckowski, G. Chen, T. Mudge, D. Blaauw, D. Sylvester. IEEE Journal of Solid-State Circuits, Vol. 48, No. 1, January 2013, pp. 104-117. [pdf]
2012xy
  • "A Customized Processor for Energy Efficient Scientific Computing", A, Sethia, S. Mahlke, G. Dasika, T. Mudge. IEEE Transactions on Computers, Vol. 61, No.12, December 2012, pp. 1711-1723. [pdf]
  • "Lazy Cache Invalidation for Self-Modifying Codes", A. Gutierrez, J. Pusdesris, R. Dreslinski, T. Mudge. The International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES 2012), October 2012, pp. 151-160. [pdf]
  • “XPoint Cache: Scaling Existing Bus Based Coherence Protocols for 2D and 3D Many-Core Systems", R. Dreslinski, T. Manville, K. Sewell, R. Das, N. Pinckney, S. Satpathy, D. Blaauw, D. Sylvester, T. Mudge. The International Conference on Parallel Architectures and Compilation Techniques (PACT 2012), September 2012, pp. 75-85. [pdf]
  • "Centip3De: A 64-Core, 3D Stacked, Near-Threshold System", G. Chen, T. Mudge, D. Sylvester, D. Blaauw. Hotchips, August 2012, pp.380-403.[pdf]
  • "Swizzle Switch: A Self-Arbitrating High-Radix Crossbar for NoC Systems",R. Dreslinski, K. Sewell, S. Satpathy, T. Manville, N. Pinckney, G. Blake, M. Cieslak, R. Das, T. Wenisch, D. Sylvester, D. Blaauw, T. Mudge. Hotchips, August 2012, pp.380 - 403.[pdf]
  • "Reevaluating Fast Dual-Voltage Power Rail Switching Circuitry", R. Dreslinski, B. Giridhar, N. Pinckney, D. Blaauw, D. Sylvester, T. Mudge. 2012 Workshop on Duplicating, Decontructing and Debunking (WDDD), June 2012, pp. 1-7.[pdf]
  • "PicoServer Revisited: On the Profitability of Eliminating Intermediate Cache Levels", P. Tandon, J. Chang, R. Dreslinski, P. Ranganathan, T. Mudge, T.F. Wenisch.2012 Workshop Duplicating, Decontructing and Debunking (WDDD), June 2012, pp. 1-10.[pdf]
  • "Limits of Voltage-Scaled Parallel Architectures to Combat Dark Silicon", N. Pinckney, R. Dreslinski, K. Sewell, D. Fick, D. Blaauw, D. Sylvester, T. Mudge. 2012 Workshop on Dark Silicon (DaSi), June 2012. [pdf]
  • “Swizzle-Switch Networks for Many-Core Systems”.  K. Sewell, R. Dreslinski, T. Manville, S. Satpathy, N. Pinckney, G. Blake, M. Cieslak, R. Das, T. Wenisch, D. Sylvester, D. Blaauw, T. Mudge. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 2, No. 2, June 2012, pp. 278-294. [pdf]
  • “High Radix Self-Arbitrating Switch Fabric with Multiple Arbitration Schemes and Quality of Service”. S. Satpathy, R. Das, R. Dreslinski, T. Mudge, D. Sylvester, D. Blaauw. Proc. of the ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 2012, pp. 406-411. [pdf]
  • “Process Variation in Near-Threshold Wide SIMD Architectures”. S. Seo, R. Dreslinski, M. Woh, Y. Park, C. Charkrabari, S. Mahlke, D. Blaauw, T. Mudge. Proc. of the ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 2012, pp. 980-987. [pdf]
  • “Assessing the Performance Limits of Parallelized Near-Threshold Computing”. N. Pinckney, K. Sewell, R. Dreslinski, D. Fick, T. Mudge, D. Sylvester, and D. Blaauw. Proc. of the ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 2012, pp. 1143-1148. [pdf]
  • “A Limits Study of Benefits from Nanostore-Based Future Data-Centric System Architectures”. J. Chang, K. Lim, T. Mudge, P. Ranganathan, D. Roberts, M. Shah. ACM Internation Conference on Computing Frontiers (CF' 12), May 2012, pp. 33-42. [pdf]
  • "Centip3De: A 3930 DMIPS/W Configurable Near‐Threshold 3D Stacked System With 64 ARM Cortex‐M3 Cores", D. Fick, R. Dreslinski, B. Giridhar, G. Kim, S. Seo, M. Fojtik, S. Satpathy, Y. Lee, D. Kim, N. Liu, M. Wieckowski, G. Chen, T. Mudge, D. Sylvester, D. Blaauw. IEEE International Solid-State Circuits Conference (ISSCC). San Francisco, CA, February 2012, pp. 190-191. [pdf]
  • "A 4.5Tb/s 3.4Tb/s/W 64×64 switch fabric with self-updating least recently granted priority and quality of service arbitration in 45nm CMOS", S. Satpathy, K. Sewell, T. Manville, Yen-Po Chen, R. Dreslinski, D. Sylvester, T. Mudge, D. Blaauw. IEEE International Solid-State Circuits Conference (ISSCC). San Francisco, CA, February 2012, pp. 478-479. [pdf]
2011
  • "Full-System Analysis and Characterization of Interactive Smartphone Applications",
    A. Gutierrez, R. Dreslinski, A. Saidi, C. Emmons, N. Paver. T. Wenisch, T. Mudge. IEEE International Symposium on Workload Characterization
    (IISWC-2011), Austin, TX, USA, November 6-8, 2011. pp. 81-90. [pdf]
  • "PEPSC: A Power-Efficient Processor for Scientific Computing", G. Dasika, A. Sethia, T. Mudge, S. Mahlke. 20th Int. Conf. on Parallel Architectures and Compilation Techniques (PACT) Galveston Island, Texas, October 2011, pp. 101-110. [pdf]
  • "Flexible product code-based ECC schemes for MLC Nand FLASH memories", C. Yang, Y. Emre, C. Chakrabarti, and T.Mudge, IEEE Workshop on Signal Processing Systems, (SiPS 2011), October 4-7 2011, Beirut, Lebanon. [pdf]
  • "SWIFT: A 2.1Tb/s 32x32 Self-Arbitrating Manycore Interconnect Fabric", S. Satpathy, R. Dreslinski, T. Ou, D. Sylvester, T. Mudge, D. Blaauw. Symposia on VLSI Technology and Circuits. Kyoto, Japan, June 2011, pp. 138-139. [Winner in the 11th Annual International VLSI Symposium Low Power Contest] [pdf]
  • "Design and Implementation of Centip3De, a 7-layer Many-Core System", D. Fick, R. Dreslinski, B. Giridhar, G. Kim, S. Seo, M. Fojtik, S. Satpathy, Y. Lee, D. Kim, N. Liu, M. Wiekowski, G. Chen, T. Mudge, D. Sylvester, and D. Blaauw. Proc. of the ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 2011. [Winner DAC/ISSCC Student Design Contest]
  • "Low Power Interconnects for SIMD Computers", M. Woh, S. Satpathy, R. Dreslinski, D. Kershaw, D. Sylvester, D. Blaauw, T. Mudge. Proceedings Design, Automation and Test in Europe DATE 11. March 2011. Grenoble, France. pp. 600-605. [pdf]
  • "Sponge: Portable Stream Programming on Graphics Engines", A. Hormati, M. Samadi, M. Woh, T. Mudge, S. Mahlke. 16th International Conference on Architectural Support for Programming Languages and Operating Systems ASPLOS XVI. March 2011, Newport Beach, CA. pp. 381-392. [pdf]
  • "Bloom Filter Guided Transaction Scheduling", G. Blake, R. Dreslinski, T. Mudge. Proceedings 37th International Symposium on High Performance Computer Architecture HPCA 17. February 2011. San Antonio, TX. pp. 75-86. [pdf]
2010
  • "An Ultra Low Power SIMD Processor for Wireless Communications", M. Woh, S. Seo, C. Chakrabarti, S. Mahlke, T. Mudge. Proceedings of the Asilomar Conference on Signals, Systems and Computers. November, 2010. Asilomar, CA. [pdf]
  • "Yield-driven Near-threshold SRAM Design", G. Chen, D. Sylvester, D. Blaauw, T. Mudge. IEEE Transactions on VLSI Systems. vol 18, no 11. November, 2010. pp. 1590-1598. [pdf]
  • "Mighty-Morphing Power-SIMD", G. Dasika, M. Woh, S. Seo, N. Clark, T. Mudge, S. Mahlke. Proceedings 2010 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems CASES 10. October, 2010. Scottsdale, AZ. pp. 67-75. [pdf]
  • "MEDICS: Ultra-Portable Processing for Medical Image Reconstruction", G. Dasika, A. Sethia, V. Robby, T. Mudge, S. Mahlke. 19th International Conference on Parallel Architectures and Compilation Techniques PACT 10. September, 2010. Vienna, Austria. pp. 181-192. [pdf]
  • "A Low Power DSP for Wireless Communications", H. Lee, C. Chakrabarti, T. Mudge. IEEE Transactions on VLSI Systems. vol 18, no 9. September, 2010. pp. 1310-1322. [pdf]
  • "Diet SODA: A Power-Efficient Processor for Digital Cameras", S. Seo, M. Woh, R. Dreslinski, C. Chakrabarti, S. Mahlke, T. Mudge. International Symposium on Low Power Electronics and Design ISLPED. August, 2010. pp. 79-84. [pdf]
  • "Challenges And Opportunities For Extremely Energy-efficient Processors", T. Mudge. IEEE MICRO. vol 30, no 4. July, 2010. pp. 20-22.[pdf]
  • "Evolution of Thread-Level Parallelism in Desktop Applications", G. Blake, R. Dreslinski, T. Mudge, K. Flautner. The 37th International Symposium on Computer Architecture. June, 2010. St. Malo, France. pp. 302-313. [pdf]
  • "Data Dwarfs: Motivating a Coverage Set for Future Large Data Center Workloads", M. Shah, P. Ranganathan, J. Chang, N. Tolia, D. Roberts, T. Mudge. Architectural Concerns in Large Datacenters Workshop held in conjunction with The 37th International Symposium on Computer Architecture. June, 2010. St. Malo, France. [Poster and text] [pdf]
  • "A 1.07 Tbit/s 128x128 Swizzle Network for SIMD Processors", S. Satpathy, Z. Foo, B. Giridhar, R. Dreslinski, D. Sylvester, T. Mudge, D. Blaauw. IEEE Symposium on VLSI Circuits. June, 2010. Honolulu, Hawaii. pp. 81-82. [pdf]
  • "Circuit design advances for ultra-low power sensing platforms", M. Wieckowski, R. Dreslinski, T. Mudge, D. Blaauw, D. Sylvester. Proceedings of SPIE. vol 7679, 76790W. April, 2010. pp. 1-7. DOI: 10.1117/12.850720. [pdf]
  • "Hypervisor-based Prototyping of Disaggregated Memory and Benefits of VM Consolidation", K. Lim, J. Chang, J. Santos, Y. Turner, T. Mudge, P. Ranganathan, S. Reinhardt, T. Wenisch. 15th International Conference Architectural Support for Programming Languages and Operating Systems. March, 2010. Pittsburgh, Pennsylvania. [Poster] [pdf]
  • "MacroSS: Macro-SIMDization of Streaming Applications", A. Hormati, Y. Choi, M. Woh, M. Kudlur, R. Rabbah, T. Mudge, S. Mahlke. 15th International Conference on Architectural Support for Programming Languages and Operating Systems. March, 2010. Pittsburgh, Pennsylvania. pp. 285-296. [pdf]
  • "Near-threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits", R. Dreslinski, M. Wieckowski, D. Blaauw, D. Sylvester, T. Mudge. Proceedings of the IEEE. vol 98, no 2. February, 2010. pp. 253-256. [pdf]
  • "AnySP: Anytime Anywhere Anyway Signal Processing", M. Woh, S. Seo, S. Mahlke, T. Mudge, C. Chakrabarti, K. Flautner. IEEE MICRO Top Picks Issue. vol 30, no 1. January, 2010. pp. 81-91. [Top Pick: selected as one of the 12 best papers in computer architecture for 2009] [pdf]
  • "Guest Editor's Introduction: Top Picks From The Computer Architecture Conferences Of 2009", T. Mudge. IEEE MICRO. vol 30, no 1. January, 2010. pp. 8-11. [pdf]
  • "Mobile Supercomputers for the Next-Generation Cell Phone", M. Woh, S. Mahlke, T. Mudge, C. Chakrabarti. Computer. vol 43, no 1. January, 2010. pp. 93-97. [pdf]
  • "PicoServer: Using 3D Stacking Technology To Build Energy Efficient Servers", T. Kgil, D. Roberts, T. Mudge. (Eds.) Y. Xie, J. Cong, S. Sapatnekar. Kluwer Hardcover. 2010. pp. 219-260. ISBN: 978-1-4419-0783-7. [pdf]
2009
  • "Low Power Scientific Computing", G. Dasika, A. Sethia, T. Mudge, S. Mahlke. 2009 Workshop on New Directions in Computer Architecture held in conjunction with The 42nd Annual IEEE/ACM International Symposium on Microarchitecture. December, 2009. New York, New York. pp. 7-8. [pdf]
  • "Proactive Transaction Scheduling for Contention Management", G. Blake, R. Dreslinski, T. Mudge. The 42nd Annual IEEE/ACM International Symposium on Microarchitecture. December, 2009. New York, New York. pp. 156-167. [pdf]
  • "Overcoming Moore's Curse: Techniques for Powering Large Transistor Counts in Sub-Micron Technologies", R. Dreslinski, M. Wieckowski, D. Blaauw, D. Sylvester, T. Mudge. 2009 Workshop on New Directions in Computer Architecture held in conjunction with The 42nd Annual IEEE/ACM International Symposium on Microarchitecture. December, 2009. New York, New York. pp. 20-21. [pdf]
  • "Baseband Processing Architectures for SDR", Y. Lin, M. Woh, S. Seo, C. Chakrabarti, S. Mahlke, T. Mudge. CRC Press. Chapter 21 in Wireless, Networking, Radar, Sensor Array Processing and Nonlinear Signal Processing, The Digital Signal Processing Handbook. November, 2009. pp. 21-1 -- 21-18. [pdf]
  • "A Survey of Multicore Processors", G. Blake, R. Dreslinski, T. Mudge. IEEE Signal Processing Magazine. vol 26, no 6. November, 2009. pp. 26-37. [pdf]
  • "Flextream: Adaptive Compilation of Streaming Applications for Heterogeneous Architectures", A. Hormati, Y. Choi, M. Kudlur, R. Rabbah, T. Mudge, S. Mahlke. Parallel Architectures and Compilation Techniques. September, 2009. pp. 214-223. [pdf]
  • "Analyzing the Next Generation Software Defined Radio for Architectures", M. Woh, Y. Lin, S. Seo, S. Mahlke, T. Mudge. Springer. Journal of Signal Processing Systems. August, 2009. New York. DOI: 10.1007/s11265-009-0402-z. [published online] [pdf]
  • "Customizing Wide-SIMD Architectures for H.264", S. Seo, M. Woh, S. Mahlke, T. Mudge, S. Vijay, C. Chakrabarti. International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation. July, 2009. Greece. pp. 172-179. [pdf]
  • "Reconfigurable Multicore Server Processors for Low Power Operation", R. Dreslinski, D. Fick, D. Blaauw, D. Sylvester, T. Mudge. International Workshop on Systems, Architectures, Modeling, and Simulation. July, 2009. Greece. pp. 247-254. [pdf]
  • "Disaggregated Memory for Expansion and Sharing in Blade Servers", K. Lim, J. Chang, T. T. Mudge, P. Ranganathan, S. Reinhardt, T. Wenisch. The 36th International Symposium on Computer Architecture. June, 2009. Austin, Texas. pp. 267-278. [pdf]
  • "End-To-End Performance Forecasting: Finding Bottlenecks Before They Happen", A. Saidi, N. Binkert, S. Reinhardt, T. Mudge. The 36th International Symposium on Computer Architecture. June, 2009. Austin, Texas. pp. 361-370. [pdf]
  • "AnySP: Anytime Anywhere Anyway Signal Processing", M. Woh, S. Seo, S. Mahlke, T. Mudge, C. Chakrabarti, K. Flautner. The 36th International Symposium on Computer Architecture. June, 2009. Austin, Texas. pp. 128-139. [pdf]
  • "Near Threshold Computing: Overcoming Performance Degradation from Aggressive Voltage Scaling", R. Dreslinski, M. Wieckowski, D. Blaauw, D. Sylvester, T. Mudge. Workshop on Energy-Efficient Design held in conjunction with The 36th International Symposium on Computer Architecture WEED. June, 2009. Austin, Texas. pp. 44-49. [pdf]
  • "SuiteSpecks and SuiteSpots: A Methodology for the Automatic Conversion of Benchmarking Programs into Intrinsically Checkpointed Assembly Code", Ringenberg J., T. Mudge. 2009 IEEE International Symposium on Performance Analysis of Systems and Software. April, 2009. Boston, Massachusetts. pp. 227-237. [pdf]
  • "Integrating NAND Flash Devices Onto Servers", Communications of the ACM, Research Highlights. vol 52, no 4. April, 2009. pp. 98-103. [pdf]
  • "Using Non-Volatile Memory to Save Energy in Servers", D. Roberts, T. Kgil, T. Mudge. Design, Automation and Test in Europe. April, 2009. Nice, France. pp. 743-748. [pdf]
  • "Stream Compilation for Real-time Embedded Multicore Systems", Y. Choi, Y. Lin, N. Chong, S. Mahlke, T. Mudge. The 2009 International Symposium on Code Generation and Optimization. March, 2009. pp. 210-220. [pdf]
  • "EXtreme Virtual Pipelining (XVP): Moving Towards Scalable Multithreaded Processors", K. Sewell, T. Mudge, S. Reinhardt. Wild and Crazy Ideas held in conjunction with 16th International Conference on Architectural Support for Programming Languages and Operating Systems. March, 2009. Washington DC. [pdf]
  • "Server Designs for Warehouse Computing Environments", K. Lim, P. Ranganathan, J. Chang, C. Patel, T. Mudge, S. Reinhardt. IEEE MICRO. vol 29, no 1. January, 2009. pp. 41-49. [pdf]
2008
  • "From SODA to Scotch: The Evolution of a Wireless Baseband Processor", M. Woh, Y. Lin, S. Seo, S. Mahlke, T. Mudge, C. Chakrabarti, R. Bruce, D. Kershaw, A. Reid, M. Wilder, K. Flautner. November, 2008. Lake Como. pp. 152-163. [Best Paper] [pdf]
  • "Reconfigurable Energy Efficient Near Threshold Cache Architectures", R. Dreslinski, G. Chen, T. Mudge, D. Blaauw, D. Sylvester, K. Flautner. The 41st IEEE/ACM International Symposium on Microarchitecture. November, 2008. Lake Como, Italy. pp. 459-470. [pdf]
  • "PicoServer: Using 3D Stacking Technology To Build Energy Efficient Servers", T. Kgil, A. Saidi, N. Binkert, S. Reinhardt, K. Flautner, T. Mudge. ACM Journal on Emerging Technologies in Computing Systems. vol 4, no 4. October, 2008. 33 pp. [pdf]
  • "A parameterized dataflow language extension for embedded streaming systems", Y. Lin, Y. Choi, S. Mahke, T. Mudge, C. Chakrabarti. International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation. July, 2008. Samos, Greece. pp. 10-17. [pdf]
  • "Energy-efficient simultaneous thread fetch from different cache levels in a soft real-time SMT processor", E. Ozer, R. Dreslinski, T. Mudge, S. Biles, K. Flautner. (Eds.) M. Berekovic, N. Dimopoulos, S. Wong. Springer-Verlag Berlin Heidelberg. SAMOS VIII Workshop. July, 2008. Greece. pp. 12-22. [pdf]
  • "Improving NAND Flash based disk caches", T. Kgil, D. Roberts, T. Mudge. The 35th International Symposium on Computer Architecture. June, 2008. Beijing, China. pp. 327-338. [pdf]
  • "Understanding and designing new server architectures for emerging warehouse-computing environments", K. Lim, P. Ranganathan, J. Chang, C. Patel, T. Mudge, S. Reinhardt. The 35th International Symposium on Computer Architecture. June, 2008. Beijing, China. pp. 315-326. [Top Pick: selected as one of the 12 best papers in computer architecture for 2008] [pdf]
  • "Full System Critical Path Analysis", A. Saidi, N. Binkert, T. N. Mudge, S. K. Reinhardt. 2008 IEEE International Symposium on Performance Analysis of Systems and Software. April, 2008. pp. 63-74. [pdf]
  • "On-chip cache device scaling limits and effective fault repair techniques in future nanoscale technology", D. Roberts, N. S. Kim, T. Mudge. Journal on Microprocessors and Microsystems. vol 32. April 2008. pp. 244-253. [pdf]
  • "Analyzing the scalability of SIMD for the next generation software defined radio", M. Woh, Y. Lin, S. Seo, T. Mudge, S. Mahlke. 33rd International Conference on Acoustics, Speech, and Signal Processing. April, 2008. Las Vegas, Nevada. pp. 5388-5391. [pdf]
  • "True Random Number Generator with a Metastability-based Quality Control", D. B. C. Tokunaga, T. Mudge. IEEE Journal on Solid-State Circuits. vol 43, no 1. January, 2008. pp. 78-85. [pdf]
  • "Architectural Techniques For Adaptive Computing", S. Das, D. Roberts, D. Blaauw, D. Bull, T. Mudge. (Eds.) A. Wang,, S. Naffziger. Springer Science+Business Media. Adaptive Techniques for Dynamic Processor Optimization. 2008. pp. 175-204. [pdf]
2007
  • "Yield-Driven Near-Threshold SRAM Design", G. Chen, D. Blaauw, T. Mudge, D. Sylvester, N. Kim. IEEE/ACM International Conference on Computer Aided Design. November, 2007. pp. 660-666. [pdf]
  • "Hierarchical Coarse-grained Stream Compilation for Software Defined Radio", Y. Lin, M. Kudlur, S. Mahlke, T. Mudge. International Conference on Compiler and Architecture Support for Embedded Systems. October, 2007. Salzburg, Austria. pp. 115-124. [pdf]
  • "Design and Analysis of LDPC Decoders for Software Defined Radio", S. Seo, T. Mudge, Y. Zhu, C. Chakrabarti. 2007 IEEE Workshop on Signal Processing Systems. October, 2007. Shanghai, China. pp. 210-215. [pdf]
  • "An Energy Efficient Parallel Architecture Using Near Threshold Operation", R. Dreslinski, B. Zhai, T. Mudge, D. Blaauw, D. Sylvester. 16th International Conference on Parallel Architectures and Compilation Techniques. September, 2007. Romania. pp. 175-188. [pdf]
  • "When Homogeneous becomes Heterogeneous: Wearout Aware Task Scheduling for Streaming Applications", D. Roberts, R. Dreslinski, E. Karl, T. Mudge, D. Sylvester, D. Blaauw. Workshop on Operating System Support for Heterogeneous Multicore Architectures. September, 2007. Romania. pp. 5-13. [pdf]
  • "Energy Efficient Near-threshold Chip Multi-processing", B. Zhai, R. Dreslinski, D. Blaauw, T. Mudge, D. Sylvester. International Symposium on Low Power Electronics and Design - 2007. August, 2007. pp. 32-37. [Best Paper Nomination] [pdf]
  • "On-chip cache device scaling limits and effective fault repair techniques in future nanoscale technology", D. Roberts, N. S. Kim, T. Mudge. 10th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools. August, 2007. Lubeck, Germany. pp. 570-578. [pdf]
  • "The Next Generation Challenge for Software Defined Radio", M. Woh, S. Seo, H. Lee, Y. Lin, S. Mahlke, T. Mudge, C. Chakrabarti, K. Flautner. (Eds.) S. Vassiliadis et al. Springer-Verlag Berlin Heidelberg. SAMOS VII Workshop. July, 2007. Greece. pp. 343-354. [Best Paper] [pdf]
  • "Duplicating and Verifying LogTM with OS Support in the M5 Simulator", G. Blake, T. Mudge. Workshop on Duplicating, Deconstructing, and Debunking held in conjunction with the International 34th Symposium on Computer Architecture. June, 2007. San Diego, California. pp. 23-31. [pdf]
  • "Analysis of hardware prefetching across virtual page boundaries", R. Dreslinski, A. Saidi, T. Mudge, S. Reinhardt. ACM International Conference on Computing Frontiers. May, 2007. Italy. pp. 13-22. [pdf]
  • "True random number generator with a metastable-based quality control", C. Tokunaga, D. Blaauw, T. Mudge. International Solid-State Circuits Conference. February, 2007. pp. 404-405. [pdf]
  • "SODA: A High-Performance DSP Architecture for Software-Defined Radio", Y. Lin, H. Lee, M. Woh, Y. Harel, S. Mahlke, T. Mudge, C. Chakrabarti, K. Flautner. IEEE MICRO Top Picks Issue. January, 2007. pp. 114-123. [pdf]
2006
  • "SPEX: A programming language for software defined radio", Y. Lin, R. Mullenix, M. Woh, S. Mahlke, T. Mudge, A. Reid, K. Flautner. 2006 SDR Technical Conference. November, 2006. Orlando, Florida. Section 2.3, 6 pp. [pdf]
  • "PicoServer: Using 3D stacking technology to enable a compact energy efficient chip multiprocessor", Kgil T., D'Souza, S., A. Saidi, N. Binkert, R. Dreslinski, S. Reinhardt, K. Flautner, T. Mudge. 12th International Conference on Architectural Support for Programming Languages and Operating Systems. November, 2006. pp. 117-128. [pdf]
  • "FlashCache: A NAND Flash memory file cache for low power web servers", T. Kgil, T. Mudge. Conference for Compiler and Architecture Support for Embedded Systems. October, 2006. Seoul, South Korea. pp. 103-112. [pdf]
  • "Reducing idle mode power in software defined radio terminals", H. Lee, C. Chakrabati, T. Mudge. International Symposium on Low Power Electronics and Design - 2006. October, 2006. Tegernsee, Germany. pp. 101-106. [pdf]
  • "Design and implementation of Turbo decoders for software defined radio", Y. Lin, S. Mahlke, T. Mudge, C. Chakrabarti, A. Reid, K. Flautner. IEEE 2006 Workshop on Signal Processing Systems. October, 2006. Banff, Canada. pp. 22-27. [pdf]
  • "Reliability modeling and management in dynamic microprocessor-based systems", E. Karl, D. Sylvester, D. Blaauw, T. Mudge. The ACM/IEEE Design Automation Conference. June, 2006. San Francisco, California. pp. 1057-1060. [pdf]
  • "Advances and insights into parallel SAT solving", S. Plaza, I. Kountanis, Z. Andraus, V. Bertacco, T. Mudge. International Workshop on Logic and Synthesis. June, 2006. pp. 188-194. [pdf]
  • "SODA: A low-power architecture for software radio", Y. Lin, H. Lee, M. Woh, Y. Harel, S. Mahlke, T. Mudge, C. Chakrabarti, K. Flautner. 33rd Annual International Symposium on Computer Architecture. June, 2006. Boston, Massachusetts, USA. pp. 89-101. [Top Pick: selected as one of the 12 best papers in computer architecture for 2006] [pdf]
  • "A self-tuning dynamic voltage scaled processor using delay-error detection and correction", S. Das, D. Roberts, S. Lee, S. Pant, D. Blaauw, T. Austin, T. Mudge, K. Flautner. IEEE International Conference on Integrated Circuit Design and Technology. May, 2006. Padova, Italy. pp. 211-214. [pdf]
  • "Guest editorial: Concurrent hardware and software design for multiprocessor SoC", A. Jerraya, T. Mudge. ACM Transactions on Embedded Computing Systems. vol 5, no 2. May, 2006. pp. 259-262.
  • "A self-tuning DVS processor using delay-error detection and correction", S. Das, D. Roberts, S. Lee, S. Pant, D. Blaauw, T. Austin, K. Flautner, T. Mudge. IEEE Journal on Solid-State Circuits. vol 41, no 4. April, 2006. pp. 792-804. [pdf]
2005
  • "Software defined radio-A high performance embedded challenge", H. Lee, Y. Lin, Y. Harel, M. Woh, S. Mahlke, T. Mudge, K. Flautner. 1st International Conference on High Performance Embedded Architectures and Compilers. November, 2005. Barcelona, Spain. [pdf]
  • "How to fake 1000 registers", D. Oehmke, N. Binkert, T. Mudge, S. Reinhardt. 38th Annual IEEE/ACM Symposium Microarchitecture. November, 2005. pp. 7-18. [Best Paper Nomination] [pdf]
  • "A system solution for high-performance, low-power SDR", Y. Lin, H. Lee, Y. Harel, M. Woh, N. Baron, S. Mahlke, T. Mudge, K. Flautner. Proc. 2005 SDR Technical Conf. November, 2005. Annaheim, California. [pdf]
  • "Total power-optimal pipelining and parallel processing under process variations in nanometer technology", N. S. Kim, T. Kgil, K. Bowman, V. De, T. Mudge. International Conference of Computer Aided Design ICCAD. November, 2005. pp. 535-540. [pdf]
  • "Quantitative analysis and optimization techniques for on-chip cache leakage power", IEEE Transactions on VLSI. vol 13, no 10. October, 2005. pp. 1147-1156. [pdf]
  • "A dual processor solution for the MAC layer of a software defined radio terminal", H. Lee, T. Mudge. Conference on Compiler and Architecture Support for Embedded Systems. September, 2005. California. pp. 257-265. [pdf]
  • "Introduction to the special issue of the IEEE Transactions in Computers on Energy Efficient Computing", T. Mudge. IEEE Transactions in Computers on Energy Efficient Computing. vol 54, no 6. June, 2005. pp. 641-641. [pdf]
  • "An Intrusion tolerant and self-recoverable network service system using security enhanced chip multiprocessors", W. Shi, H. H. Lee, G. Gu, M. Ghosh, L. Falk, T. Mudge. The 2nd International Conference on Autonomic Computing. June, 2005. Seattle, Washington. [pdf]
  • "A self-tuning DVS processor using delay-error detection and correction", S. Das, S. Pant, D. Roberts, S. Lee, D. Blaauw, T. Austin, T. Mudge, K. Flautner. 2005 Symposium on VLSI Circuits. June, 2005. Kyoto, Japan. pp. 258-261. [pdf]
  • "PowerFITS: Reduce Dynamic and Static I-cache power using application specific instruction set synthesis", A. Cheng, G. Tyson, T. Mudge. The IEEE International Symposium on Performance Analysis of Systems and Software. March, 2005. Austin, Texas. pp. 32-41. [pdf]
  • "Power-performance trade-offs in nanometer-scale multi-level caches considering total leakage", R. Bai, N. S. Kim, T. Mudge, D. Sylvester. Design, Automation and Test in Europe. March, 2005. Munich, Germany. pp. 650-651. [pdf]
  • "Error analysis for the support of robust voltage scaling", D. Roberts, T. Austin, D. Blaauw, T. Mudge. 6th International Symposium on Quality Electronic Design. March, 2005. pp. 65-70. [pdf]
  • "Intrinsic checkpointing: A methodology for decreasing simulation time through binary modification", J. Ringenberg, C. Pelosi, D. Oehmke, T. Mudge. IEEE International Symposium on Performance Analysis of Systems and Software. March, 2005. Austin, Texas. pp. 78-88. [pdf]
  • "Total leakage optimization strategies for multi-level caches", R. Bai, N. S. Kim, D. Sylvester, T. Mudge. ACM/IEEE Great Lakes Symposium on VLSI. 2005. pp. 381-384. [pdf]
  • "DVS for on-chip bus designs based on timing error correction", H. Kaul, D. Sylvester, D. Blaauw, T. Mudge, T. Austin. Design, Automation and Test in Europe. 2005. Munich, Germany. pp. 80-85. [pdf]
  • "Opportunities and challenges for better than worst-case design", T. Austin, V. Bertacco, D. Blaauw, T. Mudge. Asia South Pacific Design Automation Conference. vol 1. January, 2005. China. pp. I/2-I/7. [pdf]
2004-2000
  • "Razor: circuit-level correction of timing errors for low-power operation", D. Ernst, S. Das, S. Lee, D. Blaauw, T. Austin, T. Mudge, N. S. Kim, K. Flautner. IEEE MICRO. vol 24, no 6. November, 2004. pp. 10-20. [Best Paper, Top Pick: selected as one of the best papers in computer architecture for 2006 from the top conferences of 2003/4: Micro-36, HPCA 10, ISCA 31, PACT 2004, ASPLOS XI] [pdf]
  • "ChipLock: Support for Secure Microarchitectures", T. Kgil, L. Falk, T. Mudge. Workshop on Architectural Support for Security and Anti-virus held in conjunction with the 11th International Conferference on Architectural Support for Programming Languages and Operating Systems. October, 2004. Boston, Massachusetts. pp. 130-139. [pdf]
  • "A programmable vector coprocessor architecture for wireless applications", Y. Lin, N. Baron, H. Lee, S. Mahlke, T. Mudge. 3rd Workshop on Application Specific Processors held in conjunction with the International Conference on Hardware/Software Codesign and System Synthesis. September, 2004. Stockholm. pp. 103-110. [pdf]
  • "Microarchitectural power modeling techniques for deep sub-micron microprocessors", N. Kim, T. Kgil, V. Bertacco, T. Austin, T. Mudge. The International Symposium on Low Power Electronics and Design. August, 2004. Newport Beach, California. pp. 212-217. [pdf]
  • "Single Vdd and single Vt super-drowsy techniques for low-leakage high-performance instruction caches", N. Kim, K. Flautner, D. Blaauw, T. Mudge. The International Symposium on Low Power Electronics and Design. August, 2004. Newport Beach, California. pp. 54-57. [pdf]
  • "Reducing pipeline energy demands with local DVS and dynamic retiming", S. Lee, T. Austin, D. Blaauw, T. Mudge. The International Symposium on Low Power Electronics and Design. August, 2004. Newport Beach, California. pp. 319-324. [pdf]
  • "FITS: Framework-based instruction-set tuning synthesis for embedded application specific processors", A. Cheng, G. Tyson, T. Mudge. The ACM/IEEE Design Automation Conference. June, 2004. San Diego, California. pp. 920-923. [pdf]
  • "Circuit-aware architectural simulation", S. Lee, S. Das, V. Bertacco, T. Austin, D. Blaauw, T. Mudge. The ACM/IEEE Design Automation Conference. June, 2004. San Diego, California. pp. 305-310. [pdf]
  • "Mobile Supercomputers", T. Austin, D. Blaauw, S. Mahlke, T. Mudge, C. Chakrabati, W. Wolf. Computer. vol 37, no 5. May, 2004. pp. 81-83. [pdf]
  • "FITS: Increasing code density for embedded systems with a cost-effective 16-bit ISA synthesis technique" 2nd IEEE/ACM Workshop on Optimizations for DSP and Embedded Systems held in conjunction with the International Symposium on Code Generation and Optimization", A. Cheng, G. Tyson, T. Mudge. March, 2004. San Jose, California.
  • "Circuit and microarchitectural techniques for reducing cache leakage power", N. Kim, K. Flautner, D. Blaauw, T. Mudge. IEEE Transactions on VLSI. vol 12, no 2. February, 2004. pp. 167-184. [pdf]
  • "Making Typical Silicon Matter with Razor", T. Austin, D. Blaauw, T. Mudge, K. Flautner. Computer. vol 37, no 3. 2004. pp. 57-65. [pdf]
  • "Razor: A low-power pipeline based on circuit-level timing speculation", D. Ernst, N. Kim, S. Das, S. Pant, T. Pham, R. Rao, C. Ziesler, D. Blaauw, T. Austin, T. Mudge, K. Flautner. The 36th Annual IEEE/ACM Symposium on Microarchitecture. December, 2003. pp. 7-18. [Best paper] [pdf]
  • "SimpleDSP: A Fast and Flexible DSP Processor Model", J. Ringenberg, D. Oehmke, T. Austin, T. Mudge. 5th Workshop on Media and Streaming Processors held in conjunction with the 36th Annual IEEE/ACM Symposium on Microarchitecture. December, 2003. [pdf]
  • "Leakage Current: Moore's Law Meets Static Power", N. Kim, T. Austin, D. Blaauw, T. Mudge, K. Flautner, J. Hu, M. Irwin, M. Kandemir, N. Vijaykrishnan. Computer. vol 36, no 12. December, 2003. pp. 68-75. [pdf]
  • "Leakage power optimization techniques for ultra deep sub-micron multi-level caches", N. Kim, D. Blaauw, T. Mudge. International Conference of Computer Aided Design. November, 2003. San Jose, California. pp. 627-632. [pdf]
  • "A 2.3Gb/s fully integrated and synthesizable AES Rijndael core", N. Kim, T. Mudge, R. Brown. IEEE Custom Integrated Circuits Conference. September, 2003. pp. 193-196. [pdf]
  • "Microarchitecture for a low power register file with reduced register ports", N. Kim, T. Mudge. The International Symposium on Low Power Electronics and Design. August, 2003. Seoul, South Korea. pp. 384-389. [pdf]
  • "Reducing register ports using delayed write-back queues and operand pre-fetch", N. Kim, T. Mudge. International Supercomputing Conference. June, 2003. San Francisco, California. pp. 172-182. [pdf]
  • "Special Issue on Compilers, Architecture, and Synthesis for Embedded Systems", G. Gao, T. Mudge. ACM Transactions on Embedded Computer Systems. vol 2, no 2. 2003.
  • "Vertigo: Automatic performance-setting for Linux", K. Flautner, T. Mudge. The 5th Operating Systems Design and Implementation. December, 2002. pp. 105-116. [pdf]
  • "Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads", S. Martin, K. Flautner, D. Blaauw, T. Mudge. International Conference of Computer Aided Design. November, 2002. San Jose, California. pp. 721-725. [ICCAD Ten Year Retrospective Most Infulential Paper Award][pdf]
  • "Drowsy instruction caches: Leakage power reduction using dynamic voltage scaling and cache sub-bank prediction", N. Kim, K. Flautner, D. Blaauw, T. Mudge. 35th Annual IEEE/ACM Symposium on Microarchitecture. November, 2002. pp. 219-230. [pdf]
  • "Automatic performance setting for dynamic voltage scaling", K. Flautner, S. Reinhardt, T. Mudge. ACM Journal on Wireless Networks. vol 8, no 5. September, 2002. pp. 507-520. [pdf]
  • "Low-energy data cache using sign compression and cache line bisection", N. Kim, T. Austin, T. Mudge. 2nd Annual Workshop on Memory Performance Issues held in conjunction with the 29th Annual International Symposium on Computer Architecture. May, 2002. Anchorage, Alaska. [pdf]
  • "Drowsy Caches: Simple techniques for reducing leakage power", K. Flautner, N. Kim, S. Martin, D. Blaauw, T. Mudge. The 29th Annual International Symposium on Computer Architecture. May, 2002. Anchorage, Alaska. pp. 148-157. [pdf]
  • "Leakage current reduction in VLSI systems", D. Blaauw, S. Martin, T. Mudge, K. Flautner. Journal of Circuits, Systems, and Computers. vol 11, no 6. 2002. pp. 621-636.
  • "MiBench: A free, commercially representative embedded benchmark suite", M. Guthaus, J. Ringenberg, D. Ernst, T. Austin, T. Mudge, R. Brown. IEEE 4th Annual Workshop on Workload Characterization, held in conjunction with The 34th Annual IEEE/ACM Symposium on Microarchitecture. December, 2001. Austin, Texas. pp. 3-14. [pdf]
  • "High-performance DRAMs in workstation environments", V. Cuppu, B. Jacob, B. Davis, T. Mudge. IEEE Transactions on Computers. vol 50, no 11. November, 2001. pp. 1133-1153. [pdf]
  • "Automatic performance setting for dynamic voltage scaling", K. Flautner, S. Reinhardt, T. Mudge. 7th Annual International Conference On Mobile Computing and Networking. July, 2001. Rome, Italy. pp. 260-271. [pdf]
  • "Hybrid myths in branch prediction", A. Eden, J. Ringenberg, S. Sparrow, T. Mudge. 5th World Multiconference on Systemics, Cybernetics and Informatics and the 7th Interenational Conference on Information Systems Analysis and Synthesis. vol XIV. July, 2001. Orlando, Florida. pp. XIV 74-81. [pdf]
  • "Integrating superscalar processor components to implement register caching", M. Postiff, D. Greene, S. Raasch, T. Mudge. 15th ACM International Conference On Supercomputing. June, 2001. Sorrento, Italy. pp. 348-357. [pdf]
  • "Uniprocessor virtual memory without TLBs", IEEE Transactions on Computers. vol 50, no 5. May, 2001. pp. 482-499. [pdf]
  • "Power: A first class design constraint", T. Mudge. Computer. vol 34, no 4. April, 2001. pp. 52-57. [pdf]
  • "Challenges for architectural level power modeling", N. Kim, T. Austin, T. Mudge, D. Grunwald. (Eds.) R. Melhem, R. Graybill. Kluwer Academic Publishers. Power Aware Computing. 2001. [pdf]
  • "The store-load address table and speculative register promotion", M. Postiff, D. Greene, T. Mudge. 33rd Annual IEEE/ACM Symposium Microarchitecture. December, 2000. pp. 235-244. [pdf]
  • "Power: A first class design constraint for future architectures", T. Mudge. 7th International Conference on High Performance Computing. December, 2000. Bangalore, India. pp. 215-224.
  • "Collection and analysis of microprocessor design errors", D. Van Campenhout, T. Mudge, J. P. Hayes. IEEE Design and Test. vol 17, no 4. October, 2000. pp. 51-60. [pdf]
  • "The new DRAM interfaces: SDRAM, RDRAM and variants", B. Davis, B. Jacob, T. Mudge. 3rd International Symposium on High Performance Computing. October, 2000. Tokyo, Japan. pp. 26-31. [pdf]
  • "Thread-level parallelism and interactive performance of desktop applications", K. Flautner, S. Reinhardt, T. Mudge. 9th International Conference on Architectural Support for Programming Languages and Operating Systems. August, 2000. pp. 129-138. [pdf]
  • "DDR2 and low latency variants", B. Davis, T. Mudge, B. Jacob. Memory Wall Workshop held in conjunction with the 26th Annual International Symposium on Computer Architecture. June, 2000. [pdf]
  • "Web latency reduction via client-side prefetching", A. Eden, B. Joh, T. Mudge. 2000 IEEE International Symposium on Performance Analysis of Systems and Software. April, 2000. Austin, Texas. pp. 193-200. [pdf]
  • "Thread level parallelism of desktop applications", K. Flautner, R. Uhlig, S. Reinhardt, T. Mudge. Workshop on Multi-threaded Execution, Architecture and Compilation held in conjunction with the 6th International Symposium on High Performance Computer Architecture. January, 2000. Toulouse.
  • "Reducing code size with run-time decompression", C. Lefurgy, E. Piccininni, T. Mudge. The 6th International Symposium on High-Performance Computer Architecture. January, 2000. pp. 218-227. [pdf]
1999-1995
  • "Evaluation of a high performance code compression method", C. Lefurgy, E. Piccininni, T. Mudge. The 32nd Annual Symposium on Microarchitecture. November, 1999. pp. 93-102. [pdf]
  • "Error simulation with conditional error models", D. Van Campenhout, T. Mudge, J. P. Hayes. 4th IEEE International High Level Design Validation and Test Workshop. November, 1999. La Jolla, California. pp. 198-205. [pdf]
  • "Fast software-managed code decompression", C. Lefurgy, T. Mudge. 2nd International Workshop on Compiler and Architecture Support for Embedded Systems. October, 1999. pp. 139-143. [pdf]
  • "Performance limits of trace caches", M. Postiff, G. Tyson, T. Mudge. Journal of Instruction Level Parallelism. October, 1999. [pdf]
  • "High-level test generation for design verification of pipelined microprocessors", D. Van Campenhout, T. Mudge, J. P. Hayes. The 36th ACM/IEEE Design Automation Conference. June, 1999. New Orleans, Louisiana. pp. 185-188. [pdf]
  • "Timing verification of sequential dynamic circuits", D. Van Campenhout, T. Mudge, K. Sakallah. IEEE Transactions on Computer-Aided Design. vol 18, no 5. May, 1999. pp. 645-658. [pdf]
  • "A performance comparison of contemporary DRAM architectures", V. Cuppu, B. Jacob, B. Davis, T. Mudge. The 26th Annual International Symposium on Computer Architecture. May, 1999. pp. 222-233.
  • "MIRVSim: a high level simulator integrated with the MIRV compiler", K. Flautner, G. Tyson, T. Mudge. Computer Architecture News. vol 27, no 1. March, 1999. pp. 43-46. [Condensed from Proc. 3rd Workshop on Interaction Between Compilers and Computer Architecture (INTERACT-3) at the 8th Int. Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII), Oct. 1998] [pdf]
  • "The limits of instructions level parallelism in SPEC95 applications", M. Postiff, D. Greene, G. Tyson, T. Mudge. Computer Architecture News. vol 27, no 1. March, 1999. pp. 31-34. [Condensed from Proc. 3rd Workshop on Interaction Between Compilers and Computer Architecture (INTERACT-3) at the 8th Int. Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII), Oct. 1998] [pdf]
  • "Modeling and detecting control errors in microprocessors", H. Al-Asaad, J. Hayes, T. Mudge. International IEEE Conference on DYnamic CONtrol Systems. 1999. [pdf]
  • "Trace-driven memory simulation: A survey", R. Uhlig, T. Mudge. (Eds.) G. Haring, C. Lindemann, M. Reiser. Springer-Verlag. Performance Evaluation: Origins and Directions. 1999. pp. 97-139. [Abridged from ACM Computing Surveys, vol. 29, no, 2, June 1997, pp. 128-170.]
  • "The YAGS branch predictor", A. Eden, T. Mudge. 31st Annual IEEE/ACM Symposium on Microarchitecture. December, 1998. pp. 69-77. [pdf]
  • "Code compression for DSP", C. Lefurgy, T. Mudge. 2nd International Workshop on Compiler and Architecture Support for Embedded Systems. vol 3, no 4. December, 1998. [pdf]
  • "High-level test generation for design verification of pipelined microprocessors", D. Van Campenhout, T. Mudge, J. P. Hayes. 3rd IEEE International High Level Design Validation and Test Workshop. November, 1998. La Jolla, California. pp. 1-8. [pdf]
  • "The limits of instructions level parallelism in SPEC95 applications", M. Postiff, D. Greene, G. Tyson, T. Mudge. 3rd Workshop on Interaction Between Compilers and Computer Architecture held in conjunction with the 8th International Conference on Architectural Support for Programming Languages and Operating Systems. October, 1998. [pdf]
  • "Introspective computers", K. Flautner, T. Mudge. Wild and Crazy Ideas Session held in conjunction with The 8th International Conference on Architectural Support for Programming Languages and Operating Systems. October, 1998. [pdf]
  • "Alcohol Content vs. Flavor: A Case Study", D. Burger, G. Tyson, T. Austin, J. Smith, T. Mudge. Zymurgy Magazine. October, 1998.
  • "Evaluation of design error models for verification testing of microprocessors", D. Van Campenhout, T. Mudge, J. P. Hayes. IEEE 1st International Workshop on Microprocessor Test and Verification. October, 1998. Washington DC. [pdf]
  • "High-level design verification of microprocessors via error modeling", D. Van Campenhout, H. Al-Asaad, J. P. Hayes, T. Mudge, R. Brown. ACM Transactions on Design Automation of Electronic Systems. vol 3, no 4. October, 1998. pp. 581-599. [pdf]
  • "A look at several memory management units, TLB-refill mechanisms, and page table organizations", B. Jacob, T. Mudge. 8th International Conference on Architectural Support for Programming Languages and Operating Systems. October, 1998. San Jose, California. pp. 295-306. [pdf]
  • "MIRVSim: a high level simulator integrated with the MIRV compiler", K. Flautner, G. Tyson, T. Mudge. 3rd Workshop on Interaction Between Compilers and Computer Architecture held in conjunction with the 8th International Conference on Architectural Support for Programming Languages and Operating Systems. October, 1998. [pdf]
  • "Virtual memory in contemporary microprocessors", B. Jacob, T. Mudge. Micro. vol 18, no 4. July, 1998. pp. 60-75. [pdf]
  • "Design and performance evaluation of global history dynamic branch predictors", C-C. Lee, I-C. Chen, T. Mudge. World Multiconference on Systemics Cybernetics and Informatics, and, The 4th International Conference on Information Systems Analysis and Synthesis. vol 2. July, 1998. Orlando, Florida. pp. 664-671. [pdf]
  • "Virtual memory: Issues of implementation", B. Jacob, T. Mudge. Computer. vol 31, no 6. June, 1998. pp. 33-43. [pdf]
  • "Overview of complementary GaAs technology for high-speed VLSI circuits", R. Brown, B. Bernhardt, M. LaMacchia, J. Abrokwah, P. Parakh, T. Basso, S. Gold, S. Stetson, C. Gauthier, D. Foster, B. Crawforth, T. McQuire, K. Sakallah, R. Lomax, T. Mudge. IEEE Transactions on VLSI. vol 6, no 1. March, 1998. pp. 47-51. [pdf]
  • "Improving code density using compression techniques", C. Lefurgy, P. Bird, I-C. Cheng, T. Mudge. 30th Annual IEEE/ACM Symposium on Microarchitecture. December, 1997. pp. 194-203. [pdf]
  • "The bi-mode branch predictor", C. Lee, I. Chen, T. Mudge. 30th Annual IEEE/ACM Symposium on Microarchitecture. December, 1997. pp. 4-13. [pdf]
  • "A complementary GaAs 32-bit multiply-accumulate unit", M. Kelley, M. Postiff, T. Strong, R. Brown, T. Mudge. 31st Asilomar Conference on Signals, Systems, and Computers. November, 1997. pp. 1507-1511. [pdf]
  • "High-level design verification of microprocessors via error modeling", H. Al-Asaad, D. Van Campenhout, J. Hayes, T. Mudge. IEEE International Workshop on High Level Design Validation and Test. November, 1997. pp. 194-201. [pdf]
  • "Instruction prefetching using branch prediction information", I-C. Chen, C-C. Lee, T. Mudge. International Conference on Computer Design 97. October, 1997. pp. 593-601. [pdf]
  • "Multilevel performance optimization of pipelined caches", O. Olukotun, T. Mudge, R. Brown. IEEE Transactions on Computers. vol 46, no 10. October, 1997. pp. 1093-1102. [pdf]
  • "Design optimization for high-speed per-address two-level branch predictors", I-C. Chen, C-C. Lee, M. Postiff, T. Mudge. International Conference on Computer Design 97. October, 1997. pp. 88-96. [pdf]
  • "Improving data cache performance by pre-executing instructions under a cache miss", J. Dundas, T. Mudge. 1997 ACM International Conference on Supercomputing. July, 1997. pp. 68-75. [pdf]
  • "Trace-driven memory simulation: A survey", R. Uhlig, T. Mudge. ACM Computing Surveys. vol 29, no 2. June, 1997. pp. 128-170. [pdf]
  • "Impact of MCMs on high performance processors", B. Davis, C. Gauthier, P. Parakh, T. Basso, C. Lefurgy, R. Brown, T. Mudge. ASME Advances in Electronic Packaging 97. vol 1. June, 1997. pp. 863-868. [pdf]
  • "Software-managed address translation", B. L. Jacob, T. Mudge. 3rd Symposium on High Performance Computer Architecture. February, 1997. San Antonio, Texas. pp. 156-167. [pdf]
  • "Trap-driven memory simulation with Tapeworm II", R. Uhlig, D. Nagle, T. Mudge, S. Sechrest. ACM Transactions on Modeling and Computer Simulation. vol 7, no 1. January, 1997. pp. 7-41. [pdf]
  • "Strategic directions in computer architecture", T. Mudge. ACM Computing Surveys. vol 28, no 4. December, 1996. pp. 671-678. [Also available online to Surveys subscribers via the URL http://www.acm.org/pubs/contents/journals/surveys/1996-28/#4] [pdf]
  • "Timing verification of sequential domino circuits", D. Van Campenhout, T. Mudge, K. Sakallah. International Conference on CAD. December, 1996. pp. 127-132. [pdf]
  • "Wrong path instruction prefetching", J. Pierce, T. Mudge. 29th Annual IEEE/ACM Symposium on Microarchitecture. December, 1996. pp. 165-175. [pdf]
  • "Complementary GaAs technology for a GHz microprocessor", R. Brown, T. Basso, P. Parakh, S. Gold, C. Gauthier, R. Lomax, T. Mudge. Tech. Digest of the GaAsIC Symposium. November, 1996. pp. 313-316. [pdf]
  • "Support for nomadism in a global environment", B. L. Jacob, T. Mudge. Workshop on Object Replication and Mobile Computing. October, 1996. San Jose, California. [pdf]
  • "Analysis of Branch Prediction via Data Compression", I-C. Cheng, J. Coffey, T. Mudge. 7th International Conference on Architectural Support for Programming Languages and Operating Systems. October, 1996. pp. 128-137. [pdf]
  • "An analytical model for designing memory hierarchies", B. Jacob, P. Chen, S. Silverman, T. Mudge. IEEE Transactions on Computers. vol 45, no 10. October, 1996. pp. 1180-1194. [pdf]
  • "Timing verification of sequential domino circuits", D. Van Campenhout, T. Mudge, K. Sakallah. TechCon 96. September, 1996. [Available as an electronic document to members of Semiconductor Research Corp.] [pdf]
  • "The trading function in action", B. L. Jacob, T. Mudge. 7th ACM SIGOPS European Workshop. September, 1996. Connemara, Ireland. pp. 241-247. [pdf]
  • "Rapid prototyping & evaluation of high-performance computers", R. Brown, J. Hayes, T. Mudge. Conference on Experimental Research in Computer Systems, NSF Experimental Systems. June, 1996. Washington DC. pp. 159-168. [pdf]
  • "A comparison of two common pipeline structures", M. Golden, T. Mudge. Institution of Electrical Engineers Proc.-E, Computers and Digital Techniques. vol 143, no 3. May, 1996. [pdf]
  • "Position paper: NSF Workshop on Critical Issues", T. Mudge. Computer Architecture Research. May, 1996. [Electronic document]
  • "Correlation and aliasing in dynamic branch predictors", S. Sechrest, C-C. Lee, T. Mudge. The 23rd Annual International Symposium on Computer Architecture. May, 1996. pp. 22-32. [pdf]
  • "Panel report: "How can computer architecture researchers avoid becoming the society for irreproducible results?"", T. Mudge. Computer Architecture News. vol 24, no 1. March, 1996. pp. 1-5. [pdf]
  • "The role of adaptivity in two-level branch prediction", S. Sechrest, C-C. Lee, T. Mudge. 28th Annual IEEE/ACM Symposium on Microarchitecture. December, 1995. pp. 264-270. [pdf]
  • "A parallel genetic algorithm for multi-objective microprocessor design", T. J. Stanley, T. Mudge. 6th International Conference on Genetic Algorithms. July, 1995. pp. 597-604. [pdf]
  • "Critical paths in circuits with level-sensitive latches", K. Sakallah, T. Burks, T. Mudge. IEEE Transactions on VLSI Systems. vol 3, no 2. June, 1995. pp. 273-291. [pdf]
  • "Instruction fetching: Coping with code bloat", R. Uhlig, D. Nagle, T. Mudge, S. Sechrest, J. Emer. The 22nd Annual International Symposium on Computer Architecture. June, 1995. pp. 345-356. [pdf]
  • "A Verilog preprocessor for representing datapath components", B. Davis, T. Mudge. 4th International Verilog HDL Conference. March, 1995. pp. 90-98. [pdf]
  • "A systematic approach to multi-objective computer architecture optimization", T. J. Stanley, T. N. Mudge. 1995 Conference on Advanced Research in VLSI. March, 1995. pp. 286-300. [pdf]
  • "Instrumentation tools", J. Pierce, M. D. Smith, T. Mudge. (Eds.) T. M. Conte, C. E. Gimarc. Kluwer Academic Publishers. Fast Simulation of Computer Architectures. 1995. pp. 47-86. [pdf]
1994-1990
  • "A comparison between two pipeline organizations", M. Golden, T. Mudge. 27th Annual IEEE/ACM Symposium on Microarchitecture. December, 1994. pp. 153-161. [pdf]
  • "Resource allocation in a high clock rate microprocessor", M. Upton, T. Huff, T. Mudge, R. Brown. 6th International Conference on Architectural Support for Programming Languages and Operating Systems. October, 1994. pp. 98-109. [pdf]
  • "Trap-driven simulation with Tapeworm II", R. Uhlig, D. Nagle, T. Mudge, S. Sechrest. 6th International Conference on Architectural Support for Programming Languages and Operating Systems. October, 1994. pp. 132-144. [pdf]
  • "Design trade-offs for software-managed TLBs", D. Nagle, R. Uhlig, T. Stanley, T. Mudge, S. Sechrest, R. Brown. ACM Transactions on Computer Systems. vol 12, no 3. August, 1994. pp. 175-205. [pdf]
  • "Kernel-based memory simulation", D. Nagle, R. Uhlig, T. Mudge, S. Sechrest. ACM SIGMETRICS Conference on Measurement and Modeling of Computer Systems. May, 1994. pp. 286-287. [pdf]
  • "Optimal allocation of on-chip memory for multiple-API operating systems", D. Nagle, R. Uhlig, T. Mudge, S. Sechrest. The 21st Annual International Symposium on Computer Architecture. April, 1994. pp. 358-369. [pdf]
  • "The effect of speculative execution on cache performance", J. Pierce, T. Mudge. International Parallel Processing Symposium. April, 1994. Cancun, Mexico. pp. 172-179. [pdf]
  • "IDtrace - A tracing tool for i486 simulation", J. Pierce, T. Mudge. MASCOTS. January, 1994. pp. 419-420. [pdf]
  • "A microarchitectural performance evaluation of a 3.2 GB/s microprocessor bus", T. Stanley, M. Upton, P. Sherhart, T. Mudge, R. B. Brown. The Annual ACM/IEEE International Symposium on Microarchitecture. December, 1993. Austin, Texas. pp. 31-40. [pdf]
  • "Gallium arsenide process evaluation based on a RISC microprocessor example", R. Brown, M. Upton, Ch, A. Chandna, T. Huff, T. Mudge, R. Oettel. IEEE Journal on Solid-State Circuits. vol 28, no 10. October, 1993. pp. 1030-1037. [pdf]
  • "Synchronization of pipelines", K. Sakallah, T. Mudge, T. Burks, E. Davidson. IEEE Transactions on CAD of IC's and Systems. vol 12, no 8. August, 1993. pp. 1132-1146. [pdf]
  • "The Aurora project", T. Huff, M. Upton, T. Mudge, R. Brown. Record of Hot Chips V. August, 1993. pp. 3.2.1-3.2.12. [pdf]
  • "Design tradeoffs for software-managed TLBs", D. Nagle, R. Uhlig, T. Stanley, T. Mudge, S. Sechrest, R. Brown. The 20th Annual International Symposium on Computer Architecture. May, 1993. pp. 27-38. [pdf]
  • "The impact of signal transition time on path delay computation", A. Kayssi, T. Mudge, K. Sakallah. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. vol 40, no 5. May, 1993. pp. 302-309. [pdf]
  • "A 160,000 transistor GaAs microprocessor", M. Upton, T. Huff, P. Sherhart, P. Barker, R. McVay, T. Stanley, R. Brown, R. Lomax, T. Mudge, K. Sakallah. International Solid-State Circuits Conference Digest of Technical Papers. vol 36. February, 1993. pp. 92-93. [pdf]
  • "A high performance GaAs microprocessor", T. Huff, M. Upton, P. Sherhart, P. Barker, R. McVay, T. Stanley, R. Brown, R. Lomax, T. Mudge, K. Sakallah. IEEE Laser and Optics Society Sarnoff Symposium, Princeton. March 1993.[no page numbers] [pdf]
  • "Identification of critical paths in circuits with level-sensitive latches", T. Burks, K. Sakallah, T. Mudge. International Conference on CAD. November, 1992. pp. 137-141. [pdf]
  • "GaAs RISC processors", R. Brown, P. Barker, A. Chandna, T. Huff, A. I. Kayssi, R. Lomax, T. Mudge, D. Nagle, K. Sakallah, P. Sherhart, R. Uhlig, M. Upton. GaAs IC Symposium. October, 1992. Miami, Florida. pp. 81-84. [pdf]
  • "Performance optimization of pipelined primary caches", O. Olukotun, T. Mudge, R. Brown. 19th Annual International Symposium on Computer Architecture. May, 1992. pp. 181-190. [pdf]
  • "Impact of MCMs on system performance optimization", A. Kayssi, K. Sakallah, R. Brown, R. Lomax, T. Mudge, T. Huff. 1992 IEEE International Symposium on Circuits and Systems. vol 2. May, 1992. San Diego, California. pp. 919-922. [pdf]
  • "Analysis and design of latch-controlled synchronous digital circuits", K. Sakallah, T. Mudge, O. Olukotun. IEEE Transactions on CAD of ICs and Systems. vol 11, no 3. March, 1992. pp. 322-333. [pdf]
  • "Multi-phase retiming using minTc", T. Burks, K. Sakallah, T. Mudge. TAU 92: 1992 ACM/SIGDA Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Princeton University. March, 1992. [pdf]
  • "Synthesis and verification of a GaAs microprocessor from a Verilog hardware description", R. Brown, Ch, A. Chandna, T. Hoy, T. Huff, D. Johnson, R. Lomax, T. Mudge, D. Nagle, O. Olukotun, K. Sakallah, R. Uhlig, M. Upton. Open Verilog International User Group Meeting. March, 1992. pp. 85-93.
  • "Measuring process migration effects using an MP simulator", A. Ladd, T. Mudge, O. Olukotun. (Eds.) M. Dubois, S. Thakkar. Kluwer Academic Publ.. Scalable Shared Memory Multiprocessors. 1992. pp. 97-129. [pdf]
  • "Parallel language constructs for efficient parallel processing", R. Clapp, T. Mudge. Hawaii International Conference on System Sciences. January, 1992. pp. 230-241. [pdf]
  • "Compound semiconductor device requirements for VLSI", R. Brown, A. Chandna, T. Huff, R. Lomax, T. Mudge, R. Oettel, M. Upton. 19th International Symposium on GaAs and Related Compounds, (Institute of Physics Conf. Series No. 129). 1992. Karuizawa. pp. 857-862. [pdf]
  • "Optimal clocking of circular pipelines", International Conference on Computer Design: VLSI in Computers and Processors. October, 1991. pp. 642-646. [pdf]
  • "Multilevel optimization in the design of a high-performance GaAs microcomputer", O. Olukotun, R. Brown, R. Lomax, T. Mudge, K. Sakallah. IEEE Journal on Solid-State Circuits. vol 16, no 5. May, 1991. pp. 763-767. [pdf]
  • "Implementing a cache for a high-performance GaAs microprocessor", O. Olukotun, T. Mudge, R. Brown. The 18th Annual International Symposium on Computer Architecture. May, 1991. pp. 138-147. [pdf]
  • "Impact of MCMs on system performance", A. Kayssi, K. Sakallah, R. Brown, R. Lomax, T. Mudge, T. Huff. 1991 Multichip Module Workshop, University of California. March, 1991. Santa Cruz, California. pp. 58-65. [pdf]
  • "The design of a micro-supercomputer", T. Mudge, R. Brown, W. Birmingham, J. Dykstra, A. Kayssi, R. Lomax, O. Olukotun, K. Sakallah. Computer. January, 1991. pp. 57-64. [pdf]
  • "The design of a GaAs micro-supercomputer", T. Mudge, R. Brown, W. Birmingham, J. Dykstra, A. Kayssi, R. Lomax, O. Olukotun, K. Sakallah. Hawaii International Conference on System Sciences. January, 1991. pp. 421-432. [pdf]
  • "checkTc and minTc: Timing verification and optimal clocking of synchronous digital circuits", K. Sakallah, T. Mudge, O. Olukotun. IEEE International Conference on Computer-Aided Design. November, 1990. pp. 552-555. [pdf]
  • "Optimal clocking of synchronous systems", K. Sakallah, T. Mudge, O. Olukotun. TAU 90: 1990 ACM International Workshop Timing Issues in the Specification and Synthesis of Digital Systems. August, 1990. pp. 21. [pdf]
  • "Analysis and design of latch-controlled synchronous digital circuits", K. Sakallah, T. Mudge, O. Olukotun. The 27th ACM/IEEE Design Automation Conference. June, 1990. pp. 111-117. [Nominated for best paper] [pdf]
  • "ADA performance issues", R. Clapp, T. Mudge. Ada Letters. vol X, no 3. 1990. [Chapters 1, 2, 3, 4, 5, 6, and 8] [pdf]
  • "Hierarchical gate array routing on a hypercube multiprocessor", O. Olukotun, T. Mudge. Journal of Parallel and Distributed Computing. 1990. pp. 313-324. [pdf]
  • "Performance of parallel loops using alternative cache consistency protocols on a non-bus multiprocessor", R. Clapp, T. Mudge, J. Smith. (Eds.) M. Dubois, S. Thakkar. Kluwer Academic Publ.. Cache and Interconnect Architectures in Multiprocessors. 1990. pp. 131-152. [pdf]
  • "Cache coherence requirements for interprocess rendezvous", R. Clapp, T. Mudge, D. Winsor. International Journal of Parallel Programming. vol 9, no 1. January, 1990. pp. 31-51. [pdf]
  • "Report On The Embedded AI Languages Workshop", R. Volz, T. Mudge, G. Linstrom, The University of Michigan, Ann Arbor MI, January 1990, pp. 34. [pdf]
1989-1985
  • "Efficient recognition of partially visible objects using a logarithmic complexity matching technique", P. Gottschalk, J. Turney, T. Mudge. The International Journal of Robotics Research. vol 8, no 6. December, 1989. pp. 110-130. [pdf]
  • "Hypercube supercomputers", J. Hayes, T. Mudge. Proceedings of the IEEE. vol 77, no 12. December, 1989. pp. 1829-1841. [pdf]
  • "Ada on a hypercube", R. Clapp, T. Mudge. Ada Letters. March, 1989. pp. 118-128. [pdf]
  • "Translation and execution of distributed Ada programs: Is it still Ada?", R. Volz, T. Mudge, G. Buzzard, P. Krishnan. IEEE Transactions on Software Engineering. vol 15, no 3. March, 1989. pp. 281-292. [pdf]
  • "A parallel language for a hypercube multiprocessor", R. Clapp, T. Mudge. 4th Conference on Hypercubes, Concurrent Computers & Applications. vol I. March, 1989. pp. 515-522. [pdf]
  • "Short-latency routing for hypercube multiprocessors", G. Buzzard, T. Mudge. 4th Conference on Hypercubes, Concurrent Computers & Applications. vol I. March, 1989. pp. 285-291. [pdf]
  • "Efficient encoding of local shape: Features for 3-d object recognition", P. Gottschalk, T. Mudge. The 1988 SPIE Cambridge Symposium on Optical and Optoelectronic Engineering Intelligent Robots and Computer Vision: Seventh in a Series, SPIE. November, 1988. Cambridge, Massachusetts. [pdf]
  • "Analysis of bus hierarchies for multiprocessor", D. Winsor, T. Mudge. The 15th Annual International Symposium on Computer Architecture. May, 1988. pp. 100-107. [pdf]
  • "High performance hypercube communications", G. Buzzard, T. Mudge. 3rd International Conference on Hypercube Concurrent Computers & Applications. January, 1988. pp. 600-609. [pdf]
  • "Parallel branch and bound algorithms", T. Abdelrahman, T. Mudge. 3rd International Conference on Hypercube Concurrent Computers & Applications. January, 1988. pp. 1492-1499. [pdf]
  • "Ada on a hypercube", R. Clapp, T. Mudge. 3rd International Conference on Hypercube Concurrent Computers & Applications. January, 1988. pp. 399-408. [pdf]
  • "Wanted: A new generation of software manufacturing", R. Volz, T. Mudge, A. Naylor. (Eds.) N. Malagardis, T. Williams. Standards and Information Technology and Industrial Control. 1988. Amsterdam. pp. 153-168. [pdf]
  • "Parallel branch-and-bound algorithms on hypercube multiprocessors", T. Abdel-Rahman, T. Mudge. 3rd SIAM Conference on Parallel Processing for Scientific Computing. Dec, 1987. [Abstract] [pdf]
  • "Instruction level mechanisms for accurate real-time task scheduling", R. Volz, T. Mudge. IEEE Transactions on Computers. vol C-36, no 8. August, 1987. pp. 988-993. [pdf]
  • "Crosspoint cache architectures", D. Winsor, T. Mudge. The 1987 International Conference on Parallel Processing. August, 1987. pp. 266-269. [pdf]
  • "A preliminary investigation into parallel routing on a hypercube computer", O. Olukotun, T. Mudge. The 24th Design Automation Conference. June, 1987. Miami Beach, Florida. pp. 814-820. [pdf]
  • "Multiple bus architectures", T. Mudge, J. Hayes, D. Winsor. Computer. June, 1987. pp. 42-48. [pdf]
  • "Units of distribution for distributed Ada", T. Mudge. The International Workshop on Real-Time Ada Issues, Ada UK and SIGAda. May, 1987. Devon, England. [also appears in Ada Letters, vol. VII, no. 6, Fall 1987. pp. 64-66] [pdf]
  • "Timing issues in the distributed execution of Ada programs", R. Volz, T. Mudge. IEEE Transactions on Computers. vol C-36, no 4. April, 1987. pp. 449-459. [pdf]
  • "Two-dimensional partially visible object recognition using efficient multidimensional range queries", P. Gottschalk, J. Turney, T. Mudge. The 1987 International Conference on Robotics and Automation. April, 1987. pp. 380-386. [pdf]
  • "Range image segmentation and surface parameter extraction for 3-D object recognition of industrial parts", J. Han, R. Volz, T. Mudge. The 1987 International Conference on Robotics and Automation. April, 1987. pp. 1582-1589. [pdf]
  • "Vision algorithms for hypercube machines", T. Mudge, T. Abdel-Rahman. Journal of Parallel and Distributed Computing. 1987. pp. 79-94. [pdf]
  • "Architectures for robot vision", T. Mudge, T. Abdel-Rahman. (Eds.) J. Graham. Gordon and Breach Science Publ.. Specialized Computer Architectures for Robotics and Automation. 1987. pp. 103-149. [pdf]
  • "Automatic generation of salient features for the recognition of partially occluded parts", T. Mudge, J. Turney, R. Volz. Robotica. vol 5. 1987. pp. 117-127. [pdf]
  • "A memory interference model for multi-processors based on semi-Markov processes", T. Mudge, H. Al-Sadoun, B. Makrucki. Institution of Electrical Engineers Proc. E, Computers and Digital Techniques. vol 134 Part E, no 4. 1987. pp. 203-214. [pdf]
  • "A high performance operating system for the NCUBE", T. Mudge, G. Buzzard, T. Abdel-Rahman. (Eds.) M. Heath. Hypercube Multiprocessors. 1987. [pdf]
  • "Monte Carlo photon transport on the NCUBE", W. Martin, T-C. Wan, Pol, , D., T. Mudge, T. Abdel-Rahman. (Eds.) M. Heath. Hypercube Multiprocessors. 1987. [pdf]
  • "Hypercube computer research at The University of Michigan", J. Hayes, R. Jain, W. Martin, T. Mudge, L. Scott, K. Shin, Q. Stout. (Eds.) M. Heath. Hypercube Multiprocessors. 1987. [pdf]
  • "Monte Carlo photon transport on shared memory and distributed memory parallel processors", W. Martin, T. Wan, T. Abdel-Rahman, T. Mudge. The International Journal of Supercomputer Applications. vol 1, no 3. 1987. pp. 57-74. [pdf]
  • "An Analysis of hypercube architectures for image pattern recognition algorithms", T. Mudge. The Society of Photo-optical Instrumentation Engineers Optoelectronics and Laser Applications in Science and Engineering, Image Pattern Recognition Algorithm Implementations, Techniques, and Technology: Critical Review of Technology, SPIE. vol 755. January, 1987. Los Angeles, California. pp. 71-83. [pdf]
  • "Instruction level mechanisms for accurate real-time task scheduling", R. Volz, T. Mudge. The 1986 Real-time Systems Symposium. December, 1986. pp. 209-215. [pdf]
  • "Solutions to the N queens problem using tasking in Ada", R. Clapp, T. Mudge, R. Volz. SIGPLAN Notices. vol 21, no 12. December, 1986. pp. 99-110. [pdf]
  • "A microprocessor-based hypercube supercomputer", J. Hayes, T. Mudge, Q. Stout, S. Colley, J. Palmer. IEEE MICRO. October, 1986. pp. 6-17. [Best IEEE MICRO article of 1986] [pdf]
  • "Translation and execution of distributed Ada programs: Is it still Ada?", R. Volz, T. Mudge, G. Buzzard, P. Krishnan. The Society of Photo-optical Instrumentation Engineers Cambridge Symposium Advances in Intelligent Robotics Systems, SPIE. vol 727. October, 1986. Cambridge, Massachusetts. [pdf]
  • "Architectures of a hypercube supercomputer", J. Hayes, T. Mudge, Q. Stout, S. Colley, J. Palmer. The 1986 International Conference on Parallel Processing. August, 1986. pp. 653-660. [pdf]
  • "Solving the bin of parts problem", J. Turney, T. Mudge, R. Volz. Vision '86, a Machine Vision Association of the SME Conference and Exposition. June, 1986. Detroit, Michigan. pp. 4-21 -- 4-38. [pdf]
  • "The next generation of hypercube computers", T. Mudge. The ARO Workshop Future Directions in Computer Architecture and Software. May, 1986. pp. 273-275. [pdf]
  • "Ada in a manufacturing environment", R. Volz, T. Mudge, A. Naylor, B. Brosgol. The Control Engineering Conference and Exposition. May, 1986. Rosemont, Illinois. pp. 433-440. [pdf]
  • "Hierarchical decomposition and simulation of manufacturing cells using Ada", C. Antonelli, R. Volz, T. Mudge. Simulation. vol 46, no 4. April, 1986. pp. 141-152. [pdf]
  • "Toward real-time performance benchmarks for Ada", R. Clapp, L. Duchesneau, R. Volz, T. Mudge, T. Schultze. Communications of the ACM. vol 29, no 8. 1986. pp. 760-778. [pdf]
  • "Analysis of multiple-bus interconnection networks", T. Mudge, J. Hayes, G. Buzzard, D. Winsor. Journal of Parallel and Distributed Computing. 1986. pp. 328-343. [pdf]
  • "Determining the pose of an object", R. Dolezal, T. Mudge, J. Turney, R. Volz. The Society of Photo-optical Instrumentation Engineers 2nd International Symposium on Completed Vision for Robotics, SPIE. vol 595. December, 1985. Cannes. pp. 68-71. [pdf]
  • "Vision algorithms for hypercube machines", T. Mudge. The IEEE Workshop on Computer Architecture for Pattern Analysis and Image Database Management. November, 1985. pp. 225-230. [pdf]
  • "A semi-Markov model for the performance of multiple-bus systems", T. Mudge, H. B. Al-Sadoun. IEEE Transactions on Computers. vol C-34, no 10. October, 1985. pp. 934-942. [pdf]
  • "A semi-Markov model for the performance of multiple-bus systems", T. Mudge, H. B. Al-Sadoun. The 1985 International Conference on Parallel Processing. August, 1985. pp. 521-530. [pdf]
  • "Recognizing partially occluded parts", J. Turney, T. Mudge, R. Volz. IEEE Transactions on Pattern Analysis and Machine Intelligence. vol PAMI-7, no 4. July, 1985. pp. 410-421. [pdf]
  • "Interconnecting off-the-shelf microprocessors", H. B. Al-Sadoun, O. Olukotun, T. Mudge. The National Computer Conference. vol 54. July, 1985. pp. 175-181. [pdf]
  • "Some problems in distributing real-time Ada programs across machines", R. Volz, T. Mudge, A. Naylor, J. Mayer. (Eds.) J. Barnes, G. Fischer. The 1985 International Ada Conference. May, 1985. pp. 72-84. [pdf]
  • "Recognizing partially hidden objects", J. Turney, T. Mudge, R. Volz. The IEEE International Conference on Robotics and Automation. March, 1985. pp. 48-54. [pdf]
  • "Object-based computing and the Ada programming language", G. Buzzard, T. Mudge. Computer. March, 1985. pp. 11-19. [Also in: Object Oriented Computing, (Ed.) G. Peterson, IEEE Computer Society Press 1987, pp. 115-123] [pdf]
  • "Some problems in distributing real time Ada programs across machines", R. Volz, T. Mudge, J. Mayer. IEEE Computer Society Technical Committee Real-Time Systems Newsletter. February, 1985, pp. 72-84. [pdf] [Abstract. Also presented at the IEEE Second Workshop Real-Time Operating Systems Nov. 1984] [pdf]
  • "System design for local neighborhood processing", P. Leonard, T. Mudge. The Society of Photo-optical Instrumentation Engineers Los Angeles Symposium Algorithms for Image Processing. January, 1985, 5 pp. [pdf]
1984-
  • "Unifying robot arm control", T. Mudge, J. Turney. IEEE Transactions on Industry Applications. vol IA-20, no 6. November, 1984. pp. 1554-1563. [pdf]
  • "Memory interference models with variable interconnection time", T. Mudge, H. B. Al-Sadoun. IEEE Transactions on Computers. vol C-33, no 11. November, 1984. pp. 1033-1038. [pdf]
  • "Recognizing partially hidden objects", J. Turney, T. Mudge, R. Volz. The Society of Photo-optical Instrumentation Engineers Cambridge Symposium on Intelligent Robots and Computer Vision. November, 1984. pp. 108-113. [pdf]
  • "Hierarchical decomposition and simulation of manufacturing cells", C. Antonelli, R. Volz, T. Mudge. The 1984 Winter Simulation Conference. November, 1984. pp. 415-423. [pdf]
  • "Using Ada as a programming language for robot-based manufacturing cells", R. Volz, T. Mudge, D. Gal. IEEE Transactions on Systems, Man and Cybernetics. vol SMC-14, no 6. November, 1984. pp. 863-878. [pdf] [Also in: Object Oriented Computing, (Ed.) G. Peterson, IEEE Computer Society Press 1987, pp. 99-114. and: Control and Programming in Advanced Manufacturing, (Ed.) K. Rathmill, IFS Ltd. (Springer-Verlag), 1988: Bedford, UK]
  • "A class of cellular architectures to support physical design automation", R. Rutenbar, T. Mudge, D. Atkins. IEEE Transactions on CAD of IC's and Systems. vol CAD-3, no 4. October, 1984. pp. 264-278. [pdf]
  • "Robots are (nothing more than) abstract data types", R. Volz, T. Mudge. The SME Conference on Robotics Research: The Next 5 Years and Beyond, (The First World Conference on Robotics Research). August, 1984. [pdf]
  • "Analysis of multiple-bus interconnection networks", T. Mudge, J. Hayes, G. Buzzard, D. Winsor. The 1984 Conference on Parallel Processing. August, 1984. pp. 228-232. [pdf] [Also in: Advanced Computer Architecture, Ed. D. Agrawal, IEEE Computer Society Press 1986, pp. 155-159]
  • "CAD, robot programming and Ada", R. Volz, T. Mudge, A. Woo, J. Turney, D. Gal. (Eds.) M. Brady, L. Gerhardt, H. Davidson. Springer-Verlag. Robotics and Artificial Intelligence, NATO Advanced Studies Institute Series, Series F: Computer and System Sciences. vol 11. 1984. pp. 229-246. [pdf]
  • "Experiments in occluded parts recognition", T. Mudge, J. Turney, R. Volz. The Society of Photo-optical Instrumentation Engineers Cambridge Symposium on Intelligent Robots, SPIE. vol 449 (part 2). November, 1983. pp. 719-725.
  • "Case study of a program for the recognition of occluded parts", T. Mudge, T. Abdel-Rahman. The 2nd Annual IEEE Computer Society Workshop Computer Architecture for Pattern Analysis and Image Data Base Management. October, 1983. Pasadena, California. pp. 56-60.
  • "Wire routing experiments on a raster pipeline Subarray Machine", R. Rutenbar, T. Mudge, D. Atkins. The IEEE International Conference on CAD. September, 1983. pp. 135-136.
  • "Efficiency of feature dependent algorithms for the parallel processing of images", T. Mudge, T. Abdel-Rahman. The International Conference on Parallel Processing. August, 1983. pp. 369-373.
  • "Teaching assembly language programming with ZIP, a Z80 assembly language interpreter", G. Buzzard, T. Mudge. IEEE Transactions on Education. vol E-26, no 3. Aug, 1983. pp. 91-98.
  • "Using Ada as a robot system programming language", R. Volz, T. Mudge, D. Gal. The 13th International Symposium on Industrial Robots and Robots 7 Conference. April, 1983. Chicago, Illinois. pp. 12-42 -- 12-57.
  • "Experiments in occluded parts recognition using the generalized Hough transform", J. Turney, T. Mudge, R. Volz, M. Diamond. The Conference on Artificial Intelligence, Oakland University. April, 1983. Rochester, Michigan.
  • "Object-based computer architectures", T. Mudge, G. Buzzard, D. Verhaeghe, J. Hill, D. Winsor. The 1983 Conference on Information Sciences and Systems, The Johns Hopkins University. March, 1983. pp. 733-741. [pdf]
  • "Advanced control for multirobot assembly systems", C. Lee, T. Mudge. The 10th Conference on Production Research and Technology, (NSF Grantees Conference). February, 1983. Detroit, Michigan. pp. 129-135.
  • "Unifying robot arm control", T. Mudge, J. Turney. The 1982 Annual Meeting of the Industry Applications Society. October, 1982. pp. 1315-1324. [Also appears in: IEEE Trans. Industry Applications]
  • "An approximate queueing model for packet switched multistage interconnection networks", T. Mudge, B. Makrucki. The 3rd International Conference Distributed Computing Systems. October, 1982. pp. 556-562.
  • "Hardware/software transparency in robotics through object level design", T. Mudge, R. Volz, D. Atkins. The Society of Photo-optical Instrumentation Engineers Technical Symp. West, SPIE. vol 360. Aug, 1982. pp. 216-223.
  • "Image coding using the multimicroprocessor system PASM", T. Mudge, E. Delp, L. Siegel, H. Siegel. The IEEE Computer Society Conference on Pattern Recognition and Image Processing. June, 1982. pp. 200-205.
  • "On the control of mechanical manipulators", C. Lee, M. Chung, T. Mudge, J. Turney. The 6th International Federation of Automatic Control Symposium on Identification and System Parameter Estimation. June, 1982. pp. 1454-1459.
  • "Cellular image processing techniques for VLSI circuit layout validation and routing", T. Mudge, R. Rutenbar, R. Lougheed, D. Atkins. The 19th Annual Design Automation Conference. June, 1982. pp. 537-543. [Also appears in: Selected Reprints VLSI Technologies and Computer Graphics, Henry Fuchs, IEEE Computer Society Press, 1983, pp. 484-490] [pdf]
  • "Parallel processing for computer vision", E. Delp, T. Mudge, L. Siegel, H. Siegel. The Society of Photo-optical Instrumentation Engineers Technical Symposium East. vol 336 (Robot Vision). May, 1982. pp. 161-167.
  • "Analysis of multistage networks with unique interconnection paths", T. Mudge, B. Makrucki. The 14th Southeastern Symposium on System Theory. April, 1982. pp. 7-11.
  • "Probabilistic analysis of a crossbar switch", T. Mudge, B. Makrucki. The 9th Annual International Symposium on Computer Architecture. April, 1982. pp. 311-319. [pdf]
  • "Analysis of a multiport memory", T. Mudge, B. Makrucki. The 16th Annual Conference on Information Sciences and Systems, Princeton University. March, 1982. pp. 639-643.
  • "Special purpose architectures for computer vision", T. Mudge, E. Delp. The 15th Hawaii International Conference on Systems Science. January, 1982. pp. 378-387.
  • "Hierarchical control structure using special purpose processors for the control of robot arms", C. Lee, T. Mudge, J. Turney. The IEEE Computer Society Conference on Pattern Recognition and Image Processing. 1982. pp. 634-640. [Also appears in: Tutorial Robotics, C.S.G. Lee, R. Gonzalez, and K. Fu, IEEE Computer Society Press, 1983, pp. 181-187]
  • "Special purpose VLSI processors for industrial robots", T. Mudge. The IEEE Computer Society's 5th International Computer Software and Applications Conference. November, 1981. pp. 270-271. [pdf]
  • "Block truncation coding on PASM", L. Siegel, E. Delp, T. Mudge, H. Siegel. The 19th Annual Allerton Conference on Communications, Control, and Computing. October, 1981. pp. 891-900. [pdf]
  • "Teaching assembly language using an assembly language interpreter", T. Mudge. The 1981 National Conference of the American Society for Engineering Education, University of Southern California. June, 1981. pp. 22-27. [Winner of the Curtis Award for best paper in the Computers in Education Division] [pdf]
  • "VLSI implementation of a numerical processor for robotics", J. Turney, T. Mudge. The 27th International Instrumentation Symposium. April, 1981. Indianapolis, Indiana. pp. 169-175. [Received a Best Paper Award. Also presented at the Instrument Society of America Anaheim Conf., Oct., 1981] [pdf]
  • "Cellular image processing techniques for checking VLSI circuit layouts", T. Mudge, R. Lougheed, W. Teel. The 15th Annual Conference on Information Sciences and Systems, The Johns Hopkins University. March, 1981. pp. 315-320. [pdf]
  • "Cellular image processing techniques for checking VLSI circuit layouts" (Abstract), T. Mudge, R. Lougheed, W. Teel. Abstracts of the 1981 ACM Computer Science Conf., St. Louis, February 1981, p.29.
  • "A course sequence in microprocessor-based digital systems design", T. Mudge. IEEE Transactions on Education. vol E-24, no 1. February, 1981. pp. 14-21. [Honorable mention for runner-up to the best paper published in the Transactions in the year 1981] [pdf]
  • "Design rule checking for VLSI circuits using a cellular computer", T. Mudge, R. Lougheed, W. Teel. Abstracts of the 1981 ACM Computer Science Conference. February, 1981. St. Louis. pp. 29. [Abstract] [pdf]
  • "Design language for asynchronous multiprocessor systems", T. Mudge. Report on the Workshop on Self-Timed Systems, MIT. May, 1980. pp. 13. [Abstract]
  • "A distributed operating system machine", T. Mudge. The Louisiana Computer Exposition on Distributed Systems Based on Mini and Micro Computers, University of Southwestern Louisiana. March, 1979. pp. 143-166. [pdf]
  • "A distributed operating system machine", T. Mudge. The 1979 Conference on Information Sciences and Systems, The Johns Hopkins University. March, 1979. pp. 472-477.
  • "A computer architecture for parallel processing", T. Mudge. The 16th Annual Allerton Conference on Communications, Control, and Computing. October, 1978. pp. 596.
  • "A data driven computer architecture", T. Mudge. The 1978 Conference on Information Sciences and Systems, The Johns Hopkins University. March, 1978. pp. 365-370.
  • "Characteristics of some augmented Petri nets", J. Smith, T. Mudge. The 14th Annual Allerton Conference on Circuit and System Theory. October, 1976. pp. 606-615. [pdf]
  • "Specifying a design language for digital systems", The 13th Annual Allerton Conference on Circuit and System Theory. October, 1975. pp. 906-915.
  • 2010
    • "Is Storage Hierarchy Dead? Co-located Compute-Storage NVRAM-based Architectures for Data-Centric Workloads", D. Roberts, J. Chang, P. Ranganathan, T. Mudge. HP Laboratories, HPL-2010-119, November 2010. [pdf]
    • "Data Dwarfs: Motivating a Coverage Set for Future Large Data Center Workloads", M. Shah, P. Ranganathan, J. Chang, N. Tolia, D. Roberts, T. Mudge. HP Laboratories, HPL-2010-115, November 2010. [pdf]
  • 2004
    • "Design and Applications of a Virtual Context Architecture", D. Oehmke, N. Binkert, S. Reinhardt, T. Mudge. CSE-TR-497-04. September 2004. [pdf]
  • 2000
    • "The Need for Large Register Files in Integer Codes," M. Postiff, D. Greene, T. Mudge. Department of Electrical and Computer Engineering, The University of Michigan, CSE-TR-434-00, December 2000 [pdf]
    • "The MIRV SimpleScalar/PISA Compiler", M. Postiff, D. Greene, C. Lefurgy, D. Helder, T. Mudge. Department of Electrical and Computer Engineering, The University of Michigan, CSE-TR-421-00, March 2000.[pdf]
  • 1999
    • "Smart Register Files for High-Performance Microprocessors," M. Postiff, T. Mudge. Department of Electrical and Computer Engineering, The University of Michigan, CSE-TR-403-99, June 1999 [pdf]
  • 1998
    • "Code Compression for DSP," C. Lefurgy, T. Mudge. Department of Electrical and Computer Engineering, The University of Michigan, CSE-TR-380-98, December 1998 [pdf]
    • "Performance Limits of Trace Caches", M. Postiff, G. Tyson, T. Mudge. Department of Electrical and Computer Engineering, The University of Michigan, CSE-TR-373-98, September 1998.[pdf]
  • 1997
    • "Improving Code Density Using Compression Techniques", C. Lefurgy, P. Bird, I-C. Chen, T. Mudge. Department of Electrical Engineering and Computer Science, The University of Michigan, CSE-TR-342-97. July 1997. [pdf]
    • "A Case Study of a Hardware-Managed TLB in a Multi-Tasking Environment", C. Lee, R. Uhlig, T. Mudge. Department of Electrical Engineering and Computer Science, The University of Michigan, CSE-TR-341-97. June 1997. [pdf]
    • "The Impact of Instruction Compression on I-cache Performance," I. Chen, P. Bird, T. Mudge. Department of Electrical and Computer Engineering, The University of Michigan, CSE-TR-330-97, February 1997 [pdf]
  • 1996
    • "An Instruction Stream Compression Technique", P. Bird, T. Mudge. Department of Electrical Engineering and Computer Science, The University of Michigan, CSE-TR-319-96. November, 1996. [pdf]
    • "Using Stall Cycles to Improve Microprocessor Performance", J. Dundas, T. Mudge. Department of Electrical Engineering and Computer Science, The University of Michigan, CSE-TR-301-96. September 1996. [pdf]
    • "Tagless Two-level Branch Prediction Schemes", I. Chen, C. Lee, M. Postiff, T. Mudge. Department of Electrical Engineering and Computer Science, The University of Michigan, CSE-TR-306-96. September 1996. [pdf]
    • "Specification of the PUMA memory management design," B. Jacob, T. Mudge. Department of Electrical and Computer Engineering, The University of Michigan, CSE-TR-314-96, August 1996 [pdf]
    • "Modeling Domino Logic for Static Timing Analysis", D. Van Campenhout, T. Mudge, K. Sakallah. Department of Electrical Engineering and Computer Science, The University of Michigan, CSE-TR-295-96. June 1996. [pdf]
    • "Timing Analysis of Domino Logic", D. Van Campenhout, T. Mudge, K. Sakallah. Department of Electrical Engineering and Computer Science, The University of Michigan, CSE-TR-296-96. June 1996. [pdf]
    • "Correlation and Aliasing in Dynamic Branch Predictors - Full Simulation Results", S. Sechrest, C. Lee, T. Mudge. Department of Electrical Engineering and Computer Science, The University of Michigan, CSE-TR-283-96. May 1996. [pdf]
    • "Faster Static Timing Analysis via Bus Compression", D. Van Campenhout, T. Mudge. Department of Electrical Engineering and Computer Science, The University of Michigan, CSE-TR-285-96. February 1996. [pdf]
    • Limits to Branch Prediction”, T. Mudge, I. Chen, J. Coffey. Department of Electrical Engineering and Computer Science, The University of Michigan, CSE-TR-282-96. January 1996. [pdf]
  • 1995
    • "Timing Analysis of Digital Systems with Gated Clocks," D. Van Campenhout, T. Mudge. Department of Electrical and Computer Engineering, The University of Michigan, CSE-TR-257-95, August 1995 [pdf]
    • "Notes on Calculating Computer Performance", B. Jacob, T. Mudge. Department of Electrical and Computer Engineering, The University of Michigan, CSE-TR-231-95, March 1995.[pdf]
  • 1994
    • "Wrong-Path Instruction Prefetching," J. Pierce, T. Mudge. Department of Electrical and Computer Engineering, The University of Michigan, CSE-TR-222-94, November 1994 [pdf]
    • "IDtrace-A Tracing Tool for i486 Simulation", J. Pierce, T. Mudge. Department of Electrical and Computer Engineering, The University of Michigan, CSE-TR-203-94, March 1994.[pdf]
  • 1993
    • "Software TLB Management in OSF/1 and Mach 3.0", R. Uhlig, D. Nagel, T. Mudge, S. Sechrest. Department of Electrical and Computer Engineering, The University of Michigan, CSE-TR-147-92, December1992.[pdf]
    • "Hardware Support for Hiding Cache Latency", M. Golden, T. Mudge. Department of Electrical and Computer Engineering, The University of Michigan, CSE-TR-152-93, February 1993.[pdf]
  • 1992
    • "Monster: A Tool for Analyzing the Interaction Between Operating Systems and Computer Architectures", D. Nagle, R. Uhlig, T. Mudge. Department of Electrical and Computer Engineering, The University of Michigan, CSE-TR-147-92, November 1992.[pdf]
  • 1991
    • "Synchronization of Pipelines", K. Sakallah, T. Mudge, T. Burks, E. Davidson. Department of Electrical and Computer Engineering, The University of Michigan, CSE-TR-97-91, February 1991.[pdf]
  • 1990
    • "Algorithms for Timing Verification and Optimal Clocking of Synchronous Digital Circuits", K. Sakallah, T. Mudge, O. Olukotun. Department of Electrical and Computer Engineering, The University of Michigan, CSE-TR-71-90, September 1990.[pdf]
    • "Optimal Clocking of Synchronous Systems", K. Sakallah, T. Mudge, O. Olukotun. Department of Electrical and Computer Engineering, The University of Michigan, CSE-TR-65-90, June 1990. [pdf]
    • "Parallel Language Constructs for Efficient Parallel Processing", R. Clapp, T. Mudge, R. Milano. Department of Electrical and Computer Engineering, The University of Michigan, CSE-TR-66-90, June 1990. [pdf]
    • "A GaAs Micro-Supercomputer: Rationale and Design", R. Brown, J Dykstra, T. Mudge, R. Milano. Department of Electrical and Computer Engineering, The University of Michigan, CSE-TR-42-90, January 1990. [pdf]
  • 1989
    • "Analysis and Design of Latch-Controlled Synchronous Digital Circuits", K. Sakallah, T. Mudge, O. Olukotun. Department of Electrical and Computer Engineering, The University of Michigan, CRL-TR-31-89, October 1989.[pdf]
    • "Bus and Cache Memory Organizations for Multiprocessors", D. C. Winsor. Department of Electrical and Computer Engineering, The University of Michigan, CRL-TR-19-89, 1989. [copy of Ph.D. thesis] [pdf]
  • 1988
    • "Distributed ADA on a Loosely Coupled Multiprocessor", R. Clapp, T. Mudge. Department of Electrical and Computer Engineering, The University of Michigan, RSD-TR-03-88. February 1988. [pdf]
  • 1987
    • "Distributed Run-Time Support for ADA on the NCUBE Hypercube Multiprocessor", R. Clapp, T. Mudge, R. Volz. Department of Electrical and Computer Engineering, The University of Michigan, RSD-TR-10-87. August 1987. [pdf]
    • "An Algorithm for Model Based Recognition of Objects Using Range Maps", P. Gottschalk, T. Mudge. Department of Electrical and Computer Engineering, The University of Michigan, RSD-TR-3-87. February 1987. [pdf]
  • 1986
    • "Toward Real-Time Performance Bechmarks for ADA", R. Clapp, L. Duchesneau, R. Volz, T. Mudge, T. Schultze. Department of Electrical and Computer Engineering, The University of Michigan, RSD-TR-12-86. July 1986. [pdf]
    • "Translation and Execution of Distributed ADA Programs: Is it Still ADA", R. Volz, T. Mudge, G. Buzzard, P. Krishnan. Department of Electrical and Computer Engineering, The University of Michigan, RSD-TR-9-86. March 1986. [pdf]
  • 1985
    • "Comparisons Between ADA and LISP", P. Bhugra, T. Mudge. Department of Electrical and Computer Engineering, The University of Michigan, RSD-TR-9-85. October 1985.[pdf]
    • "Some Problems in Distributing Real-Time ADA Programs Across Machines", R. Volz, A. Naylor, T. Mudge, J. Mayer. Department of Electrical and Computer Engineering, The University of Michigan, RSD-TR-2-85. April 1985. [pdf]
  • 1984
    • "Hierarchical Decomposition and Simulation of Manufacturing Cells", C. Antonelli, R. Volz, T. Mudge. Department of Electrical and Computer Engineering, The University of Michigan, RSD-TR-18-84. November 1984.[pdf]
    • "A Semi-Markov Model for Memory Interference in Multiprocessors", T. Mudge, Humoud Al-Sadoun, B. Makrucki. Department of Electrical and Computer Engineering, The University of Michigan, CRL-TR-44-84. October 1984. [pdf]
    • "Memory Interface Models With Variable Connection Time", T. Mudge, Humoud Al-Sadoun. Department of Electrical and Computer Engineering, The University of Michigan, CRL-TR-16-84. July 1984. [pdf]
    • "A Stochastic Model of Multiprocessing", B. Makrucki. Department of Electrical and Computer Engineering, The University of Michigan, CRL-TR-23-84. March 1984.[copy of Ph.D. thesis] [pdf]
    • "User Manual for ZIP, A Z80 Assembly Language Interpreter Program", G. Buzzard, T. Mudge. Department of Electrical and Computer Engineering, The University of Michigan, CRL-TR-12-84. March 1984. [pdf]
    • "Analysis of Multiple-Bus Interconnection Networks", T. Mudge, J. Hayes, G. Buzzard, D. Winsor. Department of Electrical and Computer Engineering, The University of Michigan, CRL-TR-12-84. February 1984. [pdf]
  • 1983
    • "An Investigation of the Discrete Karhunen-Loeve Transform: Methods and Computational Aspects", M. Betker, E. Delp, T. Mudge. Department of Electrical and Computer Engineering, The University of Michigan, CRL-TR-35-83. Decembe, 1983. [pdf]
    • "Object-Based Computer Systems and The ADA Programming Language", G. Buzzard, T. Mudge. The Department of Electrical and Computer Engineering, The University of Michigan, CRL-TR-29-83. August 1983. [pdf]
    • "A Queueing Model of Delta Networks", B. Makrucki, T. Mudge. Department of Electrical and Computer Engineering, The University of Michigan, CRL-TR-26-83. August 1983. Reissue of two Systems Engineering Lab (now defunct) reports: SEL-TR-159 (January 1982) and SEL-TR-167 (August 1983). [pdf]
    • "Object-Based Computer Architectures", T. Mudge, G. Buzzard, D. Verhaeghe, J. Hill, D. Winsor. Department of Electrical and Computer Engineering, The University of Michigan, CRL-TR-18-83. April 1983. [pdf]
    • "Efficiency of Feature Dependent Algorithms for the Parallel Processing of Images", T. Mudge, T. Rahman. Department of Electrical and Computer Engineering, The University of Michigan, CRL-TR-11-83. March 1983. [pdf]
    • "A Class of Cellular Architectures to Support Physical Design Automation", R. Rutenbar, T. Mudge, D. Atkins. Department of Electrical and Computer Engineering, The University of Michigan, CRL-TR-10-83. February 1983. [pdf]
  • 1982
    • "A Stochastic Model of Parallel and Concurrent Program Execution on Multiprocessors", B. Makrucki, T. Mudge. Department of Electrical and Computer Engineering, The University of Michigan, CRL-TR-3-82. October 1982. [pdf]
    • "Note on a Queueing Model of Delta Networks", B. Makrucki, T. Mudge. Department of Electrical and Computer Engineering, The University of Michigan, SEL-TR-167. July 1982. [pdf]
    • "Bin of Parts Strategy", J. Turney, T. Mudge. Center for Robotics and Integrated Manufacturing, The University of Michigan, RSD-MEMO-1-82. May 1982. [pdf]
    • "On The Control of Mechanical Manipulators", C. Lee, M. Chung, T. Mudge, J. Turney. Center for Robotics and Integrated Manufacturing, The University of Michigan, RSD-TR-5-82. April 1982. [pdf]
    • "VLSI Crossbar Design Version Two", S. McFarling, J. Turney, T. Mudge. Department of Electrical and Computer Engineering, The University of Michigan, SEL-TR-165. February 1982. [pdf]
    • "A Queueing Model of Delta Networks", B. Makrucki, T. Mudge. Department of Electrical and Computer Engineering, The University of Michigan, SEL-TR-159. January 1982. [pdf]
  • 1981
    • "Connection Between Formulations of Robot Arm Dynamics with Applications to Simulation and Control", J. Turney, T. Mudge, C. Lee. Department of Electrical and Computer Engineering, The University of Michigan, RSD-TR-4-82. November, 1981. [pdf]
    • "A Multiple M/Dz/1/L Queueing Network Model of Crossbar-based Multiprocessors", B. Makrucki, T. Mudge. Department of Electrical and Computer Engineering, The University of Michigan, SEL-TR-157. September, 1981. [pdf]
    • "Probabilistic Analysis of a Crossbar Switch", B. Makrucki, T. Mudge. Department of Electrical and Computer Engineering, The University of Michigan, SEL-TR-150. March, 1981. [pdf]
    • "VLSI Design of a Crossbar Switch", B. Makrucki, T. Mudge. Department of Electrical and Computer Engineering, The University of Michigan, SEL-TR-149. January 1981. [pdf]
  • 1980
    • "Equivalence of Two Formulations For Robot Arm Dynamics", J. Turney, T. Mudge, C. Lee. Department of Electrical and Computer Engineering, The University of Michigan, SEL-TR-142. December 1980. [pdf]
    • "Equivalence of Two Formulations for Robot Arm Dynamics", J. Turney, T. Mudge, C. Lee. Center for Robotics and Integrated Manufacturing, The University of Michigan, RSD-TR-3-82. Decembe 1980. [pdf]
  • 1979
    • "A Data Driven Computer that Uses Lookahead without Associative Search", T. Mudge. Department of Electrical and Computer Engineering, The University of Michigan, SEL-TR-131. June 1979. [pdf]
    • "Application of Sorting Networks to Sparse Matrix Problems", T. Mudge, K. Hadavi. Department of Electrical and Computer Engineering, The University of Michigan, SEL-TR-130. May 1979. [pdf]
  • 1978
    • "A Data Driven Computer Architecture", T. Mudge. Department of Electrical and Computer Engineering, The University of Michigan, SEL-TR-117. January 1978. [pdf]
  • 1977
    • "A Computer Hardware Design Language for Multiprocessor Systems", T. Mudge. Department of Computer Science, University of Illinois at Urbana-Champaign, UILU-ENG-77-2234. September 1977. [pdf]
  • 1973
    • "SEMANTRIX: A Semantically Guided Digital Electronic Machine", T. Mudge. Department of Computer Science, University of Illinois at Urbana-Champaign, UIUCDCS-R-73-559. February 1973. [copy of M.S. thesis] [pdf]
  • 2014
    • "Error Recovery Within Integrated Circuit," K. Flautner, T. Austin, D. Blaauw, T. Mudge, D. Bull. USPTO Number: 8,650,470. February 11, 2014. [pdf]
  • 2013
    • "Crossbar Circuitry and Method of Operation of Such Crossbar Circuitry", S. Satpathy, D. Blaauw, T. Mudge, D. Sylvester, R. Dreslinski. USPTO Number: 8,549,207; 8,255,610; 8,230,152; 8,108,585. October 31, 2013; August 28, 2012; July 24, 2012; January 31, 2012.[pdf] [pdf] [pdf] [pdf]
    • "Error Recovery Within Processing Stages of an Integrated Circuit," K. Flautner, T. Austin, D. Blaauw, T. Mudge, D. Bull. USPTO Number: 8,407,537. March 26, 2013. [pdf]
    • "Vertical Interconnect Patterns in Multi-Layer Integrated Circuits", D. Blaauw, T. Mudge, D. Sylvester, R. Dreslinski Jr. USPTO Number: 8,381,155. February 19, 2013. [pdf]
    • “Random Number Generator”, T. Mudge, D. Blaauw, C. Tokunaga. USPTO Number: 8,346,832. January 1, 2013. [pdf]
  • 2012
    • "Cache Memory System for a Data Processing Apparatus" ,R. Dreslinski, G. Chen, T. Mudge, D. Blaauw, D. Sylvester. USPTO Number: 8,335,122. December 18, 2012. [pdf]
    • "Cache Memory with Power Saving State", T. Mudge, D. Roberts, T. Wenisch. USPTO Number: 8,285,936. October 9, 2012. [pdf]
    • "Crossbar Circuitry and Method of Operation of Such Crossbar Circuitry", S. Satpathy, D. Blaauw, T. Mudge, D. Sylvester, R. Dreslinski. (Japan) Patent Number 5074538. August 31, 2012.
    • "Random Number Generator", T. Mudge, D. Blaauw, C. Tokunaga. (Japan) Patent Number 4938612. August 14, 2013.
    • "Error Recovery Within Processing Stages of an Integrated Circuit", K. Flautner, T. Austin, D. Blaauw, T. Mudge. USPTO Number: 8,185,786. May 22, 2012. [pdf]
    • "Priority Arbitration Control Within Interconnect Circuitry", S. Satpathy, D. Blaauw, D. Sylvester, T. Mudge. Appllcation Number: 13/,438,920. April 4, 2012. [pdf]
    • "Storage of Data in Data Stores Having Some Faulty Storage Locations", T. Mudge, G. Dasika, D. Roberts. USPTO Number: 8,145,960, 8,230,277. March 27, 2012; July 24, 2012. [pdf] [pdf]
  • 2011
    • "Crossbar Circuitry for Applying an Adaptive Priority Scheme and Method of Operation of Such Crossbar Circuitry", S. Satpathy, T. Mudge, D. Sylvester, D. Blaauw. Application Number: 12/926,462. June 16, 2011. [pdf]
    • “Random Number Generator”, T. Mudge, D. Blaauw, C. Tokunaga.  United Kindgom Number: GB2442838. May 11, 2011.
    • “Cost Effective Razor Pipeline Recovery with Micro-Architectural Support,” T. Mudge, K. Flautner, D. Blaauw, T. Austin, D. Bull, S. Das.  (Japan) Patent Number 4722994. April 15, 2011. (Same title in China, United Kingdom) .
    • "Data Retention Latch Provision Within Integrated Circuits", T. Mudge. Patent Number: 168514 (Israel). February 1, 2011.
  • 2010
    • "Error Recovery Within Integrated Circuit," K. Flautner, T. Austin, D. Blaauw, T. Mudge, D. Bull. Application Number: 12/926,084. [pdf]
    • “Integrated Circuit with error Correction Mechanisms to Offset Narrow Tolerancing Razor Technology”, T. Mudge, K. Flautner, D. Blaauw, T. Austin, David Bull. USPTO Number: 7,701,240.  April 20, 2010. [pdf]
    • “Error Detection and recovery within Processing Stages of an Integrated Circuit”, K. Flautner, T. Austin, D. Blaauw, T. Mudge.  USPTO Number: 7,650,551. January 19, 2010. (Same title in Israel and the Republic of Korea). [pdf]
  • 2009
    • "Memory Control", D. Roberts, T. Mudge, T. Wenisch. Application Number: 12/588,592. October 20, 2009. [pdf]
    • “Data Processor Memory Circuit”, K. Flautner, N. Kim, S. Martin, D. Blaauw, T. Mudge. USPTO Number: 7,533,226. May 12, 2009. [pdf]
    • Performance level selection in a data processing system by combining a plurality of performance requests”, K. Flautner, T. Mudge.  USPTO Number: 7,512,820. March 31, 2009. [pdf]
    • “Using Shadow Latches As Low Leakage Retention Latches”, K. Flautner, D. Blaauw, T. Austin, T. Mudge.  China ZL200480007397. March 11, 2009.  (Same title in Japan).
  • 2008
    • “Systematic and random error detection and recovery within processing stages of an integrated circuit”, T. Austin, D. Blaauw, K. Flautner, T. Mudge. USPTO Number: 7,337,356. February 26, 2008. (Same title in Europe). [pdf]
    • “Performance counter for adding variable work increment value that is dependent upon clock frequency”, T. Mudge, K. Flautner, D. Flynn.  USPTO Number: 7,321,942.  January 22, 2008. [pdf]
  • 2007
    • "Data Retention Latch Provision Within Integrated Circuits", T. Mudge, T. Austin, D. Blaauw, K. Flautner. USPTO Number: 7,310,755. December 18, 2007. [pdf]
    • "Error Detection and Recovery Within Processing Stages of an Integrated Circuit", K. Flautner, T. Austin, D. Blaauw, T. Mudge. USPTO Number: 7,278,080. October 2, 2007. [pdf]
    • "Data Processor Memory Circuit", K. Flautner, T. N. Mudge. USPTO Number: 7,260,694. August 21, 2007. [pdf]
    • "Performance Level Setting of a Data Processing System", K. Flautner, T. N. Mudge. USPTO Number: 7,194,385. March 20, 2007. [pdf]
    • "Systematic and Random Error Detection and Recovery Within Processing Stages of an Integrated Circuit", T. N. Mudge, T. M. Austin, D. T. Blaauw, K. Flautner. USPTO Number: 7,162,661. January 9, 2007. [pdf]
  • 2006
    • "Performance Level Selection in a Data Processing System Using a Plurality of Performance Request Calculating Algorithms", K. Flautner, T. N. Mudge. USPTO Number: 7,131,015. October 31, 2006. [pdf]
    • "Memory System Having Fast and Slow Data Reading Mechanisms", T. M. Austin, D. T. Blaauw, T. N. Mudge, D. M. Sylvester, K. Flautner. USPTO Number: 7,072,229. July 4, 2006. [pdf]
    • "Data Processor Memory Circuit", K. Flautner, D. T. Blaauw, T. N. Mudge, N. S. Kim, S. M. Martin. USPTO Number: 7,055,007. May 30, 2006. [pdf]
  • 2005
    • "Memory System Having Fast and Slow Data Reading Mechanisms", T. N. Mudge, T. M. Austin, D. T. Blaauw, D. M. Sylvester, K. Flautner. USPTO Number: 6,944,067. September 13, 2005. [pdf]
  • 1985
    • "Design Rule Checking Using Serial Neighborhood Processors", R. M. Lougheed, T. N. Mudge. USPTO Number: 4,510,616. April 9, 1985. [pdf]
  • 1984
    • "Design Rule Checking Using Serial Neighborhood Processors", R. M. Lougheed, T. N. Mudge. USPTO Number: 4,441,207. April 3, 1984. [copy of M.S. thesis] [pdf]