EECS 373 Lab 3: Introduction to Memory Mapped IO

Copyright © 2010-2011, Matt Smith, Thomas Schmid, Ye-Sheng Kuo, Lohit Yerva, and Prabal Dutta.

Schedule

See posted lab schedule for due dates, in-lab, and post-lab due dates.

Objectives

In Lab 2 we provided you with the "hardware" to read and write the LEDs and switches from software. We used dedicated hardware that Actel provides for this purpose. In this lab we will discover how to create our own hardware in the FPGA for this purpose. You will provide the memory locations (registers), data path and control to access registers connected to the LEDs and switches.

Overview

Pre-Lab Assignment

There is no Pre-Lab assignment for this lab. Read over the In-Lab assignment and get started.

In-Lab Assignment

The In-Lab assignment is a tutorial that shows you how to interface to the LEDs and push button switches as memory mapped IO (MMIO), that is we will read and write the LEDs and switches as though they are memory locations. The functional components of the MMIO interface are organized a bit like this.

We will implement the register control, registers, connections to the LEDS and switches in Verilog. We will use some prepackaged "core" from Actel and the Libero Smart Design environment to make the bus connections.

1 Creating the IO Registers

We will create registers in the FPGA that will act as the storage element for the memory mapped IO interface. Lets start with LED register. The register will be 8 bit, read/write with the output ported directly to the LEDS. A reset is provided that sets the register to logical 0. We have provided you with the following example code to do this. Create a new project, create a new Verilog file as you did in lab one and copy the the following contents into it. Save the file. Do a HDL check to be sure all is well.

// ledreg.v

module ledreg( clk, nreset, wr_en, rd_en, data_in, data_out, led_port); 
 
//Inputs Declarations 
input clk; //Clock
input nreset; //active low reset 
input wr_en; //Write Enable 
input rd_en; //Read Enable 
input [7:0] data_in; //Data Input 
 
//output Declarations 
output [7:0] data_out; //Data Output 
output [7:0] led_port; //path to led connection
 
//reg Declarations 
reg [7:0] ledioreg; //the io register 
reg [7:0] data_out; //Data Output
wire [7:0] led_port;

//map led register to leds
assign led_port = ledioreg;

//read led register
always @(posedge clk, negedge nreset) 
 begin : READ_GEN 
 if(nreset == 1'b0)
 begin
 data_out <= 8'h00;
 end
 else if(rd_en)
 begin 
 data_out <= ledioreg; 
end end 

//write led register 
always @(posedge clk, negedge nreset) 
 begin : WRITE_GEN 
 if(nreset == 1'b0)
 begin
 ledioreg <= 8'h00;
 end
 else if(wr_en)
 begin 
 ledioreg <= data_in;
 end 
end 
endmodule

// swreg.v
module swreg( clk, nreset, rd_en, sw_port, data_out); 
 
//Inputs Declarations 
input clk; //Clock
input nreset; //active low reset 
input rd_en; //Read Enable 
input [1:0] sw_port; //path from switches
 
//output Declarations 
output [7:0] data_out;
 
//reg Declarations 
reg [7:0] data_out;
wire [1:0] sw_port;

//read led register
always @(posedge clk, negedge nreset) 
begin : READ_GEN 
 if(nreset == 1'b0)
 begin
 data_out <= 8'h00;
 end
 else if(rd_en)
 begin 
 data_out[0] <= sw_port[0];
 data_out[1] <= sw_port[1];
 end 
end
endmodule

2 Creating and APB3 "wrapper"

The name wrapper is a bit of misnomer: it is really an interface. Specifically, it is the Verilog that provides the interface interface between your IO register and the APB3 bus. The wrapper provides a control and data path conections and control logic between the IO register and the Cortex M3 APB3 bus. The APB3 bus (advanced peripheral bus) is designed to interface with slow IO and has a simple protocol. Transfers fundamentally consists of two cycles: the setup phase and access phase. During the setup phase, the processor provides unique information that identifies the transaction such as read/write, device address, etc. During the access phase, the device either provides or excepts data from the processor. Additionally, the device provides a control signal during the access phase to the processor to extend the phase if more time is needed to latch or provide data. For more detail, you can see the reference at the end of the lab. For your convenience, the read/write transfer cycles with and without extended accesses are provide below. A description of the signals follows.

1. Consider the case of writing the LED register. Examining the verilog code we see that the register is written on the rising edge of clk and wr_en true. To generate wr_en signal, the device has to be selected (PSEL == 1), it has to be a write cycle (PWRITE == 1) and it should be an access phase (PENABLE == 1).
2. So we have wr_en = PSEL && PWRITE && PENABLE with the PCLK used as the register clock. The read register is similarly accessed except PWRITE == 0 and the processor requires that the data is available at the beginning of the access cycle so PENABLE is omitted.
3. So we have wr_en = PSEL && !PWRITE with the PCLK used as the register clock.
4. There is no need to extend the access cycle, so PREADY is set logical 1. There is no criteria for PSLVERR so it is driven logical 0.

// ledregwrp.v
module ledregwrp(
 PCLK,
 PENABLE,
 PSEL,
 PRESERN,
 PWRITE,
 PREADY,
 PSLVERR,
 PWDATA,
 PRDATA,
 LEDCON,
 TPS);

input PCLK,PENABLE, PSEL, PRESERN, PWRITE;
input [7:0] PWDATA;
output [7:0] PRDATA, LEDCON;
output PREADY, PSLVERR;
output [4:0] TPS;//test points

wire rd_enable;
wire wr_enable;

assign wr_enable = (PENABLE && PWRITE && PSEL);
assign rd_enable = (!PWRITE && PSEL); //Data is ready during first cycle to make it availble on the bus when PENABLE is asserted

ledreg ledreg_0 (.clk(PCLK), .nreset(PRESERN), .wr_en(wr_enable), 
 .rd_en(rd_enable), .data_in(PWDATA), .data_out(PRDATA), .led_port(LEDCON));
 
assign PREADY = 1'b1; 
assign PSLVERR = 1'b0;

assign TPS[0] = PCLK;
assign TPS[1] = PWRITE;
assign TPS[2] = PSEL;
assign TPS[3] = PENABLE;
assign TPS[4] = PREADY; 
 
endmodule

// swregwrp.v
module swregwrp(
 PCLK,
 PENABLE,
 PSEL,
 PRESERN,
 PWRITE,
 PREADY,
 PSLVERR,
 PWDATA,
 PRDATA,
 SWCON,
 TPS);

input PCLK,PENABLE, PSEL, PRESERN, PWRITE;
input [7:0] PWDATA;
input [1:0] SWCON;
output [7:0] PRDATA;
output PREADY, PSLVERR;
output [4:0] TPS;//test points

wire rd_enable;
wire wr_enable;

assign rd_enable = (!PWRITE && PSEL); //Data is ready during first cycle to make it availble on the bus when PENABLE is asserted

swreg swreg_0 (.clk(PCLK), .nreset(PRESERN),
.rd_en(rd_enable), .data_out(PRDATA), .sw_port(SWCON));
 
assign PREADY = 1'b1; 
assign PSLVERR = 1'b0;

assign TPS[0] = PCLK;
assign TPS[1] = PWRITE;
assign TPS[2] = PSEL;
assign TPS[3] = PENABLE;
assign TPS[4] = PREADY; 
 
endmodule

Double click on the MSS icon in the project flow window and provide a name to the MSS configure such as m. A view of the MSS system will open revealing all the available components and connections. All the components are enabled to begin. We will only need the Reset Management, Fabric Interface< Watch Dog and Clock Management Component. The components are enabled by selecting the check box in the lower right corner. Notice that some components like the Clock Management do not have the option to exclude since they are needed for any configuration. Turn off all the components we don't need and your canvas should look something like this.

3.2 Configure Clock Manager

This component provides clock sources for the various system components and custom FPGA hardware. We will use a clock that can be mapped to the FPGA hardware for the APB3 bus clock. Double click on the Clock Management icon. FAB_CLK (fabric clock) is the FPGA clock. Enable by clicking on the box. We are going to divide the clock down from the source clock (100 MHz) to 25 MHz. Do this by selecting the drop down menu just upstream from the FAB_CLK output and select divide by 4. The default source clock should be the RC oscillator (upper left). Also, you should notice the FAB_CLK added as an output port (upper right) from the MSS system to the FGPA fabric when you return to the MSS canvas. The connections are not shown between the components and MSS boundary. You can add them under the Canvas menu if you wish (show nets). The clock manager configuration should look something like this before closing.

3.3 Configure Reset Manager

The reset manager provides power up system reset to the various components and FPGA fabric. We need provide the power up reset to the FPGA fabric. Open the Reset Manager and select "Enable MSS to Fabric Reset". It should look like this and you should notice a reset output to the FPGA fabric on the MSS canvas.

3.4 Configure Fabric Interface

T

he Fabric Interface component is use configure bus ports to custom FPGA hardware. In this case we must configure a APB3 interface. Double click on the icon opening the fabric interface configuration. Notice that the MSS clock frequency and fabric clock frequency are inherited from the clock settings. We need a APB3 interface so select "AMBA APB3". The interface will act as a "Master" controlling the LED and switch registers so configure as MSS Master. The setting should look like this.

3.5 Generate MSS

Finally HDL has to be generated from the MSS for synthesis. Click the generate icon or select under the design menu. Make sure there are no errors indicated in the script below. The MSS generator will warn you that a root has not been set for the design hierarchy. You can ignore this for now. The final canvas should look something like this with the net view enabled (not necessary). Inspect the project explorer in the files tab and you will see Verilog files added for the MSS components.

4 Connecting the IO Register Wrappers to the APB3

4.2 Instantiate MSS Components in SmartDesign Canvas

We need to start by instantiating the MSS components we establishes earlier in the SmartDesign Canvas. Select IP mssio in the Design Explorer and drag it into the SmartDesign canvas. Or, select IP mssio, right click and choose instantiate in apb3_to_ledswreg. The MSS components we configured will be represented as a block with the ports we provided. The reset connection is automatically made since this is a fixed input. The block should look something like this.

4.3 Instantiate Register APB3 Wrappers in SmartDesign Canvas

4.4 Convert IO Register APB3 Wrapper Ports to APB3 Slave Interface

 Next we need to repackage the wrapper ports so that they interface a bit easier with standard APB3 signals. SmartDesign has a handy tool for this. Select the Bus Definitions tab (lower right) in the Catalog window (right). Select APB, AMBA, AMBA2, slave. Drag this onto one of the instantiation blocks of one of the wrappers. You will be prompted to associate the signals of the wrapper with standard APB3 signals. Many of these can be associated automatically by using the map by name feature (upper right) if we took care to use similar names when we created the wrapper ports. You will find most of these signals mapped except PSELx and PADDR. Use the signal window set PSELx to PSEL and the width window to set to 1 bit. We are not using PADDR so it can remain blank. The result should look like this.

4.5 Instantiate APB3 Core Interface

Under bus interfaces in the catalog window (left) select CoreAPB3 and drag onto the canvas. A configuration window will appear. Basically allows you to determine how many IO devices you wish to select and how much memory space you wish to allocate per device. Keep all the settings but reduce the slot number (devices) to just two. It should look like this.

4.6 Connect IO Register APB3 Wrappers to APB3 Core Interface

4.7 Connect Resets

Notice that the components are all located to one side of the canvas and the reset connection has to be routed over one of the components. SmartDesign has an auto component arrange feature to nicely distribute the components. Right click in the window and select auto arrange instances. Usually this works, but you might have to manually adjust too. Also use the auto fit feature after auto arranging. It is this middle icon.

4.8 Connect LEDs, Switch Ports and Test Points

Finally we need to connect the LEDs, Switches and Test Points to the appropriate FPGA pins. Since the test points are identical for both wrappers we need only connect one set. You can add FPGA ports to the canvas by right clicking just outside the canvas and selecting add port. However, when you have an existing port on the canvas there is a much easier way. Select the port you wish to provide connection to, right click and select promote to top level. This will create the connection automatically. After adding these connections and auto arranging instances the canvas should look like a bit like this.

4.9 Check Design and Generate HDL for Synthesis

5 Synthesize all Components

6 Assign FPGA Pins

7 Place and Route

8 Simulation

9 Program FPGA

10 Debug and Verify with SoftConsole

10.1 Create a SoftConsole Project and Debugger Session

10.2 Use GDB Commands to Verify IO Register Function

10.2.1 Write the Led  Register

When we setup the APB3 interface we discovered that register base address was 0x40050000.  Although the register is 8 bits, it can be treated like a 32 bit value with the low order byte effective. For example, 

        set *(int *) 0x40050000 = 0x55

Try writing different values and see if the LEDs correspond to your values.

10.2.2 Read the Switch  Register

The GDB command to read is examine or simply  "x". The format is:

When we setup the APB3 interface we discovered that register base address was 0x40050100.  Although the register is 8 bits, it can be treated like a 32 bit value with the low order byte effective. For example, 

        x 0x40050100

Try reading  different values and see if it corresponds to the switch values.  Remember the switches are active low.

There are many other options for the examine command. You can search the web for GDB quick references for more detail.t

10.3 Use GDB Commands to Observe the APB3 Bus Signals

USER IO 1 = PCLK

USER IO 2 = PWRITE

USER IO 3 = PSEL

USER IO 4 = PENABLEUSER

USER IO 5 = PREADY

Note, it may be necessary to power reset the kit to get the FAB clock and in this case the APB3 clock set. You can try the RESET button or it may be necessary to disconnect the USB power cable (nearest push button). This will disrupt the SoftConsole debug connection. You need to reload the configuration to recover the connection. Click on the following icon (upper left) in the debug window and reload the configuration

10.4 Write a Simple Program

.equ STACK_TOP, 0x20000800

.equ LEDIO_REG_BASE, 0x40050000
.equ SWIO_REG_BASE, 0x40050100

	.section .int_vector,"a",%progbits @ First linker code section
	.global _start @ Linker entry point
_start:
	.word STACK_TOP, main
	@ End of int_vector section

	@ Standard text section
	.text
	.syntax unified
	.thumb

	.type main, %function
main:
	@ Load led register base address
	movw r0, #:lower16:LEDIO_REG_BASE
	movt r0, #:upper16:LEDIO_REG_BASE
	@ Load switch register base address
	movw r1, #:lower16:SWIO_REG_BASE
	movt r1, #:upper16:SWIO_REG_BASE

loop:
	@ Read switch register
	ldr r3, [r1, #0]
	@ Write switch values to led register
	str r3, [r0, #0]
b loop
.end

Lab 3 Debugging Pit Falls

Post-Lab Assignment

The Hardware Assignment

// timer.v
module timer (clock, compare, equal, soft_reset);
input clock;
input [15:0]compare;
input soft_reset;
output equal;

reg [15:0] counter, ncounter;
reg equal;
wire divided_clock;
reg [17:0] divide;
reg [17:0] nextDivide;

wire [15:0]nextcounter = counter + 16'd1;

//The following code divides the fabric clock to approximately 100Hz

always @*
  begin
      nextDivide = divide + 16'd1;
  end

always @(posedge clock)
begin
    divide <= nextDivide;
end

assign divided_clock = divide[17];

// This code provides the counter, comparator and software reset functions
of the timer
always @*
begin
    if (soft_reset == 1)
	begin
		equal = 0;
	end
	else if (counter == compare)
	begin
		equal = 1;
	end
	else
	begin
		ncounter = counter + 1;
	end
end
	
always @(posedge divided_clock or posedge soft_reset)
if (soft_reset)
begin
    counter <= 0;
end
else
begin
	counter <= ncounter;
end
	
endmodule

Interfacing to the APB3

The timer can be instantiated and added to the top level canvas as a module as you did above. The timers ports: compare, equal and soft_reset will have to be connected to the APB3 bus via a register interface not unlike the register interfaces provided for the switches and leds.  In this case; however, we will provide 3 APB3 interfaced registers to support the timer: a 16 bit write only compare register, a 1 bit read only equal register and a 1 bit write only soft_reset register.  Note, you need to keep the switch and led registers for a software application. The MMIO including the timer should look a bit like this.

Soft_reset Register Verilog

The soft reset is a software generated reset to clear the timer counter and reset the timer equal status. The Verilog for a Soft_reset register and Soft_reset register wrapper follows. You will have to follow the procedure above to instantiate the module in the top level canvas. Be sure and connect the Soft_reset signal to the Timer module. You will have to add another slave port the APB3 bus. Click on the buss-->properties and add another slot. 

Soft Reset Register

// softresetreg.v

module softresetreg( clk, nreset, wr_en, rd_en, data_in, softreset); 
 
//Inputs Declarations 
input clk; //Clock
input nreset; //active low reset 
input wr_en; //Write Enable 
input rd_en; //Read Enable 
input [7:0] data_in; //Data Input 
 
//output Declarations 
output softreset; //path to softreset
 
//reg Declarations 
reg [7:0] softresetreg; //the io register 
wire softreset;

//map led register to leds
assign softreset = softresetreg[0];

//write softreset register 
always @(posedge clk, negedge nreset) 
 begin : WRITE_GEN 
 if(nreset == 1'b0)
 begin
 softresetreg <= 8'h00;
 end
 else if(wr_en)
 begin 
 softresetreg[0] <= data_in[0];
 end 
end 
endmodule

// softresetwrp.v
module softresetwrp(
 PCLK,
 PENABLE,
 PSEL,
 PRESERN,
 PWRITE,
 PREADY,
 PSLVERR,
 PWDATA,
 PRDATA,
 SOFTRESET,
 TPS);

input PCLK,PENABLE, PSEL, PRESERN, PWRITE;
input [7:0] PWDATA;
output [7:0] PRDATA
output SOFTRESET;
output PREADY, PSLVERR;
output [4:0] TPS;//test points

wire rd_enable;
wire wr_enable;

assign wr_enable = (PENABLE && PWRITE && PSEL);
assign rd_enable = (!PWRITE && PSEL); //Data is ready during first cycle to make it availble on the bus when PENABLE is asserted

softresetreg softresetreg_0 (.clk(PCLK), .nreset(PRESERN), .wr_en(wr_enable), 
 .rd_en(rd_enable), .data_in(PWDATA), .softreset(SOFTRESET));
 
assign PREADY = 1'b1; 
assign PSLVERR = 1'b0;

//for the post lab you are asked to monitor the PSELs for all the MMIO with the logic anlayzer. Choose a test point that you wish
// to port the PSEL on for each MMIO wrapper
//assign TPS[0] = PCLK;
//assign TPS[1] = PWRITE;
assign TPS[2] = PSEL;
//assign TPS[3] = PENABLE;
//assign TPS[4] = PREADY; 
 
endmodule

Timer Counter and Equal Status Register Verilog

Complete the Verilog for the compare and equal registers, add to your top level canvas. Hint. Use the LED register and LED register wrapper Verilog as a model to build the compare register and wrapper Verilog. Similarly, look at the switch register and switch register wrapper Verilog as a model to build the enable register and wrapper Verilog. 

The Software Assignment

1. Blink the LEDs in sequence from top to bottom (led 0 to led 7) at a user determined rate.
2. The starting rate should be 1Hz
3. The rate should increment by 1 Hz when SW1 is pressed and released.
4. The rate should decrement by 1 Hz when SW2 is pressed and released.
5. The rates should remain between 1 and 10 Hz. 

1. You can get the addresses for your timer registers by selecting the APB3 bus in the top level canvas, right clicking and selecting memory map.
2. Consider the following process to develop your software:
1. Start by blinking one LED at 1 Hz using the timer.
2. Add the switch control to increase the or decrease the blink rate.
3. Modify to blink the LEDs in sequence.
3. To get the switches to increase or decrease the rate in steps of 1Hz, you will have to detect the change in the switch value. Just detecting the switch level is not sufficient. Just level detection will result in the software detecting that the switch is pressed for several loops decreasing or increasing the rate very quickly to one of the boundaries. To detect a transition, you will have to keep the previous value of the switch in a memory location or spare register and detect if the switch has changed or not.

1. Which APB3 bus signal uniquely identifies the bus transaction for a particular device? In general terms, what bus signals are decoded to generate this signal?
2. How many wait cycles do your MMIO registers need if any?
3. The timer verilog divides the fabric clock to approximately 100Hz by using a simple binary counter. What is the actual value in Hz?
4. In the timer Verilog code, what signal edge is the timer counter set to zero on? Why do you suppose this is necessary?

Extra Credit