EECS 373 Lab 3: Memory Mapped IO - Question Sheet

Student names:

Student unique names:


Post-Lab Assignments


Demonstrate the operation of your timer application to a 373 lab instructor.  Lab instructor signature and date.



Q1 Which APB bus signal uniquely identifies the bus transaction for a particular device? In general terms, what bus signals are decoded to generate this signal?

Q2 How many wait cycles do your MMIO registers need if any?

Q3 The timer verilog divides the fabric clock to approximately 100Hz by using a simple binary counter. What is the actual value in Hz?

Q4 In the timer Verilog code, what signal edge is the timer counter set to zero on? Why do you suppose this is necessary?

Code Submissions

1) Submit a hard copy of your timer applicatoin assembly code.


Provide a  print of the logic analyzer view showing all the PSELs. Identify each PSEL labeling with the register name.