reconfigurable architectures

CoSPARSE: A Software and Hardware Reconfigurable SpMV Framework for Graph Analytics

We build a framework for hardware-software synergistic reconfiguration that enables faster acceleration of graph analytics algorithm on a reconfigurable architecture.

Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm

We present Versa, an energy-efficient processor with 36 systolic ARM Cortex-M4F cores and a runtime-reconfigurable memory hierarchy.

Transmuter: Bridging the Efficiency Gap using Memory and Dataflow Reconfiguration

We propose a reconfigurable accelerator for parallel workloads called Transmuter with a software stack called TransPy.