Publications

Subhankar Pal, Aporva Amarnath, Siying Feng, Michael O'Boyle, Ronald Dreslinski, Christophe Dubach (2021). SparseAdapt: Runtime Control for Sparse Linear Algebra on a Reconfigurable Accelerator. In MICRO.

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Siying Feng, Jiawen Sun, Subhankar Pal, Xin He, Kuba Kaszyk, Dong-hyeon Park, John Magnus Morton, Trevor Mudge, Murray Cole, Michael O'Boyle, Chaitali Chakrabarti, Ronald Dreslinski (2021). CoSPARSE: A Software and Hardware Reconfigurable SpMV Framework for Graph Analytics. In DAC.

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Aporva Amarnath, Subhankar Pal, Hiwot Tadese Kassa, Augusto Vega, Alper Buyuktosunoglu, Hubertus Franke, John-David Wellman, Ronald Dreslinski, Pradip Bose (2021). Heterogeneity-Aware Scheduling on SoCs for Autonomous Vehicles . CAL.

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Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor Mudge, Chaitali Chakrabarti, David Blaauw, Ronald Dreslinski, Hun-Seok Kim (2021). Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm. In VLSI.

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Subhankar Pal, Swagath Venkataramani, Viji Srinivasan, Kailash Gopalakrishnan (2021). Efficient Management of Scratch-Pad Memories in Deep Learning Accelerators. In ISPASS.

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Subhankar Pal, Kuba Kaszyk, Siying Feng, Björn Franke, Murray Cole, Michael O'Boyle, Trevor Mudge, Ronald Dreslinski (2020). HetSim: Simulating Large-Scale Heterogeneous Systems using a Trace-driven, Synchronization and Dependency-Aware Framework. In IISWC.

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Subhankar Pal, Siying Feng, Dong-hyeon Park, Sung Kim, Aporva Amarnath, Chi-Sheng Yang, Xin He, Jonathan Beaumont, Kyle May, Yan Xiong, Kuba Kaszyk, John Magnus Morton, Jiawen Sun, Michael O'Boyle, Murray Cole, Chaitali Chakrabarti, David Blaauw, Hun-Seok Kim, Trevor Mudge, Ronald Dreslinski (2020). Transmuter: Bridging the Efficiency Gap using Memory and Dataflow Reconfiguration. In PACT.

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Yan Xiong, Jian Zhou, Subhankar Pal, David Blaauw, Hun-Seok Kim, Trevor Mudge, Ronald Dreslinski, Chaitali Chakrabarti (2020). Accelerating Deep Neural Network Computation on a Low Power Reconfigurable Architecture. In ISCAS.

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Javad Bagherzadeh, Aporva Amarnath, Jielun Tan, Subhankar Pal, Ronald Dreslinski (2020). R2D3: A Reliability Engine for 3D Parallel Systems. In DAC.

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Xin He, Subhankar Pal, Aporva Amarnath, Siying Feng, Dong-hyeon Park, Austin Rovinski, Haojie Ye, Yuhan Chen, Ronald Dreslinski, Trevor Mudge (2020). Sparse-TPU: Adapting Systolic Arrays for Sparse Matrices. In ICS.

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Anuraag Soorishetty, Jian Zhou, Subhankar Pal, David Blaauw, Hun-Seok Kim, Trevor Mudge, Ronald Dreslinski, Chaitali Chakrabarti (2020). Accelerating Linear Algebra Kernels on a Massively Parallel Reconfigurable Architecture. In ICASSP.

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Dong-hyeon Park, Subhankar Pal, Siying Feng, Paul Gao, Jielun Tan, Austin Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Timothy Wesley, Jonathan Beaumont, Kuan-Yu Chen, Chaitali Chakrabarti, Michael Taylor, Trevor Mudge, David Blaauw, Hun-Seok Kim, Ronald Dreslinski (2020). A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator. JSSC.

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Subhankar Pal, Dong-hyeon Park, Siying Feng, Paul Gao, Jielun Tan, Austin Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Timothy Wesley, Jonathan Beaumont, Kuan-Yu Chen, Chaitali Chakrabarti, Michael Taylor, Trevor Mudge, David Blaauw, Hun-Seok Kim, Ronald Dreslinski (2019). A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm. In VLSI.

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Siying Feng, Subhankar Pal, Yichen Yang, Ronald Dreslinski (2019). Parallelism Analysis of Prominent Desktop Applications: An 18- Year Perspective. In ISPASS.

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Subhankar Pal, Jonathan Beaumont, Dong-hyeon Park, Aporva Amarnath, Siying Feng, Chaitali Chakrabarti, Hun-Seok Kim, David Blaauw, Trevor Mudge, Ronald Dreslinski (2018). OuterSPACE: An Outer Product based Sparse Matrix Multiplication Accelerator. In HPCA.

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Aporva Amarnath, Subhankar Pal, Siying Feng, Tutu Ajayi, Austin Rovinski, Ronald Dreslinski (2017). A Carbon Nanotube Transistor based RISC-V Processor using Pass Transistor Logic. In ISLPED.

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Subhankar Pal, Chetan Vudadha, Sai Phaneendra Parlapalli, Sreehari Veeramachaneni, Srinivas Mandalika (2014). A New Design of an N-Bit Reversible Arithmetic Logic Unit. In ISED.

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