Publications

(2021). Efficient Management of Scratch-Pad Memories in Deep Learning Accelerators. In ISPASS.

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(2020). HetSim: Simulating Large-Scale Heterogeneous Systems using a Trace-driven, Synchronization and Dependency-Aware Framework. In IISWC.

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(2020). Transmuter: Bridging the Efficiency Gap using Memory and Dataflow Reconfiguration. In PACT.

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(2020). Accelerating Deep Neural Network Computation on a Low Power Reconfigurable Architecture. In ISCAS.

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(2020). R2D3: A Reliability Engine for 3D Parallel Systems. In DAC.

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(2020). Sparse-TPU: Adapting Systolic Arrays for Sparse Matrices. In ICS.

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(2020). Accelerating Linear Algebra Kernels on a Massively Parallel Reconfigurable Architecture. In ICASSP.

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(2020). A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator. JSSC.

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(2019). A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm. In VLSI.

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(2018). OuterSPACE: An Outer Product based Sparse Matrix Multiplication Accelerator. In HPCA.

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(2017). A Carbon Nanotube Transistor based RISC-V Processor using Pass Transistor Logic. In ISLPED.

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(2014). A New Design of an N-Bit Reversible Arithmetic Logic Unit. In ISED.

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