I am looking for full-time positions in Industry Research and Post-Doctoral opportunities starting Fall 2021. Please reach out to me if you are hiring.

About Me

I am a final year PhD student advised by Prof. Ronald G. Dreslinski at the University of Michigan, Ann Arbor, where I received my MS degree in 2018. I currently work on researching reconfigurable hardware that deliver high efficiencies while retaining CPU-like programmability. I received a BE degree in Electrical and Electronics Engineering from BITS-Pilani, India, following which I was with NVIDIA, Bangalore where I worked on pre-silicon verification and bring-up of multiple GPUs. My current research interests are in the area of hardware accelerators, hardware-software co-design, memory systems and emerging technologies.

My research attempts to realize general-purpose acceleration and bridge the historic gap between programmability and efficiency with a reconfigurable, hardware-software co-designed solution. The proposed architecture leverages fast reconfiguration to achieve orders of magnitude better efficiency than general-purpose processors on irregular applications, while delivering at least GPU-like performance on regular workloads such as matrix multiplication. This is achieved by reconfiguring the hardware and tailoring it to the nature of the workload, while using intelligent performance-counter based inference to determine the best configuration.


  • Computer Architecture
  • Accelerator Design
  • Hardware-Software Co-Design


  • PhD in Computer Science and Engineering, 2021 (expected)

    University of Michigan

  • MS in Computer Science and Engineering, 2018

    University of Michigan

  • BE in Electrical and Electronics Engineering, 2014

    Birla Institute of Technology and Science



Research Intern

IBM Research

May 2019 – Aug 2019 Yorktown Heights, NY, USA

Worked in the System Software research group under Dr. Viji Srinivasan. Responsibilities included:

  • Built a framework for scratchpad management in DL accelerators
  • Explored algorithms for selective quantization of mixed-precision DNNs
  • Enhanced the DeepTools compiler runtime for error detection and handling

Research Co-Op Engineer

AMD Research

May 2017 – Sep 2017 Boxborough, MA, USA

Worked at AMD Boston Design Center under Dr. John Kalamatianos. Responsibilities included:

  • Worked on the DoE PathForward project to accelerate exascale workloads
  • Devised a 2-point solution to improve the performance of instruction-fetch

Full-Chip Verification/Bring-Up Engineer


Jul 2014 – Jul 2016 Bengaluru, KA, India

Worked at the Bangalore Design Center. Responsibilities included:

  • RTL full-chip testing and verification of next-gen GPUs
  • Silicon bring-up and testing of GPUs and PCI-Express interface debug

Bring-Up Intern


Jan 2014 – Jun 2014 Bengaluru, KA, India

Worked at the Bangalore Design Center. Responsibilities included:

  • Developed GUI tools to support post-silicon validation and bring-up
  • Debug support PCI-Express interface for Tegra SoC on FPGA