Subhankar Pal

I am a second-year PhD student at the University of Michigan, where I work on the architecture and design of hardware accelerators for specialized applications in the Circuits and Architecture Design Research (CADRe) group within the Computer Science and Engineering Department.

I am advised by Prof. Ronald Dreslinski Jr. I've done internships at NVIDIA and AMD Research in the past and I've worked full-time at NVIDIA for two years before I joined graduate school. I did my Bachelor's in Electrical Engineering at BITS Pilani, Hyderabad Campus, India.

Email  /  CV  /  Google Scholar  /  LinkedIn

Research

I'm interested in developing novel hardware for specialized applications, such as graph processing, scientific computing and virtual reality. I have a broad experience in various layers of the computing stack, including operating systems, compilers, computer architecture, VLSI design, analog electronics and electronic devices.

Much of my current research is about creating reconfigurable hardware that balances programmability and specialization.

OuterSPACE: An Outer Product based Sparse Matrix Multiplication Accelerator
Subhankar Pal, Jonathan Beaumont, Dong-hyeon Park, Aporva Amarnath, Siying Feng, Chaitali Chakrabarti, Hun-Seok Kim, David Blaauw, Trevor Mudge, Ronald Dreslinski
International Symposium on High Performance Computer Architecture (HPCA), 2018
Paper / Slides / BibTeX

We architected a novel hardware-software codesigned accelerator for high-performance, energy efficient sparse matrix multiplication targeting graph analytics and scientific computation.

A Carbon Nanotube Transistor based RISC-V Processor using Pass Transistor Logic
Aporva Amarnath, Siying Feng, Subhankar Pal, Tutu Ajayi, Austin Rovinski, Ronald Dreslinski
International Symposium on Low Power Electronics and Design (ISLPED), 2017
Paper / Slides / BibTeX

We explored various architectural design choices using CNTFET-based pass transistor logic and create an energy-efficient RISC-V processor using PTL for critical path components, demonstrating a win in terms of energy-delay product over traditional Silicon-CMOS and Silicion Pass Transistor Logic.

A New Design of an n-bit Reversible Arithmetic Logic Unit
Subhankar Pal, Chetan Kumar Vudadha, P. Sai Phaneendra, V. Sreehari, Srinivas Mandalika
International Symposium on Electronic system Design (ISED), 2014
Paper / Poster / BibTeX

We designed a low-cost quantum ripple-carry adder and enhance that into an ALU using a combination of the NCV and NCV-|v1> quantum gate libraries, which compromises delay in order to improve cost in terms of the number of quantum gates.

Industry
prl

Advanced Micro Devices (AMD), Inc. Research
May 2017 - Sep 2017

I worked as a summer co-op at AMD's Boston Design Center with Dr. John Kalamatianos on the Path-Forward Project for power-efficient acceleration of exascale workloads on CPUs. I focused on improving the performance and energy efficiency of the Branch Target Buffer.

prl

NVIDIA Corporation
Jul 2014 - Jul 2016

My work rotated between functional verification of next-generation GPUs in the full-chip environment and bringing up the silicon after it comes back from the fab. I also independently developed and maintained GUI debug utilities for debugging the GPU.



Course Projects
prl

A MIPS R10K-based Superscalar Out-of-Order Processor
Subhankar Pal, Kush Goliya, Harsha Valsaraju, Sean McLaughlin, Sep 2016 - Dec 2016

We implemented a MIPS R10K-style, 2-way superscalar, 6-stage, out-of-order processor based on the Alpha ISA using SystemVerilog.

prl

Automatic Identification of Colored Bacteria in Agar
Subhankar Pal, Shivani Gupta, Padmavathi Yenmandra, Suman Kapur, Aug 2013 - Dec 2013

I worked towards the development of an Android app to detect colored bacterial colonies in agar through statistical image processing techniques. This was to test the effect of antibiotics on bacteria causing UTI in humans.



Teaching/Mentorship
570

EECS 570: Parallel Computer Architecture - Winter 2018 (GSI)
Jan 2018 - Apr 2018

I am the Graduate Student Instructor (GSI) for EECS 570, assisting Prof. Satish Narayanasamy. My responsibilities include formulating exam/assignment/project materials, assisting students with a semester-long research project, delivering a few of the lectures, maintaining course/Canvas webpage and conducting regular office hours.

prl

Mentorship in ASIC Verification, NVIDIA Corporation
Feb 2014 - Jul 2014

I mentored Anand Thati, an intern in the GPU ASIC Bring-Up team in February 2016. My responsibilities included introducing the Synopsys Verdi tool and using it for functional debug of the GPU, assisting with Python/Tkinter coding and Perl/Shell scripting.


Last updated: Mar 13, 2018 | website template credits