About Me

Hi! I am a fifth-year PhD student in the Circuits and Architecture Design Research (CADRe) group, advised by Prof. Ronald Dreslinski Jr.

Much of my current research is about creating reconfigurable hardware that balances programmability and specialization. I have a broad experience in various layers of the computing stack, including operating systems, compilers, computer architecture and VLSI design.

Interests

  • Computer Architecture
  • Accelerator Design
  • Hardware-Software Co-Design

Education

  • PhD in Computer Science and Engineering, 2021 (expected)

    University of Michigan

  • MS in Computer Science and Engineering, 2018

    University of Michigan

  • BE in Electrical and Electronics Engineering, 2014

    Birla Institute of Technology and Science

Recent Publications

Xin He, Subhankar Pal, Aporva Amarnath, Siying Feng, Dong-hyeon Park, Austin Rovinski, Haojie Ye, Yuhan Chen, Ronald Dreslinski, Trevor Mudge (2020). Sparse-TPU: Adapting Systolic Arrays for Sparse Matrices. In ICS.

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Javad Bagherzadeh, Aporva Amarnath, Jielun Tan, Subhankar Pal, Ronald Dreslinski (2020). R2D3: A Reliability Engine for 3D Parallel Systems. In DAC.

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Dong-hyeon Park, Subhankar Pal, Siying Feng, Paul Gao, Jielun Tan, Austin Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Timothy Wesley, Jonathan Beaumont, Kuan-Yu Chen, Chaitali Chakrabarti, Michael Taylor, Trevor Mudge, David Blaauw, Hun-Seok Kim, Ronald Dreslinski (2020). A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator. JSSC.

PDF DOI

Subhankar Pal, Dong-hyeon Park, Siying Feng, Paul Gao, Jielun Tan, Austin Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Timothy Wesley, Jonathan Beaumont, Kuan-Yu Chen, Chaitali Chakrabarti, Michael Taylor, Trevor Mudge, David Blaauw, Hun-Seok Kim, Ronald Dreslinski (2019). A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm. In VLSI.

PDF Slides DOI

Siying Feng, Subhankar Pal, Yichen Yang, Ronald Dreslinski (2019). Parallelism Analysis of Prominent Desktop Applications: An 18- Year Perspective. In ISPASS.

PDF Code Slides DOI

See all publications

Experience

 
 
 
 
 

Research Intern

IBM Research

May 2019 – Aug 2019 Yorktown Heights, NY, USA

Worked in the System Software research group under Dr. Viji Srinivasan. Responsibilities included:

  • Built a framework for scratchpad management in DL accelerators
  • Explored algorithms for selective quantization of mixed-precision DNNs
  • Enhanced the DeepTools compiler runtime for error detection and handling
 
 
 
 
 

Research Co-Op Engineer

AMD Research

May 2017 – Sep 2017 Boxborough, MA, USA

Worked at AMD Boston Design Center under Dr. John Kalamatianos. Responsibilities included:

  • Worked on the DoE PathForward project to accelerate exascale workloads
  • Devised a 2-point solution to improve the performance of instruction-fetch
 
 
 
 
 

Full-Chip Verification/Bring-Up Engineer

NVIDIA

Jul 2014 – Jul 2016 Bengaluru, KA, India

Worked at the Bangalore Design Center. Responsibilities included:

  • RTL full-chip testing and verification of next-gen GPUs
  • Silicon bring-up and testing of GPUs and PCI-Express interface debug
 
 
 
 
 

Bring-Up Intern

NVIDIA

Jan 2014 – Jun 2014 Bengaluru, KA, India

Worked at the Bangalore Design Center. Responsibilities included:

  • Developed GUI tools to support post-silicon validation and bring-up
  • Debug support PCI-Express interface for Tegra SoC on FPGA

Contact