About Me

I a recently graduated PhD advised by Prof. Ronald G. Dreslinski at the University of Michigan, Ann Arbor, where I received my MS degree in 2018. I currently work on researching reconfigurable hardware that deliver high efficiencies while retaining CPU-like programmability. I received a BE degree in Electrical and Electronics Engineering from BITS-Pilani, India, following which I was with NVIDIA, Bangalore where I worked on pre-silicon verification and bring-up of multiple GPUs. My current research interests are in the area of reconfigurable architectures, hardware-software co-design, memory systems and emerging technologies.

Interests

  • Computer Architecture
  • Hardware-Software Co-Design

Education

  • PhD in Computer Science and Engineering, 2021

    University of Michigan

  • MS in Computer Science and Engineering, 2018

    University of Michigan

  • BE in Electrical and Electronics Engineering, 2014

    Birla Institute of Technology and Science - Pilani

Featured Publications

SparseAdapt: Runtime Control for Sparse Linear Algebra on a Reconfigurable Accelerator

We propose a dynamic adaptation framework for power and energy-efficiency optimization of CGRAs.
Subhankar Pal, Aporva Amarnath, Siying Feng, Michael O'Boyle, Ronald Dreslinski, Christophe Dubach
PDF

Efficient Management of Scratch-Pad Memories in Deep Learning Accelerators

We propose a compiler extension to efficiently manage the scratch-pad memories in modern deep learning accelerators.
Subhankar Pal, Swagath Venkataramani, Viji Srinivasan, Kailash Gopalakrishnan
PDF Slides DOI

HetSim: Simulating Large-Scale Heterogeneous Systems using a Trace-driven, Synchronization and Dependency-Aware Framework

We propose a solution to fast simulation called HetSim, a trace-driven, synchronization and dependency-aware framework for fast and accurate pre-silicon performance and power estimations for heterogeneous systems with up to thousands of cores.
Subhankar Pal, Kuba Kaszyk, Siying Feng, Björn Franke, Murray Cole, Michael O'Boyle, Trevor Mudge, Ronald Dreslinski
PDF Code Slides DOI

Transmuter: Bridging the Efficiency Gap using Memory and Dataflow Reconfiguration

We propose a reconfigurable accelerator for parallel workloads called Transmuter with a software stack called TransPy.
Subhankar Pal, Siying Feng, Dong-hyeon Park, Sung Kim, Aporva Amarnath, Chi-Sheng Yang, Xin He, Jonathan Beaumont, Kyle May, Yan Xiong, Kuba Kaszyk, John Magnus Morton, Jiawen Sun, Michael O'Boyle, Murray Cole, Chaitali Chakrabarti, David Blaauw, Hun-Seok Kim, Trevor Mudge, Ronald Dreslinski
PDF Slides DOI

A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm

We prototype a Sparse Matrix-Matrix Multiplication accelerator with 48 heterogeneous cores and a reconfigurable memory hierarchy in 40 nm CMOS that offers significant energy- and bandwidth-efficiency improvements over state-of-the-art CPUs and GPUs.
Subhankar Pal, Dong-hyeon Park, Siying Feng, Paul Gao, Jielun Tan, Austin Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Timothy Wesley, Jonathan Beaumont, Kuan-Yu Chen, Chaitali Chakrabarti, Michael Taylor, Trevor Mudge, David Blaauw, Hun-Seok Kim, Ronald Dreslinski
PDF Slides DOI

OuterSPACE: An Outer Product based Sparse Matrix Multiplication Accelerator

We architect a novel hardware-software codesigned accelerator for high-performance, energy efficient sparse matrix multiplication targeting graph analytics and scientific computation.
Subhankar Pal, Jonathan Beaumont, Dong-hyeon Park, Aporva Amarnath, Siying Feng, Chaitali Chakrabarti, Hun-Seok Kim, David Blaauw, Trevor Mudge, Ronald Dreslinski
PDF Slides DOI
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Experience

 
 
 
 
 

Research Intern

IBM Research

May 2019 – Aug 2019 Yorktown Heights, NY, USA

Worked in the System Software research group under Dr. Viji Srinivasan. Responsibilities included:

  • Built a framework for scratchpad management in DL accelerators
  • Explored algorithms for selective quantization of mixed-precision DNNs
  • Enhanced the DeepTools compiler runtime for error detection and handling
 
 
 
 
 

Research Co-Op Engineer

AMD Research

May 2017 – Sep 2017 Boxborough, MA, USA

Worked at AMD Boston Design Center under Dr. John Kalamatianos. Responsibilities included:

  • Worked on the DoE PathForward project to accelerate exascale workloads
  • Devised a 2-point solution to improve the performance of instruction-fetch
 
 
 
 
 

Full-Chip Verification/Bring-Up Engineer

NVIDIA

Jul 2014 – Jul 2016 Bengaluru, KA, India

Worked at the Bangalore Design Center. Responsibilities included:

  • RTL full-chip testing and verification of next-gen GPUs
  • Silicon bring-up and testing of GPUs and PCI-Express interface debug
 
 
 
 
 

Bring-Up Intern

NVIDIA

Jan 2014 – Jun 2014 Bengaluru, KA, India

Worked at the Bangalore Design Center. Responsibilities included:

  • Developed GUI tools to support post-silicon validation and bring-up
  • Debug support PCI-Express interface for Tegra SoC on FPGA

Contact