#Build: Synplify Pro E-2010.09A-1, Build 006R, Oct 6 2010 #install: C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1 #OS: Windows XP 5.1 #Hostname: EECS373-07 #Implementation: synthesis #Tue Sep 27 13:55:17 2011 $ Start of Compile #Tue Sep 27 13:55:17 2011 Synopsys Verilog Compiler, version comp520rcp1, Build 028R, built Sep 23 2010 @N: : | Running in 32-bit mode Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved @I::"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\smartfusion.v" @I::"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\vlog\hypermods.v" @I::"C:\Documents and Settings\373a\Desktop\lab4fpga\hdl\ReadSW_WriteLED.v" @I::"C:\Documents and Settings\373a\Desktop\lab4fpga\hdl\ReadSW_WriteLED_wrp.v" Verilog syntax check successful! Compiler output is up to date. No re-compile necessary Selecting top level module ReadSW_WriteLED_wrp @N:CG364 : ReadSW_WriteLED.v(52) | Synthesizing module Decoder3to8 @N:CG364 : ReadSW_WriteLED.v(3) | Synthesizing module ReadSW_WriteLED @N:CG364 : ReadSW_WriteLED_wrp.v(3) | Synthesizing module ReadSW_WriteLED_wrp @W:CS149 : ReadSW_WriteLED_wrp.v(39) | Port width mismatch for port subAddr. Formal has width 8, Actual 9 @W:CL247 : ReadSW_WriteLED_wrp.v(19) | Input port bit 8 of PADDR[8:0] is unused @W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[3] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[4] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[5] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[6] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[7] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[8] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[9] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[10] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[11] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[12] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[13] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[14] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[15] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[16] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[17] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[18] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[19] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[20] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[21] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[22] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[23] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[24] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[25] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[26] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[27] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[28] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[29] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[30] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[31] is always 0, optimizing ... @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 31 of data_out[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 30 of data_out[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 29 of data_out[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 28 of data_out[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 27 of data_out[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 26 of data_out[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 25 of data_out[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 24 of data_out[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 23 of data_out[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 22 of data_out[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 21 of data_out[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 20 of data_out[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 19 of data_out[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 18 of data_out[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 17 of data_out[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 16 of data_out[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 15 of data_out[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 14 of data_out[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 13 of data_out[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 12 of data_out[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 11 of data_out[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 10 of data_out[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 9 of data_out[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 8 of data_out[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 7 of data_out[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 6 of data_out[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 5 of data_out[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 4 of data_out[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 3 of data_out[31:0] @W:CL246 : ReadSW_WriteLED.v(14) | Input port bits 7 to 4 of subAddr[7:0] are unused @W:CL246 : ReadSW_WriteLED.v(14) | Input port bits 1 to 0 of subAddr[7:0] are unused @W:CL246 : ReadSW_WriteLED.v(16) | Input port bits 31 to 3 of data_in[31:0] are unused @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Sep 27 13:55:17 2011 ###########################################################]