/* Synchonization of Asynchronous switch input */
always@(posedge PCLK or negedge SW[0])
if(~SW[0])
	begin
	sw0_pulse[0] <= 1'b0;
	sw0_pulse[1] <= 1'b0;
	sw0_pulse[2] <= 1'b0;
	end
else
	begin
	sw0_pulse[0] <= 1'b1;
	sw0_pulse[1] <= sw0_pulse[0];
	sw0_pulse[2] <= sw0_pulse[1];
	end