#Build: Synplify Pro D-2009.12A, Build 040R, Jan 20 2010
#install: C:\Actel\Libero_v9.0\Synopsys\synplify_D200912A
#OS:  6.1
#Hostname: WIN-K2PJVCLULR9

#Implementation: synthesis

#Mon Oct 04 10:21:22 2010

$ Start of Compile
#Mon Oct 04 10:21:22 2010

Synopsys Verilog Compiler, version comp475rc, Build 060R, built Jan 15 2010
Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved

@I::"C:\Actel\Libero_v9.0\Synopsys\synplify_D200912A\lib\proasic\smartfusion.v"
@I::"Z:\eecs373-f10\labs\lab6\files\cc2520Fpga\component\Actel\SmartFusionMSS\MSS\2.2.101\mss_comps.v"
@I::"Z:\eecs373-f10\labs\lab6\files\cc2520Fpga\component\work\mycore\MSS_CCC_0\mycore_tmp_MSS_CCC_0_MSS_CCC.v"
@I::"Z:\eecs373-f10\labs\lab6\files\cc2520Fpga\component\work\mycore\mycore.v"
@I::"Z:\eecs373-f10\labs\lab6\files\cc2520Fpga\component\Actel\DirectCore\CORESPI\3.0.156\rtl\vlog\core_obfuscated\spi_master.v"
@I::"Z:\eecs373-f10\labs\lab6\files\cc2520Fpga\component\Actel\DirectCore\CORESPI\3.0.156\rtl\vlog\core_obfuscated\spi_slave.v"
@I::"Z:\eecs373-f10\labs\lab6\files\cc2520Fpga\component\Actel\DirectCore\CORESPI\3.0.156\rtl\vlog\core_obfuscated\corespi_sfr.v"
@I::"Z:\eecs373-f10\labs\lab6\files\cc2520Fpga\component\Actel\DirectCore\CORESPI\3.0.156\rtl\vlog\core_obfuscated\corespi.v"
@I::"Z:\eecs373-f10\labs\lab6\files\cc2520Fpga\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3_muxptob3.v"
@I::"Z:\eecs373-f10\labs\lab6\files\cc2520Fpga\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v"
@I::"Z:\eecs373-f10\labs\lab6\files\cc2520Fpga\component\work\mytop\mytop.v"
Verilog syntax check successful!
Options changed - recompiling
Selecting top level module mytop
@W:CG775 : coreapb3.v(13) | Found Component CoreAPB3 in library COREAPB3_LIB
@N:CG364 : coreapb3_muxptob3.v(13) | Synthesizing module CAPB3O

@N:CG364 : coreapb3.v(13) | Synthesizing module CoreAPB3

	APB_DWIDTH=6'b100000
	RANGESIZE=21'b000000000000100000000
	IADDR_ENABLE=1'b0
	APBSLOT0ENABLE=1'b1
	APBSLOT1ENABLE=1'b0
	APBSLOT2ENABLE=1'b0
	APBSLOT3ENABLE=1'b0
	APBSLOT4ENABLE=1'b0
	APBSLOT5ENABLE=1'b0
	APBSLOT6ENABLE=1'b0
	APBSLOT7ENABLE=1'b0
	APBSLOT8ENABLE=1'b0
	APBSLOT9ENABLE=1'b0
	APBSLOT10ENABLE=1'b0
	APBSLOT11ENABLE=1'b0
	APBSLOT12ENABLE=1'b0
	APBSLOT13ENABLE=1'b0
	APBSLOT14ENABLE=1'b0
	APBSLOT15ENABLE=1'b0
	CAPB3O1I=32'b00000000000000000000000000001000
	CAPB3I1I=32'b00000000000000000000000000001000
	CAPB3l1I=8'b00001100
	CAPB3OOl=8'b00001000
	CAPB3IOl=8'b00000100
	CAPB3lOl=8'b00000000
	CAPB3OIl=8'b00000100
	CAPB3IIl=8'b00000000
	CAPB3lIl=8'b00000000
	CAPB3Oll=16'b0000000000000001
	CAPB3Ill=16'b0000000000000000
	CAPB3lll=16'b0000000000000000
	CAPB3O0l=16'b0000000000000000
	CAPB3I0l=16'b0000000000000000
	CAPB3l0l=16'b0000000000000000
	CAPB3O1l=16'b0000000000000000
	CAPB3I1l=16'b0000000000000000
	CAPB3l1l=16'b0000000000000000
	CAPB3OO0=16'b0000000000000000
	CAPB3IO0=16'b0000000000000000
	CAPB3lO0=16'b0000000000000000
	CAPB3OI0=16'b0000000000000000
	CAPB3II0=16'b0000000000000000
	CAPB3lI0=16'b0000000000000000
	CAPB3Ol0=16'b0000000000000000
   Generated name = CoreAPB3_Z1

@N:CG364 : smartfusion.v(1814) | Synthesizing module VCC

@N:CG364 : smartfusion.v(1133) | Synthesizing module GND

@N:CG364 : mss_comps.v(37) | Synthesizing module OUTBUF_MSS

@N:CG364 : mss_comps.v(145) | Synthesizing module MSSINT

@N:CG364 : mss_comps.v(23) | Synthesizing module INBUF_MSS

@N:CG364 : mss_comps.v(85) | Synthesizing module BIBUF_OPEND_MSS

@N:CG364 : mss_comps.v(151) | Synthesizing module MSS_CCC

@N:CG364 : mss_comps.v(1) | Synthesizing module MSS_XTLOSC

@N:CG364 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(5) | Synthesizing module mycore_tmp_MSS_CCC_0_MSS_CCC

@N:CG364 : mss_comps.v(680) | Synthesizing module MSS_APB

@N:CG364 : mycore.v(5) | Synthesizing module mycore

@N:CG364 : corespi_sfr.v(5) | Synthesizing module CSPIlI

	USE_MASTER=32'b00000000000000000000000000000001
	USE_SLAVE=32'b00000000000000000000000000000000
   Generated name = CSPIlI_1s_0s

@N:CG364 : spi_master.v(5) | Synthesizing module spi_master

@W:CL118 : spi_master.v(731) | Latch generated from always block for signal CSPIll0[3:0], probably caused by a missing assignment in an if or case stmt
@N:CG364 : corespi.v(4) | Synthesizing module CORESPI

	FAMILY=32'b00000000000000000000000000001111
	USE_MASTER=32'b00000000000000000000000000000001
	USE_SLAVE=32'b00000000000000000000000000000000
   Generated name = CORESPI_15s_1s_0s

@N:CG364 : mytop.v(5) | Synthesizing module mytop

@W:CL246 : corespi.v(70) | Input port bits 1 to 0 of PADDR[3:0] are unused

@W:CL159 : corespi_sfr.v(84) | Input s_sck is unused
@W:CL159 : corespi_sfr.v(90) | Input s_mosi is unused
@W:CL159 : corespi_sfr.v(93) | Input s_ss is unused
@W:CL157 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(62) | *Output RCOSC_CLKOUT has undriven bits - a simulation mismatch is possible 
@W:CL157 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(63) | *Output MAINXIN_CLKOUT has undriven bits - a simulation mismatch is possible 
@W:CL157 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(64) | *Output LPXIN_CLKOUT has undriven bits - a simulation mismatch is possible 
@W:CL159 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(36) | Input CLKA is unused
@W:CL159 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(37) | Input CLKA_PAD is unused
@W:CL159 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(38) | Input CLKA_PADP is unused
@W:CL159 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(39) | Input CLKA_PADN is unused
@W:CL159 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(40) | Input CLKB is unused
@W:CL159 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(41) | Input CLKB_PAD is unused
@W:CL159 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(42) | Input CLKB_PADP is unused
@W:CL159 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(43) | Input CLKB_PADN is unused
@W:CL159 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(44) | Input CLKC is unused
@W:CL159 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(45) | Input CLKC_PAD is unused
@W:CL159 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(46) | Input CLKC_PADP is unused
@W:CL159 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(47) | Input CLKC_PADN is unused
@W:CL159 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(49) | Input LPXIN is unused
@W:CL159 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(50) | Input MAC_CLK is unused
@W:CL246 : coreapb3.v(217) | Input port bits 23 to 12 of PADDR[23:0] are unused

@W:CL159 : coreapb3.v(208) | Input PRESETN is unused
@W:CL159 : coreapb3.v(210) | Input PCLK is unused
@W:CL159 : coreapb3.v(356) | Input PRDATAS1 is unused
@W:CL159 : coreapb3.v(363) | Input PRDATAS2 is unused
@W:CL159 : coreapb3.v(370) | Input PRDATAS3 is unused
@W:CL159 : coreapb3.v(377) | Input PRDATAS4 is unused
@W:CL159 : coreapb3.v(384) | Input PRDATAS5 is unused
@W:CL159 : coreapb3.v(391) | Input PRDATAS6 is unused
@W:CL159 : coreapb3.v(398) | Input PRDATAS7 is unused
@W:CL159 : coreapb3.v(405) | Input PRDATAS8 is unused
@W:CL159 : coreapb3.v(412) | Input PRDATAS9 is unused
@W:CL159 : coreapb3.v(419) | Input PRDATAS10 is unused
@W:CL159 : coreapb3.v(426) | Input PRDATAS11 is unused
@W:CL159 : coreapb3.v(433) | Input PRDATAS12 is unused
@W:CL159 : coreapb3.v(440) | Input PRDATAS13 is unused
@W:CL159 : coreapb3.v(447) | Input PRDATAS14 is unused
@W:CL159 : coreapb3.v(454) | Input PRDATAS15 is unused
@W:CL159 : coreapb3.v(458) | Input PREADYS1 is unused
@W:CL159 : coreapb3.v(460) | Input PREADYS2 is unused
@W:CL159 : coreapb3.v(462) | Input PREADYS3 is unused
@W:CL159 : coreapb3.v(464) | Input PREADYS4 is unused
@W:CL159 : coreapb3.v(466) | Input PREADYS5 is unused
@W:CL159 : coreapb3.v(468) | Input PREADYS6 is unused
@W:CL159 : coreapb3.v(470) | Input PREADYS7 is unused
@W:CL159 : coreapb3.v(472) | Input PREADYS8 is unused
@W:CL159 : coreapb3.v(474) | Input PREADYS9 is unused
@W:CL159 : coreapb3.v(476) | Input PREADYS10 is unused
@W:CL159 : coreapb3.v(478) | Input PREADYS11 is unused
@W:CL159 : coreapb3.v(480) | Input PREADYS12 is unused
@W:CL159 : coreapb3.v(482) | Input PREADYS13 is unused
@W:CL159 : coreapb3.v(484) | Input PREADYS14 is unused
@W:CL159 : coreapb3.v(486) | Input PREADYS15 is unused
@W:CL159 : coreapb3.v(490) | Input PSLVERRS1 is unused
@W:CL159 : coreapb3.v(492) | Input PSLVERRS2 is unused
@W:CL159 : coreapb3.v(494) | Input PSLVERRS3 is unused
@W:CL159 : coreapb3.v(496) | Input PSLVERRS4 is unused
@W:CL159 : coreapb3.v(498) | Input PSLVERRS5 is unused
@W:CL159 : coreapb3.v(500) | Input PSLVERRS6 is unused
@W:CL159 : coreapb3.v(502) | Input PSLVERRS7 is unused
@W:CL159 : coreapb3.v(504) | Input PSLVERRS8 is unused
@W:CL159 : coreapb3.v(506) | Input PSLVERRS9 is unused
@W:CL159 : coreapb3.v(508) | Input PSLVERRS10 is unused
@W:CL159 : coreapb3.v(510) | Input PSLVERRS11 is unused
@W:CL159 : coreapb3.v(512) | Input PSLVERRS12 is unused
@W:CL159 : coreapb3.v(514) | Input PSLVERRS13 is unused
@W:CL159 : coreapb3.v(516) | Input PSLVERRS14 is unused
@W:CL159 : coreapb3.v(518) | Input PSLVERRS15 is unused
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Mon Oct 04 10:21:24 2010

###########################################################]
Synopsys Actel Technology Mapper, Version map500act, Build 058R, Built Jan 18 2010 09:16:23
Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved
Product Version D-2009.12A
@N:MF249 :  | Running in 32-bit mode. 
@N:MF258 :  | Gated clock conversion disabled  

@W:MO111 : mycore_tmp_mss_ccc_0_mss_ccc.v(62) | tristate driver RCOSC_CLKOUT on net RCOSC_CLKOUT has its enable tied to GND (module mycore_tmp_MSS_CCC_0_MSS_CCC) 
@W:MO111 : mycore_tmp_mss_ccc_0_mss_ccc.v(63) | tristate driver MAINXIN_CLKOUT on net MAINXIN_CLKOUT has its enable tied to GND (module mycore_tmp_MSS_CCC_0_MSS_CCC) 
@W:MO111 : mycore_tmp_mss_ccc_0_mss_ccc.v(64) | tristate driver LPXIN_CLKOUT on net LPXIN_CLKOUT has its enable tied to GND (module mycore_tmp_MSS_CCC_0_MSS_CCC) 
Automatic dissolve at startup in view:COREAPB3_LIB.CoreAPB3_Z1(verilog) of CAPB3llOI(CAPB3O)
Automatic dissolve at startup in view:work.mycore(verilog) of MSS_CCC_0(mycore_tmp_MSS_CCC_0_MSS_CCC)
Automatic dissolve at startup in view:work.mytop(verilog) of mycore_0(mycore)
Automatic dissolve at startup in view:work.mytop(verilog) of CoreAPB3_0(CoreAPB3_Z1)

Available hyper_sources - for debug and ip models
	None Found

Finished RTL optimizations (Time elapsed 0h:00m:02s; Memory used current: 56MB peak: 57MB)

@N: : spi_master.v(294) | Found counter in view:work.spi_master(verilog) inst CSPIOO1[7:0]
@N:MO106 : spi_master.v(731) | Found ROM, 'CSPIll1', 11 words by 1 bits 
Automatic dissolve during optimization of view:work.mytop(verilog) of CORESPI_0(CORESPI_15s_1s_0s)
Finished factoring (Time elapsed 0h:00m:02s; Memory used current: 57MB peak: 57MB)

Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:02s; Memory used current: 56MB peak: 57MB)

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:02s; Memory used current: 57MB peak: 57MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:02s; Memory used current: 57MB peak: 57MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:02s; Memory used current: 57MB peak: 57MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:02s; Memory used current: 57MB peak: 57MB)

Finished preparing to map (Time elapsed 0h:00m:02s; Memory used current: 57MB peak: 57MB)


High Fanout Net Report
**********************

Driver Instance / Pin Name              Fanout, notes                 
----------------------------------------------------------------------
mycore_0.MSS_ADLIB_INST / M2FRESETn     73 : 73 asynchronous set/reset
======================================================================

@N:FP130 :  | Promoting Net CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.un2_busy on CLKINT  CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.un2_busy_inferred_clock  
Buffering mycore_0_FAB_CLK, fanout 74 segments 4
Finished technology mapping (Time elapsed 0h:00m:02s; Memory used current: 57MB peak: 57MB)

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:03s; Memory used current: 57MB peak: 57MB)


Added 3 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication
Finished restoring hierarchy (Time elapsed 0h:00m:03s; Memory used current: 57MB peak: 57MB)

Writing Analyst data base Z:\eecs373-f10\labs\lab6\files\cc2520Fpga\synthesis\mytop.srm
Finished Writing Netlist Databases (Time elapsed 0h:00m:03s; Memory used current: 56MB peak: 57MB)

Writing EDIF Netlist and constraint files
D-2009.12A
Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:03s; Memory used current: 57MB peak: 57MB)

@W:MT420 :  | Found inferred clock mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock with period 1000.00ns. A user-defined clock should be declared on object "n:mycore_0_FAB_CLK" 

@W:MT420 :  | Found inferred clock spi_master|un2_busy_inferred_clock with period 1000.00ns. A user-defined clock should be declared on object "n:CORESPI_0.CSPIOl.genblk6.genblk7.CSPII1l.un2_busy" 

@W:MT246 : mycore.v(124) | Blackbox MSS_APB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W:MT246 : mycore.v(107) | Blackbox MSSINT is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W:MT246 : mycore_tmp_mss_ccc_0_mss_ccc.v(97) | Blackbox MSS_XTLOSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 


##### START OF TIMING REPORT #####[
# Timing Report written on Mon Oct 04 10:21:36 2010
#


Top view:               mytop
Library name:           smartfusion
Operating conditions:   COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree )
Requested Frequency:    1.0 MHz
Wire load mode:         top
Wire load model:        smartfusion
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. 

@N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock.. 



Performance Summary 
*******************


Worst slack in design: 987.186

                                                             Requested     Estimated     Requested     Estimated                 Clock        Clock              
Starting Clock                                               Frequency     Frequency     Period        Period        Slack       Type         Group              
-----------------------------------------------------------------------------------------------------------------------------------------------------------------
mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     1.0 MHz       78.0 MHz      1000.000      12.814        987.186     inferred     Inferred_clkgroup_0
System                                                       1.0 MHz       81.6 MHz      1000.000      12.249        987.751     system       default_clkgroup   
=================================================================================================================================================================





Clock Relationships
*******************

Clocks                                                                                                              |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                                  Ending                                                    |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock  mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock  |  1000.000    987.186  |  No paths    -      |  No paths    -      |  No paths    -    
mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock  spi_master|un2_busy_inferred_clock                        |  No paths    -        |  No paths    -      |  Diff grp    -      |  No paths    -    
spi_master|un2_busy_inferred_clock                        mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock  |  No paths    -        |  No paths    -      |  No paths    -      |  Diff grp    -    
============================================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

		No IO constraint found 



====================================
Detailed Report for Clock: mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                        Starting                                                                                         Arrival            
Instance                                                Reference                                                    Type         Pin     Net            Time        Slack  
                                                        Clock                                                                                                               
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.CSPIIl0[0]   mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1C0       Q       CSPIIl0[0]     0.737       987.186
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.CSPIIl0[3]   mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1C0       Q       CSPIIl0[3]     0.580       987.270
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.CSPIIl0[1]   mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1C0       Q       CSPIIl0[1]     0.737       987.774
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.CSPIIl0[2]   mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1C0       Q       CSPIIl0[2]     0.737       988.123
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.CSPII00      mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1C0       Q       CSPII00        0.737       990.480
CORESPI_0.CSPIOl.CSPIOOI[4]                             mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1E1C0     Q       CSPIOOI[4]     0.737       990.980
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.CSPIO00      mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1C0       Q       CSPIO00        0.580       992.464
CORESPI_0.CSPIOl.CSPIOOI[3]                             mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1E1C0     Q       CSPIOOI[3]     0.737       992.694
CORESPI_0.CSPIOl.CSPIOOI[5]                             mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1E1C0     Q       CSPIOOI[5]     0.580       992.902
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.CSPIOO1[1]   mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1E1C0     Q       CSPIOO1[1]     0.737       992.944
============================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                            Starting                                                                                                   Required            
Instance                                                    Reference                                                    Type         Pin     Net                      Time         Slack  
                                                            Clock                                                                                                                          
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.rx_data_reg[0]   mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1E1C0     E       rx_data_reg_0_sqmuxa     999.392      990.832
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.rx_data_reg[1]   mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1E1C0     E       rx_data_reg_0_sqmuxa     999.392      990.832
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.rx_data_reg[2]   mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1E1C0     E       rx_data_reg_0_sqmuxa     999.392      990.832
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.rx_data_reg[3]   mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1E1C0     E       rx_data_reg_0_sqmuxa     999.392      990.832
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.rx_data_reg[4]   mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1E1C0     E       rx_data_reg_0_sqmuxa     999.392      990.832
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.rx_data_reg[5]   mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1E1C0     E       rx_data_reg_0_sqmuxa     999.392      990.832
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.rx_data_reg[6]   mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1E1C0     E       rx_data_reg_0_sqmuxa     999.392      990.832
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.rx_data_reg[7]   mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1E1C0     E       rx_data_reg_0_sqmuxa     999.392      990.832
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.CSPII01          mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1E1C0     E       N_12                     999.392      990.878
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.CSPIOI1[1]       mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1E0C0     E       N_9                      999.566      990.883
===========================================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      1000.000
    - Setup time:                            0.608
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         999.392

    - Propagation time:                      12.206
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     987.186

    Number of logic level(s):                7
    Starting point:                          CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.CSPIIl0[0] / Q
    Ending point:                            CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.CSPIII1[0] / E
    The start point is clocked by            mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock [rising] on pin CLK
    The end   point is clocked by            mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock [rising] on pin CLK

Instance / Net                                                                 Pin      Pin               Arrival     No. of    
Name                                                              Type         Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.CSPIIl0[0]             DFN1C0       Q        Out     0.737     0.737       -         
CSPIIl0[0]                                                        Net          -        -       1.526     -           7         
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.CSPIIl0_RNIF0U3_1[0]   OR2A         B        In      -         2.263       -         
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.CSPIIl0_RNIF0U3_1[0]   OR2A         Y        Out     0.646     2.909       -         
N_105                                                             Net          -        -       0.806     -           3         
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.CSPIIl0_RNIU0S7[2]     OR2A         B        In      -         3.716       -         
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.CSPIIl0_RNIU0S7[2]     OR2A         Y        Out     0.646     4.362       -         
CSPIlO116                                                         Net          -        -       1.776     -           11        
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.CSPII00_RNIAJPE        OR2A         B        In      -         6.138       -         
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.CSPII00_RNIAJPE        OR2A         Y        Out     0.646     6.785       -         
N_86                                                              Net          -        -       0.322     -           1         
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.CSPII00_RNII7F51       NOR3C        C        In      -         7.106       -         
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.CSPII00_RNII7F51       NOR3C        Y        Out     0.641     7.748       -         
CSPII10_1_0_1                                                     Net          -        -       0.322     -           1         
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.CSPII00_RNIN96N1       AO1B         C        In      -         8.069       -         
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.CSPII00_RNIN96N1       AO1B         Y        Out     0.633     8.702       -         
CSPII10_1                                                         Net          -        -       0.386     -           2         
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.CSPIO10_RNI2CPO2       NOR2         B        In      -         9.088       -         
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.CSPIO10_RNI2CPO2       NOR2         Y        Out     0.514     9.602       -         
CSPIO11                                                           Net          -        -       0.386     -           2         
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.CSPIO0013_RNI65H23     MX2          A        In      -         9.988       -         
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.CSPIO0013_RNI65H23     MX2          Y        Out     0.579     10.567      -         
CSPIl11                                                           Net          -        -       1.639     -           8         
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.CSPIII1[0]             DFN1E1C0     E        In      -         12.206      -         
================================================================================================================================
Total path delay (propagation time + setup) of 12.814 is 5.652(44.1%) logic and 7.162(55.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                Starting                                                                             Arrival            
Instance                        Reference     Type           Pin              Net                                    Time        Slack  
                                Clock                                                                                                   
----------------------------------------------------------------------------------------------------------------------------------------
mycore_0.MSS_ADLIB_INST         System        MSS_APB        MSSPSEL          mycore_0_MSS_MASTER_APB_PSELx          0.000       987.751
mycore_0.MSS_ADLIB_INST         System        MSS_APB        MSSPENABLE       CoreAPB3_0_APBmslave0_PENABLE          0.000       987.786
mycore_0.MSS_ADLIB_INST         System        MSS_APB        MSSPADDR[11]     mycore_0_MSS_MASTER_APB_PADDR_\[11\]   0.000       987.993
mycore_0.MSS_ADLIB_INST         System        MSS_APB        MSSPADDR[8]      mycore_0_MSS_MASTER_APB_PADDR_\[8\]    0.000       988.027
mycore_0.MSS_ADLIB_INST         System        MSS_APB        MSSPADDR[10]     mycore_0_MSS_MASTER_APB_PADDR_\[10\]   0.000       988.041
mycore_0.MSS_ADLIB_INST         System        MSS_APB        MSSPADDR[9]      mycore_0_MSS_MASTER_APB_PADDR_\[9\]    0.000       988.181
mycore_0.MSS_ADLIB_INST         System        MSS_APB        MSSPWRITE        CoreAPB3_0_APBmslave0_PWRITE           0.000       989.814
mycore_0.MSS_ADLIB_INST         System        MSS_APB        MSSPADDR[2]      mycore_0_MSS_MASTER_APB_PADDR_\[2\]    0.000       991.262
mycore_0.MSS_ADLIB_INST         System        MSS_APB        MSSPADDR[3]      mycore_0_MSS_MASTER_APB_PADDR_\[3\]    0.000       991.413
mycore_0.MSS_CCC_0.I_XTLOSC     System        MSS_XTLOSC     CLKOUT           N_CLKA_XTLOSC                          0.000       994.169
========================================================================================================================================


Ending Points with Worst Slack
******************************

                                                     Starting                                                            Required            
Instance                                             Reference     Type         Pin              Net                     Time         Slack  
                                                     Clock                                                                                   
---------------------------------------------------------------------------------------------------------------------------------------------
mycore_0.MSS_ADLIB_INST                              System        MSS_APB      MSSPRDATA[0]     CSPII0l_RNII5LG9[0]     1000.000     987.751
mycore_0.MSS_ADLIB_INST                              System        MSS_APB      MSSPRDATA[1]     CSPIOOI_RNI092J9[1]     1000.000     987.751
mycore_0.MSS_ADLIB_INST                              System        MSS_APB      MSSPRDATA[2]     CSPIOOI_RNIS76J9[2]     1000.000     987.751
mycore_0.MSS_ADLIB_INST                              System        MSS_APB      MSSPRDATA[3]     CSPII0l_RNI3UIV9[3]     1000.000     987.751
mycore_0.MSS_ADLIB_INST                              System        MSS_APB      MSSPRDATA[7]     CSPII0l_RNISL4C9[7]     1000.000     987.751
mycore_0.MSS_ADLIB_INST                              System        MSS_APB      MSSPRDATA[4]     CSPIOOI_RNI0FLH7[4]     1000.000     988.170
mycore_0.MSS_ADLIB_INST                              System        MSS_APB      MSSPRDATA[5]     CSPIOOI_RNI2FLH7[5]     1000.000     988.170
mycore_0.MSS_ADLIB_INST                              System        MSS_APB      MSSPRDATA[6]     CSPIOOI_RNI4FLH7[5]     1000.000     988.170
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.CSPII01   System        DFN1E1C0     E                N_12                    999.392      989.407
CORESPI_0.CSPIOl.genblk6\.genblk7\.CSPII1l.CSPIl01   System        DFN1E1C0     E                N_14                    999.392      990.269
=============================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      1000.000
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         1000.000

    - Propagation time:                      12.249
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 987.751

    Number of logic level(s):                7
    Starting point:                          mycore_0.MSS_ADLIB_INST / MSSPSEL
    Ending point:                            mycore_0.MSS_ADLIB_INST / MSSPRDATA[1]
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                       Pin              Pin               Arrival     No. of    
Name                                     Type        Name             Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------
mycore_0.MSS_ADLIB_INST                  MSS_APB     MSSPSEL          Out     0.000     0.000       -         
mycore_0_MSS_MASTER_APB_PSELx            Net         -                -       0.322     -           1         
CORESPI_0.CSPIII_1_2                     NOR2A       A                In      -         0.322       -         
CORESPI_0.CSPIII_1_2                     NOR2A       Y                Out     0.627     0.949       -         
CSPIII_1_2                               Net         -                -       0.322     -           1         
CORESPI_0.CSPIII_1                       OR3C        C                In      -         1.270       -         
CORESPI_0.CSPIII_1                       OR3C        Y                Out     0.641     1.912       -         
CSPIII_1_i                               Net         -                -       1.279     -           5         
CORESPI_0.CSPIII                         NOR2        B                In      -         3.191       -         
CORESPI_0.CSPIII                         NOR2        Y                Out     0.514     3.705       -         
CSPIII                                   Net         -                -       1.776     -           11        
CORESPI_0.CSPIOl.rx_reg_re               OR2B        B                In      -         5.481       -         
CORESPI_0.CSPIOl.rx_reg_re               OR2B        Y                Out     0.627     6.109       -         
rx_reg_re                                Net         -                -       2.037     -           13        
CORESPI_0.CSPIOl.CSPIOOI_RNII21R1[5]     NOR2        A                In      -         8.146       -         
CORESPI_0.CSPIOl.CSPIOOI_RNII21R1[5]     NOR2        Y                Out     0.363     8.509       -         
CSPIll_1                                 Net         -                -       1.639     -           8         
CORESPI_0.CSPIOl.CSPIOOI_RNIPNET3[5]     AOI1B       A                In      -         10.148      -         
CORESPI_0.CSPIOl.CSPIOOI_RNIPNET3[5]     AOI1B       Y                Out     0.933     11.081      -         
CSPIll_iv_0[1]                           Net         -                -       0.322     -           1         
CORESPI_0.CSPIOl.CSPIOOI_RNI092J9[1]     OR3C        A                In      -         11.403      -         
CORESPI_0.CSPIOl.CSPIOOI_RNI092J9[1]     OR3C        Y                Out     0.525     11.928      -         
CSPIOOI_RNI092J9[1]                      Net         -                -       0.322     -           1         
mycore_0.MSS_ADLIB_INST                  MSS_APB     MSSPRDATA[1]     In      -         12.249      -         
==============================================================================================================
Total path delay (propagation time + setup) of 12.249 is 4.232(34.5%) logic and 8.017(65.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

--------------------------------------------------------------------------------
Target Part: A2F200M3F_FBGA256_Std
Report for cell mytop.verilog
  Core Cell usage:
              cell count     area count*area
               AO1     1      1.0        1.0
              AO1B     6      1.0        6.0
              AO1C     3      1.0        3.0
             AOI1B    14      1.0       14.0
              AOI5     1      1.0        1.0
              AX1C     5      1.0        5.0
              BUFF     3      1.0        3.0
            CLKINT     1      0.0        0.0
               GND     6      0.0        0.0
               INV     3      1.0        3.0
            MSSINT     5      0.0        0.0
           MSS_APB     1      0.0        0.0
           MSS_CCC     1      0.0        0.0
               MX2    20      1.0       20.0
              MX2C     3      1.0        3.0
              NOR2     9      1.0        9.0
             NOR2A     8      1.0        8.0
             NOR2B    23      1.0       23.0
              NOR3     2      1.0        2.0
             NOR3A     1      1.0        1.0
             NOR3B     3      1.0        3.0
             NOR3C     5      1.0        5.0
               OA1     2      1.0        2.0
              OA1A     2      1.0        2.0
               OR2     4      1.0        4.0
              OR2A     7      1.0        7.0
              OR2B    12      1.0       12.0
              OR3B    11      1.0       11.0
              OR3C    19      1.0       19.0
               VCC     6      0.0        0.0
             XNOR2     4      1.0        4.0
              XOR2     6      1.0        6.0


            DFN1C0    12      1.0       12.0
          DFN1E0C0    16      1.0       16.0
          DFN1E0P0     1      1.0        1.0
          DFN1E1C0    43      1.0       43.0
            DFN1P0     1      1.0        1.0
              DLN0     4      1.0        4.0
                   -----          ----------
             TOTAL   274               254.0


  IO Cell usage:
              cell count
   BIBUF_OPEND_MSS     2
             INBUF     3
         INBUF_MSS     5
        MSS_XTLOSC     1
            OUTBUF     3
        OUTBUF_MSS     4
                   -----
             TOTAL    18


Core Cells         : 254 of 4608 (6%)
IO Cells           : 18 of 66 (27%)

  RAM/ROM Usage Summary
Block Rams : 0 of 8 (0%)

Mapper successful!
Process took 0h:00m:04s realtime, 0h:00m:03s cputime
# Mon Oct 04 10:21:36 2010

###########################################################]