Igor Markov's publications

Highlight       -------------- by topic -------------- Circuit Test and Reliability Hypergraph Partitioning Logic and Physical Synthesis Intellectual Property Protection and Secure Hardware Post-silicon Diagnosis and Debug Quantum Circuits, Algorithms and SW SAT/ILP/BDD/Symmetries/Verification VLSI Physical Design and Physical Synthesis       ------------- by journal ------------- IEEE magazines IEEE Transactions APS Physical Review ACM Transactions       ---------- by conference --------- DAC and ASPDAC ICCAD and ICCD DATE ISPD IWLS

My papers with citations

Papers referenced by DBLP

arxiv

1. Books and Book Chapters
2. Journal papers
3. Publications in Conference and Workshop Proceedings
4. Invited talks
5. Conference and Workshop Presentations w/o Proceedings
6. Abstracts and Technical Reports

Books and Book Chapters

• L. Lavagno, I. L. Markov, G. E. Martin, L. K. Scheffer (eds), Electronic Design Automation for Integrated Circuits Handbook, CRC Press,2d ed., 2016, ISBN 978-1482254501.
• A. A. Kennings, I. L. Markov, ``Circuit Placement,'' in Encyclopedia of Algorithms, Springer, 2nd ed., 2016, pp. 301-306. ISBN 978-1-4939-2865-1.
• S. Krishnaswamy, I. L. Markov, J. P. Hayes, Design, Analysis and Test of Logic Circuits Under Uncertainty, 134 pages, Springer 2013. (available on Amazon), ISBN 978-9048196432.
• D. A. Papa and I. L. Markov, Multi-Objective Optimization in Physical Synthesis of Integrated Circuits, 164 pages, Springer 2013 (available on Amazon), ISBN 978-1461413554.
• H. Katebi and I. L. Markov, ``Large-scale Boolean Matching'' in Advanced Techniques in Logic Synthesis, Optimizations and Applications, S. Khatri and K. Gulati, eds; Springer, 2011.
• A. B. Kahng, J. Lienig, I. L. Markov, J. Hu, VLSI Physical Design: from Graph Partitioning to Timing Closure, 312 pages, Springer 2011 (flyer, official site, available on Amazon) ISBN 978-90-481-9590-9.
• G. F. Viamontes, I. L. Markov, J. P. Hayes, Quantum Circuit Simulation, Springer 2009 (cover, available on Amazon.com) ISBN: 978-9048130641
• K.-H. Chang, I. L. Markov, V. Bertacco, Functional Design Errors in Digital Circuits: Diagnosis, Correction and Layout Repair, Springer 2008 (official site, available on Amazon.com) ISBN: 978-1-4020-9364-7.
• J. A. Roy and I. L. Markov, ``Partitioning-driven Techniques for VLSI Placement'' in Handbook of Algorithms for VLSI Physical Design Automation, C. Alpert, D. Mehta and S. Sapatnekar, eds; CRC Press, 2008. ISBN: 0849372429.
• A. A. Kennings and I. L. Markov, ``Circuit Placement'' in Encyclopedia of Algorithms, M.-Y. Kao, ed.; pp. 143-146, Springer, 2008.
• J. A. Roy, D. A. Papa and I. L. Markov, ``Capo: Congestion-aware Placement for Standard-cell and RTL Netlists with Incremental Capability'' () in Modern Circuit Placement: Best Practices and Results, G.-J. Nam and J. Cong, eds; Springer, 2007. (ISBN: 038736837X)
• D. A. Papa and I. L. Markov, ``Hypergraph Partitioning and Clustering'' in Approximation Algorithms and Metaheuristics, T. Gonzalez, ed.; pages 61-1 through 61-19, CRC Press, CRC Press, 2007.
• A. Ramani and I. L. Markov, ``Automatically Exploiting Symmetries in Constraint Programming'' Lecture Notes in Computer Science vol. 3419, p. 98, Springer, March 2005.
• D. B. Motter and I. L. Markov, ``A Compressed Breadth-First Search For Satisfiability'' In Lecture Notes in Computer Science vol. 2409, Springer, 2002, pp. 29-42.
• A. E. Caldwell, A. B. Kahng and I. L. Markov, ``Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist Partitioning'' In Lecture Notes in Computer Science vol. 1619, Springer, 1999, pp. 177-193.

Publications in journals and magazines

• T. N. Mudge, F. T. Chong, I. L. Markov, R. Sendag, J. J. Yi, D. Chiou, ``Impact of Future Technologies on Architecture,'' IEEE Micro 36(4): 48-56, 2016.

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• M. M. Sabry Aly et al, ``Energy-Efficient Abundant-Data Computing: The N3XT 1,000x,'' IEEE Computer 48(12), pp. 24-33, November 2015.
• I. L. Markov, J. Hu, M.-C. Kim, ``Progress and Challenges in VLSI Placement Research,'' Proceedings of IEEE 103(11), pp. 1985-2003, 2015.
• S. M. Plaza, I. L. Markov, ``Solving the Third-Shift Problem in IC Piracy With Test-Aware Logic Locking,'' IEEE Trans. on CAD of Integrated Circuits and Systems 34(6), pp. 961-971, 2015.
• H. J. Garcia and I. L. Markov, ``Simulation of Quantum Circuits via Stabilizer Frames,'' IEEE Trans. on Computers, 64(8), pp. 2323-2336, 2015.

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• I. L. Markov, ``Limits on Fundamental Limits to Computation,'' Nature 512, pp. 147-154, August 2014 (10.1038/nature13570) (on readcube)
• H. J. Garcia, I. L. Markov, and A. W. Cross, ``On the Geometry of Stabilizer States,'' Quantum Information and Computation, vol. 14, no. 7-8, pp. 683-720, 2014.

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• R. R. Nadakuditi and I. L. Markov, ``On Bottleneck Analysis in Stochastic Stream Processing'' ACM Trans. on Design Automation of Electronic Systems (TODAES), vol. 18, no. 3, article #34, July 2013.
• M.-C. Kim, D.-J. Lee and I.L.Markov, ``SimPL: An Algorithm for Placing VLSI Circuits,'' Communications of the ACM, vol. 56 no. 6, pp. 105-113, June 2013.
• M. Saeedi, I. L. Markov, ``Synthesis and Optimization of Reversible Circuits - A Survey'' (arxiv), ACM Computing Surveys vol. 45, no. 2, February 2013.
• I. L. Markov, ``Know Your Limits: A Review of `Limits to Parallel Computation: P-Completeness Theory''' IEEE Design and Test vol. 30, no. 1, pp. 78-83, January 2013.
• I. L. Markov, M. Saeedi, ``Faster Quantum Number Factoring via Circuit Synthesis'' (arxiv), Physical Review A 87, 012310, 2013.

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• I. L. Markov, ``Too Much Automation?'' IEEE Design and Test, vol. 29, no. 2, 2012, pp. 96-98.
• I. L. Markov and M. Saeedi, ``Constant-optimized Quantum Circuits for Modular Multiplication and Exponentiation'' (arxiv), Quantum Information and Computation, vol. 12 no. 5-6, 2012, pp.361-394.
• J. Knechtel, I. L. Markov, J. Lienig, ``Assembling 2D Blocks into 3D Chips'' IEEE Trans. on Computer-Aided Design, vol. 31(2), pp. 228-241.
• D.-J. Lee, I. L. Markov, ``Obstacle-aware Clock-tree Shaping during Placement'' IEEE Trans. on Computer-Aided Design, vol. 31(2) 205-216, 2012.
• M.-C. Kim, D.-J. Lee, I. L. Markov, ``SimPL: An Effective Placement Algorithm'' IEEE Trans. on Computer-Aided Design, vol. 31(1), pp. 50-60, 2012.

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• I. L. Markov, ``Getting Your Bits in Order,'' IEEE Design and Test of Computers, vol. 28, no. 4, pp. 98-101, 2011 (reprinted by IEEE Computer Society).
• D. A. Papa, C. Sze, N. Viswanathan, Z. Li, G. Nam, C. J. Alpert, I. L. Markov, ``Physical Synthesis with Clock-network Optimization for Large SoCs'' (online), IEEE Micro 31(4), pp.51-62, 2011.
• I. L. Markov and Y. Shi, ``Constant-Degree Graph Expansions that Preserve Treewidth'' (arxiv), Algorithmica, vol. 59, no. 4, pp. 461-470, 2011.
• I. L. Markov, ``EDA: Synergy or sum of the parts?'' IEEE Design and Test of Computers, vol. 28, no. 1, 2011, pp. 78-79.
• D.-J. Lee and I. L. Markov, ``Contango: Integrated Optimization for SoC Clock Networks'' VLSI Design, vol. 2011, no. 407507, 12 pp., 2011.

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• J. A. Roy, F. Koushanfar and I. L. Markov, ``Ending Piracy of Integrated Circuits'' (online), IEEE Computer, October 2010, pp. 30-38.
• D. A. Papa, M. D. Moffitt, C. J. Alpert, I. L. Markov, ``Speeding up Physical Synthesis with Transactional Timing Analysis'' (pdf), IEEE Design and Test of Computers, vol. 27, no. 5, 2010, pp. 14-25.
• S. Yamashita, I. L. Markov, ``Fast Equivalence-checking for Quantum Circuits'' Quantum Information and Computation, vol.9, no.9-10, 2010, pp. 721-734.
• I. L. Markov, ``Chips in 3D'' (review of Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures by Y. Xie, J. Cong, and S. Sapatnekar, eds.) IEEE Design and Test of Computers, vol. 27, no. 4, July-Aug 2010, pp. 68-69.
• F. Koushanfar and I. L. Markov, ``Designing Chips that Protect Themselves'' ACM DAC Knowledge Center, March 2010.
• K.-H. Chang, V. Bertacco, I. L. Markov and A. Mishchenko, ``Logic Synthesis and Circuit Customization Using Extensive External Don't-Cares'' ACM Trans. on Design Autom. Elec. Sys (TODAES) 15 (3), May 2010.
• I. L. Markov, ``Master Numerical Tasks with Ease, (review of Advanced Excel for Scientific Data Analysis, 2nd ed. by de R. Levie, 2008)'' IEEE Design and Test of Computers, vol. 27, no. 1, Jan-Feb 2010 pp. 93-95.

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• I. L. Markov, ``A Physical-design Picture Book'' (review of Practical Problems in VLSI Physical Design Automation by S.K. Lim; 2008), IEEE Design and Test of Computers, vol. 26, no. 4, July-Aug 2009 pp. 100-101.
• V. V. Shende and I. L. Markov, ``On the CNOT-cost of TOFFOLI Gates'' (arxiv), Quantum Information and Computation, vol. 9, no. 5-6, pp. 461-486, May 2009.
• J. A. Roy, A. N. Ng, R. Aggarwal, V. Ramachandran, and I. L. Markov, ``Solving modern mixed-size placement instances,'' Integration vol. 42 no. 2, pp. 262-275, 2009.
• K.-H. Chang, D. A. Papa, I. L. Markov, V. Bertacco, ``Invers: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization'' IEEE Design and Test of Computers, vol. 26, no. 2, pp. 34-43, March 2009.
• F. A. Aloul, A. Ramani, I. L. Markov, K. A. Sakallah, ``Dynamic Symmetry-Breaking for Boolean Satisfiability,'' Annals of Mathematics and Artificial Intelligence, vol. 51. no. 1, 2009, pp. 59-73.
• S. Krishnaswamy, S. Plaza, I. L. Markov, and J. P. Hayes, ``Signature-based SER Analysis and Design of Logic Circuits'' IEEE Trans. on Computer-Aided Design, vol.28, no.1, pp. 74-86, January 2009.

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• D. A. Papa, T. Luo, M. D. Moffitt, C. N. Sze, Z. Li, G.-J. Nam, C. J. Alpert and I. L. Markov, ``RUMBLE: An Incremental, Timing-driven, Physical-synthesis Optimization Algorithm'' IEEE Trans. on Computer-Aided Design, vol. 27, no.12, pp. 2156-2168, December 2008.
• S. M. Plaza, Igor L. Markov, and V. M. Bertacco, ``Optimizing Non-Monotonic Interconnect using Functional Simulation and Logic Restructuring'' , IEEE Trans. on Computer-Aided Design, vol.27, no.12, pp. 2107-2119, December 2008.
• M. D. Moffitt, J. A. Roy, I. L. Markov, M. E. Pollack, ``Constraint-driven Floorplan Repair,'' ACM Trans. on Design Automation of Electronic Systems (TODAES) , 13(4), October 2008.
• J. A. Roy, D. A. Papa, I. L. Markov, ``Fine Control of Local Whitespace in Placement,'' VLSI Design, vol. 2008, article 517919, 10 pp. DOI:10.1155/2008/517919.
• K-H. Chang, I.L. Markov and V. Bertacco, ``Automating Post-Silicon Debugging and Repair'' , IEEE Computer, vol. 41, no. 7, pp. 47-54, July 2008.
• I. L. Markov and Y.-Y. Shi, ``Simulating Quantum Computation by Contracting Tensor Networks'' (quant-ph), SIAM Journal on Computing, vol. 38, no. 3, pp.963-981, June 2008.
• J. A. Roy and I. L. Markov, ``High-performance Routing at the Nanometer Scale'' IEEE Trans. on Computer-Aided Design, vol. 27, no. 6, pp. 1066-1077, June 2008.
• K.-H. Chang, I. L. Markov, V. Bertacco, ``SafeResynth: A New Technique for Physical Synthesis'' Integration: the VLSI Journal, vol. 41, pp. 544-556, 2008.
• K. N. Patel, I. L. Markov, and J. P. Hayes, ``Optimal Synthesis of Linear Reversible Circuits'' Quantum Information and Computation, vol. 8, no. 3-4, pp. 282-294, 2008.
• S. Krishnaswamy, G. F. Viamontes, I. L. Markov, J. P. Hayes, ``Probabilistic Transfer Matrices in Symbolic Reliability Analysis of Logic Circuits'' ACM Trans. on Design Automation of Electronic Systems, vol. 13, no. 1, #8, January 2008.
• K.-H. Chang, I. L. Markov, V. Bertacco, ``Fixing Design Errors with Counterexamples and Resynthesis'' IEEE Trans. on Computer-Aided Design, vol. 27, no. 1, pp. 184-188, January 2008.

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• J. A. Roy and I. L. Markov, ``ECO-system: Embracing the Change in Placement'' IEEE Trans. on Computer-Aided Design, vol. 26, no. 12, pp. 2173-2185, December 2007.
• F. A. Aloul, A. Ramani, I. L. Markov, K. A. Sakallah, ``Symmetry-Breaking for Pseudo-Boolean Formulas'', ACM Journal on Experimental Algorithms 12, #1.3, 2007.
• F. A. Aloul, I. L. Markov and K. A. Sakallah, ``Solution and Optimization of Systems of Pseudo-Boolean Constraints,'' IEEE Trans. on Computers, vol. 56, no. 10, pp. 1415-1424, October 2007.
• K.-H. Chang, I. L. Markov and V. Bertacco, ``Post-placement Rewiring by Exhaustive Search for Functional Symmetries'' ACM Trans. on Design Automation of Electronic Systems (TODAES), 12(3), #32, August 2007.
• S. Krishnaswamy, I. L. Markov, J. P. Hayes, ``Tracking Uncertainty with Probabilistic Logic Circuit Testing'' IEEE Design and Test of Computers, vol. 24, no. 4, pp.312-321, July-August 2007.
• I. L. Markov, L. K. Scheffer, D. Stroobandt, `` Guest Editors' Introduction: Special issue on System-Level Interconnect,'' Integration, the VLSI Journal, 40/4, p.381, 2007.
• J. A. Roy and I. L. Markov, ``Seeing the Forest and the Trees: Steiner Wirelength Optimization in Placement'' IEEE Trans. on Computer-Aided Design, vol. 26 no. 4, pp. 632-644, April 2007.
• K.-H. Chang, V. Bertacco and I. L. Markov, ``Simulation-based Bug Trace Minimization with BMC-based Refinement'' IEEE Trans. on Computer-Aided Design, vol. 26, no. 1, pp. 152-165, January 2007.

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• A. K. Prasad, V. V. Shende, K. N. Patel, I. L. Markov, J. P. Hayes, ``Data Structures and Algorithms for Simplifying Reversible Circuits'' ACM Journal of Emerging Technologies in Computing Systems, vol. 2, no. 4, pp. 277-293, October 2006.
• A. Ramani, F. A. Aloul, I. L. Markov and K. A. Sakallah, ``Breaking Instance-Independent Symmetries in Exact Graph Coloring'' Journal of Artificial Intelligence Research, vol. 26, pp. 191-224, 2006.
• S. N. Adya, I. L. Markov and P. G. Villarrubia, ``On Whitespace and Stability in Physical Synthesis'' Integration, the VLSI Journal, vol. 39/4, pp. 340-362, 2006.
• J. A. Roy, S. N. Adya, D. A. Papa and I. L. Markov, ``Min-cut Floorplacement'' IEEE Trans. on Computer-Aided Design, vol.25, no.7, pp. 1313-1326, July 2006.
• V. V. Shende, S. S. Bullock, I. L. Markov, ``Synthesis of Quantum Logic Circuits'' IEEE Trans. on Computer-Aided Design, vol.25, no.6, June 2006, pp. 1000-1010.
• F. A. Aloul, K. A. Sakallah, and I. L. Markov, ``Efficient Symmetry Breaking for Boolean Satisfiability'' IEEE Trans. on Computers, vol. 55, no. 5, pp. 541-558, May 2006.
• K. M. Svore, A. W. Cross, I. L. Chuang, A. V. Aho and I. L. Markov, ``A Layered Software Architecture for Quantum Computing Design Tools'' IEEE Computer, vol. 39, no. 1, pp. 74-83, January 2006.

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• G. F. Viamontes, I. L. Markov and J. P. Hayes, ``Is Quantum Search Practical?'' IEEE/AIP Computing in Science and Engineering, May/June 2005, pp. 62-70.
• D. B. Motter, J. A. Roy, and I. L. Markov, ``Resolution Cannot Polynomially Simulate Compressed-BFS'' Annals of Mathematics and Artificial Intelligence, vol.44, no.1-2, pp. 121-156, May 2005.
• G. F. Viamontes, I. L. Markov and J. P. Hayes, ``Graph-based Simulation of Quantum Computation in the Density Matrix Representation'' Quantum Information and Computation, vol.5, no.2 pp. 113-130, February 2005.
• S. N. Adya and I. L. Markov, ``Combinatorial Techniques for Mixed-size Placement'' ACM Trans. on Design Automation of Electronic Systems, vol. 10, no. 5, January 2005.
• V. V. Shende and I. L. Markov, ``Quantum Circuits for Incompletely Specified Two-Qubit Operators'' Quantum Information and Computation, vol.5, no.1, pp. 49-57, January 2005.

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• F. A. Aloul, I. L. Markov and K. A. Sakallah, ``MINCE: A Static Global Variable-Ordering for SAT Search and BDD Manipulation'' Journal of Universal Computer Science, vol. 10, no. 12, pp. 1559-1562, December 2004.
• K. N. Patel and I. L. Markov, ``Error Correction and Crosstalk Avoidance in DSM Busses'' IEEE Trans. on VLSI vol. 12, no. 10, pp. 1076-1081, October 2004.
• K. N. Patel, J. P. Hayes, and I. L. Markov, ``Fault Testing for Reversible Circuits'' IEEE Trans. on CAD, 23(8), pp. 1220-1230, August 2004.
• V. V. Shende, S. S. Bullock, and I. L. Markov, ``Recognizing Small-circuit Structure in Two-qubit Operators,'' quant-ph/0308045 APS Physical Review A 70, 012310-012314, July 2004. Reprinted in APS/AIP Virtual Journal of Quantum Information, August 2004.
• V. V. Shende, I. L. Markov, and S. S. Bullock, ``Minimal Universal Two-qubit Controlled-NOT-based Circuits'' (quant-ph/0308033), APS Physical Review A 69, 062321-062329, July 2004. Reprinted in APS/AIP Virtual Journal of Quantum Information, July 2004.
• S. N. Adya et al., ``Benchmarking for Large-Scale VLSI Placement and Beyond'' IEEE Trans. on CAD, 23(4), April 2004, pp. 472-488.
• S. S. Bullock and I. L. Markov, ``Asymptotically Optimal Circuits for Arbitrary n-qubit Diagonal Computations,'' (quant-ph/0303039), Quantum Information and Computation, vol. 4, no. 1, January 2004, pp. 27-47.

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• S. N. Adya and I. L. Markov, ``Fixed-outline Floorplanning : Enabling Hierarchical Design'' IEEE Trans. on VLSI, vol. 11(6), December 2003, pp. 1120-1135.
• A. Caldwell, A. B. Kahng and I. L. Markov, ``Hierarchical Whitespace Allocation in Top-down Placement'' IEEE Trans. on CAD, vol. 22(11), November 2003, pp. 716-724.
• G. F. Viamontes, I. L. Markov and J. P. Hayes, ``Improving Gate-Level Simulation of Quantum Circuits'' (quant-ph/0309060), Quantum Information Processing, vol. 2(5), October 2003, pp. 347-380.
• F. A. Aloul, A. Ramani, I. L. Markov and K. A. Sakallah, ``Solving Difficult Instances of Boolean Satisfiability in the Presence of Symmetry'' IEEE Trans. on CAD, vol. 22(9), Sept 2003, pp. 1117-1137.
• S. S. Bullock and I. L. Markov, ``An Arbitrary Two-qubit Computation in 23 Elementary Gates'' APS Physical Review A vol. 68(1), July 2003, 012318-012325.
  Reprinted in APS/AIP Virtual Journal of Quantum Information, August 2003.
• V. V. Shende, A. K. Prasad, I. L. Markov and J. P. Hayes, ``Synthesis of Reversible Logic Circuits'' IEEE Trans. on CAD, vol 22(6), June 2003, pp. 710-722 (best paper award).
• Y. Cao, A. B. Kahng, X. Huang, I. L. Markov, M. R. Oliver, D. Stroobandt and D. Sylvester, "Improved A Priori Interconnect Predictions and Technology Extrapolation in the GTX System" IEEE Trans. on VLSI, vol. 11(1), January 2003, pp. 3-14.

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• A. A. Kennings and I. L. Markov, "Smoothening Max-terms and Analytical Minimization of Half-Perimeter Wirelength" VLSI Design, vol. 14, no. 3, 2002, pp. 229-237.
• A. E. Caldwell, A. B. Kahng and I. L. Markov, "Toward CAD-IP Reuse: The MARCO GSRC Bookshelf of Fundamental CAD Algorithms" IEEE Design and Test of Computers, May 2002, pp. 72-81.

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• R. Baldick, A. B. Kahng, A. A. Kennings and I. L. Markov, "Efficient Optimization by Modifying the Objective Function" IEEE Trans. on Circuits and Systems, vol. 48, no. 8, pp. 947-957, 2001.
• A. B. Kahng et al., "Constraint-Based Watermarking Techniques for Design Intellectual Property Protection" IEEE Trans. on CAD, vol. 20, no. 10, 2001, pp. 1236-1252.

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• A. E. Caldwell, A. B. Kahng, I. L. Markov, "Optimal Partitioners and End-case Placers for Standard-cell Layout" , IEEE Trans. on CAD, vol. 19, no. 11, pp. 1304-1314, 2000.
• A. E. Caldwell, A. B. Kahng, I. L. Markov, "Iterative Partitioning With Varying Node Weights", VLSI Design, vol. 11, no. 3, 2000, pp. 249-58
• C. J. Alpert, A. E. Caldwell, A. B. Kahng, I. L. Markov, "Hypergraph Partitioning With Fixed Vertices" IEEE Trans. on CAD, vol. 19, no. 2, 2000, pp. 267-272.
• A. E. Caldwell, A. B. Kahng, I. L. Markov, "Design and Implementation of Move-Based Heuristics for VLSI Hypergraph Partitioning" ACM Journal on Experimental Algorithms, vol. 5, 2000.

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• C. J. Alpert, A. E. Caldwell, T. F. Chan, D. J.-H. Huang, A. B. Kahng, I. L. Markov and M. S. Moroz, "Analytic Engines Are Unnecessary in Top-Down Partitioning-Based Placement" (.ps), VLSI Design, 10(1) (1999), pp. 99-116.
• A. E. Caldwell, A. B. Kahng, S. Mantik, I. L. Markov and A. Zelikovsky,   "On Wirelength Estimations for Row-Based Placement" IEEE Trans. on CAD 18(9), (1999), pp. 1265-1278.

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• C. J. Alpert, T. Chan, A. B. Kahng, I. Markov, P. Mulet, "Faster Minimization of Linear Wirelength for Global Placement" IEEE Trans. on CAD 17(1) (1998), pp. 3-13.

Conference and Workshop Refereed Proceedings

• S. Osmolovskyi, J. Knechtel, I. L. Markov, J. Lienig, ``Optimal die placement for interposer-based 3D ICs,'' ASP-DAC 2018, pp. 513-520.
• R.I. Bahar, A.K. Jones, S. Katkoori, P.H. Madden, D.Marculescu, and I.L.Markov, ``Workshops on Extreme Scale Design Automation (ESDA) Challenges and Opportunities for 2025 and Beyond'' Computing Community Consortium (CCC), 2014.
• M. Wang, A. Yates, and I.L. Markov, ``SuperPUF: Integrating Heterogeneous Physically Unclonable Functions'' ICCAD 2014.
• S.M. Plaza and I.L. Markov, ``Protecting Integrated Circuits from Piracy with Test-aware Logic Locking,'' , ICCAD 2014.

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• P. Codenotti, H. Katebi, K. A. Sakallah and I. L. Markov, ``Conflict Analysis and Branching Heuristics in the Search for Graph Automorphisms,'' in Proc. Int'l Conf. on Tools with Artificial Intelligence (ICTAI), pp. 907-914, Washington, DC, 2013.
• A. B. Kahng, S. Kang, H. Lee, I. L. Markov, P. Thapar, ``High-Performance Gate Sizing with a Signoff Timer'' in Proc. Int'l. Conf. Comp.-Aided Design (ICCAD), 450-457, San Jose, CA, 2013.
• H. Katebi, K. Sakallah, I. L. Markov, ``Generalized Boolean Symmetries Through Nested Partition Refinement'' in Proc. Int'l. Conf. Comp.-Aided Design (ICCAD), pp. 763-770, San Jose, CA, 2013.
• H. J. Garcia, I. L. Markov, "Quipu: High-performance Simulation of Quantum Circuits using Stabilizer Frames'' Int'l Conf. Computer Design (ICCD), pp. 404-410, Asheville, NC, 2013.
• I. R. Bahar, A. K. Jones, S. Katkoori, P. H. Madden, D. Marculescu, and I. L. Markov, "Scaling the Impact of EDA Education: Preliminary Findings from the CCC Workshop Series on Extreme Scale Design Automation," in Proc. Conf. on Microelectronic Systems Education (MSE), Austin, TX, 2013.
• J. Hu, M.-C. Kim, I. L. Markov, ``Taming the Complexity of Coordinated Place and Route'' , in Proc. Design Automation Conference (DAC), pp. 150-155, Austin, TX, 2013.
• Y. Yao, M.-B. Kim, J. Li, I. L. Markov, F. Koushanfar, ``ClockPUF: Physical Unclonable Functions based on Clock Networks'' in Proc. Design Automation and Test in Europe (DATE), pp. 422-427, Grenoble, France, March 2013.

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• I. L. Markov, J. Hu, M.-C. Kim, ``Progress and Challenges in VLSI Placement Research'' in Proc. Int'l. Conf. Comp.-Aided Design (ICCAD), San Jose, CA, November 2012.
• J. Hu, A. B. Kahng, S. Kang, M.-C. Kim, I. L. Markov, ``Sensitivity-guided Metaheuristics for Accurate Discrete Gate Sizing'' in Proc. Int'l. Conf. Comp.-Aided Design (ICCAD), San Jose, CA, November 2012.
• J. Knechtel, I. L. Markov, J. Lienig, and M. Thiele, ``Multiobjective Optimization of Deadspace, a Critical Resource for 3D-IC Integration'' in Proc. Int'l. Conf. Comp.-Aided Design (ICCAD), San Jose, CA, November 2012.
• H. Katebi, K. A. Sakallah and I. L. Markov, ``Graph Symmetry Detection and Canonical Labeling: Differences and Synergies'' in Proc. Turing-100, EPIC vol. 10, pp. 181-195, Manchester, UK, 2012. (Best-paper award)
• M.-C. Kim and I.L. Markov, ``ComPLx: A Competitive Primal-dual Lagrange Optimization for Global Placement'' in Proc. Design Autom. Conf. (DAC), pp. 747-755, San Francisco, CA, 2012.
• H. Katebi, K. A. Sakallah and I. L. Markov, ``Conflict Anticipation in the Search for Graph Automorphisms'' in Proc. Int'l Conf. on Logic for Programming, Artificial Intelligence and Reasoning (LPAR), LNCS vol. 7180, pp. 243-257, Merida, Venezuela, 2012.
• T. Güneysu, I. L. Markov, A. Weimerskirch, ``Securely Sealing Multi-FPGA Systems'' in Proc. Int'l Symp. on Applied Reconfigurable Computing (ARC), LNCS vol. 7199, pp. 276-289, Hong Kong, March 2012.
• M.-C. Kim, N. Viswanathan, C. J. Alpert, I. L. Markov and S. Ramji, ``MAPLE: Multilevel Adaptive PLacEment for Mixed-Size Designs,'' in Proc. Int'l Symp. Physical Design (ISPD), pp. 193-200, San Francisco, March 2012 (BPA nominee).
• K.-H. Chang, H.-Z. Chou, I. L. Markov, ``RTL Analysis and Modifications for Improving At-speed Test,'' in Proc. Design Autom. and Test in Europe Conf. (DATE), pp. 400-405, Dresden, March 2012 (BPA nominee).

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• I. L. Markov, D.-J. Lee, ``Algorithmic Tuning of Clock Trees and Derived Non-Tree Structures'' in Proc. Int'l. Conf. Comp.-Aided Design (ICCAD), pp. 279-282, November 2011.
• M.-C. Kim, J. Hu, D.-J. Lee, I. L. Markov, ``A SimPLR method for Routability-driven Placement'' in Proc. Int'l. Conf. Comp.-Aided Design (ICCAD), pp. 67-73, November 2011 (BPA nominee).
• D.-J. Lee, I. L. Markov, ``Multilevel Tree Fusion for Robust Clock Networks'' in Proc. Int'l. Conf. Comp.-Aided Design (ICCAD), pp. 632-639, November 2011.
• D.-J. Lee, I. L. Markov, ``Obstacle-aware Clock-tree Shaping during Placement'' (BPA nominee) in Proc. Int'l. Symp. on Physical Design (ISPD), pp. 123-130, March 2011.
• J. Knechtel, I. L. Markov, J. Lienig, ``Assembling 2D Blocks into 3D Chips'' in Proc. Int'l. Symp. on Physical Design (ISPD), pp. 81-88, March 2011.

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• D. A. Papa, S. Krishnaswamy, I. L. Markov, ``SPIRE: A Retiming-based Physical-Synthesis Transformation System'' in Proc. Int'l. Conf. on Computer-Aided Design (ICCAD), pp. 373-380, November 2010.
• D.-J. Lee, M.-C. Kim, I. L. Markov, ``Low-Power Clock Trees for CPUs'' in Proc. Int'l. Conf. on Computer-Aided Design (ICCAD), pp. 444-451, November 2010.
• M.-C. Kim, D.-J. Lee, I. L. Markov, ``SimPL: An Effective Placement Algorithm'' in Proc. Int'l. Conf. on Computer-Aided Design (ICCAD), pp. 649-656, November 2010 (best paper award).
• H. Katebi, K. A. Sakallah, I. L. Markov, ``Symmetry and Satisfiability: An Update'' in Proc. Satisfiability Symposium (SAT), pp. 113-127, Edinburgh, Scotland, July 2010.
• S. Yamashita, I. L. Markov, ``Fast Equivalence-checking for Quantum Circuits'' in Proc. Int'l Symp. on Nanoscale Architectures, pp. 23-28, (NanoArch), Anaheim, CA, June 2010.
• R. R. Nadakuditi, I. L. Markov, ``On the Costs and Benefits of Stochasticity in Stream Processing'' in Proc. Design Autom. Conf. (DAC), pp. 320-325, Anaheim, CA, June 2010.
• J. Hu, J. A. Roy, I. L. Markov, ``Completing High-quality Routes'' in Proc. Int'l. Symp. on Physical Design (ISPD), pp. 35-40, San Francisco, CA, March 2010.
• H. J. Garcia and I. L. Markov, ``Spinto: a High-performance Solver for Energy Minimization in Ising Spin-glasses'' in Proc. Design Autom. and Test in Europe Conf. (DATE), pp. 160 - 165, Dresden, March 2010.
• H. Katebi and I. L. Markov, ``Large-scale Boolean Matching'' in Proc. Design Autom. and Test in Europe Conf. (DATE), pp. 771-776, Dresden, March 2010.
• D.-J. Lee and I. L. Markov, ``Contango: Integrated Optimizations for SoC Clock Networks'' in Proc. Design Autom. and Test in Europe Conf. (DATE), pp. 1468-1473, Dresden, March 2010.

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• J. A. Roy, N. Viswanathan, G.-J. Nam, C. J. Alpert and I. L. Markov, ``CRISP: Congestion Reduction by Iterated Spreading during Placement'' in Proc. Int'l. Conf. on Computer-Aided Design (ICCAD), pp. 357-362, November 2009.
• S. Krishnaswamy, I.L. Markov, J.P. Hayes, ``Improving Testability and Soft-Error Resilience through Retiming'' in Proc. Design Autom. Conf. (DAC), pp. 924-929, July 2009.
• K.-H. Chang, V. Bertacco, I. L. Markov, ``Customizing IP Cores for System-on-Chip Designs, Using Extensive External Don't-Cares'' in Proc. Design Autom. and Test in Europe (DATE), pp. 582-585, April 2009.

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• J.-S. Seo, I. L. Markov, D. Blaauw, D. Sylvester, ``On the Decreasing Significance of Large Standard Cells in Technology Mapping,'' in Proc. Int'l. Conf. on Computer-Aided Design (ICCAD) pp. 116-121, November 2008.
• J. A. Roy, F. Koushanfar and I. L. Markov, ``Circuit CAD Tools as a Security Threat'' Hardware-Oriented Security and Trust Workshop (HOST), pp. 68-69, Anaheim, CA, 2008.
• S. Krishnaswamy, I. L. Markov, J. P. Hayes, ``On the Role of Timing Masking in Reliable Logic Circuit Design'' Proc. Design Autom. Conf. (DAC), pp. 924-929, Anaheim, CA, 2008.
• P. T. Darga, K. A. Sakallah, I. L. Markov, ``Faster Symmetry Discovery using Sparsity of Symmetries'' Proc. Design Autom. Conf. (DAC), pp. 149-154, Anaheim, CA, 2008.
• J. A. Roy, F. Koushanfar, I. L. Markov, ``Protecting Bus-based Hardware IP by Secret Sharing,'' Proc. Design Autom. Conf. (DAC), pp. 846-851, Anaheim, CA, 2008.
• I. L. Markov and J. P. Hayes, ``Why Nanoscale Physics Favors Quantum Information'' Proc. VLSI Test Symposium (VTS), p. 107, San Deigo, CA, 2008.
• J. Hu, J. A. Roy, I. L. Markov, ``Sidewinder: A Scalable Wire Router Based on ILP'' Int'l Workshop on System-Level Interconnect Prediction (SLIP), pp. 73-80, Newcastle, England, 2008.
• M. D. Moffitt, J. A. Roy, I. L. Markov, ``The Coming of Age of (Academic) Global Routing'' Int'l Symposium on Physical Design (ISPD), pp. 148-155, Portland, Oregon, 2008.
• S. M. Plaza, I. L. Markov, and V. Bertacco, ``Optimizing Non-Monotonic Interconnect using Functional Simulation and Logic Restructuring,'' Int'l Symposium on Physical Design (ISPD), pp. 95-102, Portland, Oregon, 2008 (best paper award).
• K.-H. Chang, I. L. Markov, and V. Bertacco, ``Reap What You Sow: Spare Cells for Post.-Silicon Metal Fix'' Int'l Symposium on Physical Design (ISPD), pp. 103-110, Portland, Oregon, 2008.
• D. A. Papa, T. Luo, M. D. Moffitt, C. N. Sze, Z. Li, G.-J. Nam, C. J. Alpert and I. L. Markov, ``RUMBLE: An Incremental, Timing-driven, Physical-synthesis Optimization Algorithm'' Int'l Symposium on Physical Design (ISPD), pp. 2-9, Portland, Oregon, 2008.
• J. A. Roy, F. Koushanfar, I. L. Markov, ``EPIC: Ending Piracy of Integrated Circuits'' Proc. Design Autom. and Test in Europe (DATE), pp. 1069-1074, Munich, Germany, 2008.
• S. M. Plaza, I. L. Markov, and V. Bertacco ``Random Stimulus Generation using Entropy and XOR constraints'' Proc. Design Autom. and Test in Europe (DATE), pp. 664-669, Munich, Germany, 2008.

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• K.-H. Chang, I. Wagner, V. Bertacco, and I. L. Markov ``Automatic Error Diagnosis and Correction for RTL Designs'' Proc. High-Level Design Validation and Test workshop (HLDVT), pp. 65-72, Irvine, CA, November 2007.
• S. Krishnaswamy, S.M. Plaza, I.L.Markov, J.P.Hayes, ``Enhancing Design Robustness with Reliability-aware Resynthesis and Logic Simulation,'' Proc. Int'l Conf. on Computer-Aided Design (ICCAD), pp. 149-154, San Jose, CA, November 2007.
• K-H. Chang, I.L. Markov and V. Bertacco, ``Automating Post-Silicon Debugging and Repair'' Proc. Int'l Conf. on Computer-Aided Design (ICCAD), pp. 91-98, San Jose, CA, November 2007.
• J.A. Roy and I.L.Markov, ``High-performance Routing at the Nanometer Scale'' Proc. Int'l Conf. on Computer-Aided Design (ICCAD), pp. 496-502, San Jose, CA, November 2007.
• G.F. Viamontes, I.L. Markov and J.P. Hayes, ``Equivalence Checking of Quantum Circuits and States,'' Proc. Int'l Conf. on Computer-Aided Design (ICCAD) (quant-ph), pp. 69-74, San Jose, CA, November 2007.
• K.-H. Chang, D. A. Papa, I. L. Markov and V. Bertacco, ``InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization'' Proc. Int'l Symposium on Quality Electronic Design (ISQED), pp. 487-492, San Jose, CA, March 2007.
• K.-H. Chang, I. L. Markov and V. Bertacco, ``Safe Delay Optimization for Physical Synthesis'' (slides), Proc. Asia and South Pacific Design Automation Conf. (ASPDAC) pp. 628-633, Yokohama, Japan, January 2007.
• S. M. Plaza, K.-H. Chang, I. L. Markov and V. Bertacco, ``Node Mergers in the Presence of Don't Cares'' (slides) Proc. Asia and South Pacific Design Automation Conf. (ASPDAC), pp. 414-419, Yokohama, Japan, January 2007.
• K.-H. Chang, I. L. Markov and V. Bertacco, ``Fixing Design Errors with Counterexamples and Resynthesis'' (slides) Proc. Asia and South Pacific Design Automation Conf. (ASPDAC), pp. 944-949, Yokohama, Japan, January 2007.
• J. A. Roy and I. L. Markov, ``ECO-System: Embracing the Change in Placement'' (slides) Proc. Asia and South Pacific Design Automation Conf. (ASPDAC), pp. 147-152, Yokohama, Japan, January 2007.
• I. L. Markov, ``Almost-symmetries of Graphs'' (slides) Proc. International Symmetry Conference (ISC) pp. 60-70, Edinburgh, Scotland, January 2007.

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• M. D. Moffitt, A. N. Ng, I. L. Markov, M. E. Pollack, ``Constraint-driven Floorplan Repair'' (slides) Proc. Design Automation Conf. (DAC), pp. 1103-1108, San Francisco, CA, July 2006.
• R. Das, I. L. Markov, J. P. Hayes, ``On-Chip Test Generation Using Linear Subspaces'' (slides) Proc. European Test Symposium(ETS), pp. 111-117, Southampton, UK, May 2006.
• J. A. Roy, D. A. Papa, A. N. Ng, I. L Markov, ``Satisfying Whitespace Requirements in Top-down Placement'' , Proc. Int'l Symp. on Physical Design (ISPD), pp. 206-208, San Jose, CA, April 2006.
• J. A. Roy, J. F. Lu and I. L. Markov, ``Seeing the Forest and the Trees: Steiner Wirelength Optimization in Placement'' (slides) Proc. Int'l Symp. on Physical Design (ISPD), pp. 78-85, San Jose, CA, April 2006.
• A. N. Ng, I. L. Markov, R. Aggarwal and V. Ramachandran, ``Solving Hard Instances of Floorplacement'' (slides) Proc. Int'l Symp. on Physical Design (ISPD) (BPA nominee), pp. 170-177, San Jose, CA, April 2006.
• D. A. Papa, I. L. Markov and P. Chong, ``Utility of OpenAccess in Academic Research'' Proc. Asia and South Pacific Design Automation Conference (ASPDAC), pp. 440-441, Yokohama, Japan, January 2006.

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• K.-H. Chang, I. L. Markov and V. Bertacco, ``Post-Placement Rewiring and Rebuffering by Exhaustive Search For Functional Symmetries'' Proc. Int'l Conf. Computer-Aided Design (ICCAD), pp. 56-63, San Jose, CA, November 2005.
• K.-H. Chang, V. Bertacco and I. L. Markov, ``Simulation-based Bug Trace Minimization with BMC-based Refinement'' Proc. Int'l Conf. Computer-Aided Design (ICCAD), pp. 1045-1051, San Jose, CA, November 2005.
• S. Krishnaswamy, I. L. Markov and J. P. Hayes, ``Testing Logic Circuits for Transient Faults'' in Proc. IEEE Eur. Test Symp. (ETS), pp. 102-107, Tallin, Estonia, May 2005.
• J. A. Roy, D. A. Papa, S. N. Adya, H. H. Chan, J. F. Lu, A. N. Ng, I. L. Markov, ``Capo: Robust and Scalable Open-Source Min-cut Floorplacer'' Proc. Intl. Symposium on Physical Design (ISPD), pp. 224-227, San Francisco, April 2005.
• Zh. Xiu, D. A. Papa, P. Chong, A. Kuehlmann, Rob A. Rutenbar, Igor L. Markov, ``Early Research Experience with OpenAccess Gear: An Open Source Development Environment for Physical Design'' Proc. Intl. Symposium on Physical Design (ISPD), pp. 94-100, San Francisco, April 2005.
• H. H. Chan, S. N. Adya and I. L. Markov, ``Are Floorplan Representations Important in Digital Design?'' Proc. Intl. Symposium on Physical Design (ISPD), pp.129-136, San Francisco, April 2005.
• A. N. Ng and I. L. Markov, ``Toward High Quality Tools and Tool Flows Through High-Performance Computing'', Proc. Intl. Symp. on Quality Electronic Design (ISQED), pp. 22-27, San Jose, California, March 2005.
• S. Krishnaswamy, G. F. Viamontes, I. L. Markov and J. P. Hayes, ``Accurate Reliablity Evaluation and Enhancement via Probabilistic Transfer Matrices'', Proc. Design Automation and Test in Europe (DATE), pp. 282-287, Munich, Germany, March 2005 (best paper award).
• I. L. Markov and D. Maslov, ``Uniformly-switching Logic for Cryptographic Applications'' Proc. Design Automation and Test in Europe (DATE), Munich, Germany, pp. 432-433, March 2005.
• F. A. Aloul, A. Ramani, I. L. Markov and K. A. Sakallah, ``Dynamic Symmetry-Breaking for Improved Boolean Optimization'', Proc. Asia and South Pacific Design Autom. Conf. (ASPDAC) pp. 445-450, Shanghai, China, January 2005.
• V. V. Shende, I. L. Markov and S. S. Bullock, ``Synthesis of Quantum Logic Circuits'', Proc. Asia and South Pacific Design Autom. Conf. (ASPDAC) pp. 272-275, Shanghai, China, January 2005.

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• S. N. Adya, S. Chaturvedi, J. A. Roy, D. A. Papa and I. L. Markov, ``Unification of Partitioning, Placement and Floorplanning'' (slides) Intl. Conf. Computer-Aided Design (ICCAD), San Jose, CA, November 2004, pp. 550-557.
• P. T. Darga, M. H. Liffiton, K. A. Sakallah and I. L. Markov, ``Exploiting Structure in Symmetry Detection for CNF'' Proc. Design Autom. Conf. (DAC), San Diego, California, June 2004, pp. 530-534.
• Y. Oh, M. Mneimneh, Z. S. Andraus, K. A. Sakallah and I. L. Markov, ``AMUSE: A Minimally Unsatisfiable Subformula Extractor'' Proc. Design Autom. Conf. (DAC),(BPA nominee) San Diego, California, June 2004, pp. 518-523.
• A. B. Kahng, I. L. Markov and S. Reda, ``On Legalization of RowBased Placements'' Proc. Great Lakes Symp. on VLSI (GLSVLSI), Boston, Massachusetts, April 2004, pp. 214-219.
• H. H. Chan and I. L. Markov, ``Practical Slicing and Nonslicing Block-Packing without Simulated Annealing'' Proc. Great Lakes Symp. on VLSI (GLSVLSI), Boston, Massachusetts, April 2004, pp. 282-287.
• D. A. Papa, S. N. Adya and I. L. Markov, ``Constructive Benchmarking for Placement'' Proc. Great Lakes Symp. on VLSI (GLSVLSI), Boston, Massachusetts, April 2004, pp. 113-118.
• V. V. Shende, I. L. Markov and S. S. Bullock, ``Finding Small Two-qubit Circuits'' Proc. SPIE vol. 5436 (Conf. on Quantum Information and Computation), pp. 348-359, Orlando, Florida, April 2004.
• G. F. Viamontes, I. L. Markov and J. P. Hayes, ``Graph-based Simulation of Quantum Computation in the State-vector and Density-matrix Representation,'' Proc. SPIE vol. 5436 (Conf. on Quantum Information and Computation), pp. 285-296. Orlando, Florida, April 2004.
• A. Ramani, F. A. Aloul, I. L. Markov and K. A. Sakallah, ``Breaking Instance-Independent Symmetries in Exact Graph Coloring'' Proc. Design Autom. and Test in Europe (DATE), Paris, France, February 2004, pp. 324-329.
• V. V. Shende, I. L. Markov and S. S. Bullock, ``Smaller Two-Qubit Circuits for Quantum Communication and Computation'' Proc. Design Autom. and Test in Europe (DATE), Paris, France, February 2004, pp. 980-985.
• A. B. Kahng, I. L. Markov and S. Reda, ``Boosting: Min-Cut Placement with Improved Signal Delay'' Proc. Design Autom. and Test in Europe (DATE), Paris, France, February 2004, pp. 1098-1103.
• G. F. Viamontes, I. L. Markov and J. P. Hayes, ``High-performance QuIDD-based Simulation of Quantum Circuits,'' Proc. Design Autom. and Test in Europe (DATE), Paris, France, February 2004, pp. 1354-1359.
• F. A. Aloul, A. Ramani, I. L. Markov and K. A. Sakallah, ``Symmetry-Breaking for Pseudo-Boolean Formulas'' Proc. Asia and South Pacific Design Autom. Conf. (ASPDAC), Yokohama, Japan, January 2004, pp. 884 - 887.

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• S. N. Adya, I. L. Markov and P. G. Villarrubia, ``On Whitespace and Stability in Physical Synthesis'' in Proc. Intl. Conf. on Computer-Aided Design(ICCAD) San Jose, November 2003, pp. 311-318.
• F. A. Aloul, I. L. Markov, and K. A. Sakallah, ``Efficient Symmetry Breaking for Boolean Satisfiability'' in Proc. Intl. Joint Conf. on Artificial Intelligence (IJCAI), pp. 271-282, Acapulco, Mexico, August 2003.
• A. Ramani and I. L. Markov, ``Combining Two Local Search Approaches to Hypergraph Partitioning,'' Proc. Intl. Joint Conf. on Artificial Intelligence (IJCAI), pp. 1546 - 1548, Acapulco, Mexico, August 2003.
• S. Bullock and I. L. Markov, ``An Arbitrary Two-qubit Computation In 23 Elementary Gates Or Less'' (.ppt) Proc. ACM/IEEE Design Automation Conf. (DAC), pp. 324-329, Anaheim, CA, June 2003 (BPA nominee).
• F. A. Aloul, K. A. Sakallah, and I. L. Markov, ``Shatter: Efficient Symmetry-Breaking for Boolean Satisfiability'' (.ppt) Proc. ACM/IEEE Design Automation Conf. (DAC), pp. 836-839, Anaheim, CA, June 2003.
• K. N. Patel, J. P. Hayes and I. L. Markov, ``Fault Testing for Reversible Circuits'' Proc. IEEE VLSI Test Symposium (VTS), pp. 410-416, Napa, CA, April 2003.
• F. A. Aloul, I. L. Markov and K. A. Sakallah, ``FORCE: A Fast and Easy-To-Implement Variable-Ordering Heuristic'' Proc. Great Lakes Symp. on VLSI (GLSVLSI), pp. 116-119, Washington, DC, 2003.
• S. N. Adya, M. Yildiz, I. L. Markov, P. G. Villarrubia, P. N. Parakh and P. H. Madden, ``Benchmarking For Large-Scale Placement and Beyond'' (.ppt) Proc. Intl. Symp. on Physical Design (ISPD), pp. 95-103, Monterey, CA, April 2003.
• K. N. Patel and I. L. Markov, ``Error-Correction and Crosstalk Avoidance in DSM Busses,'' Proc. Intl. Workshop on System-Level Interconnect Prediction (SLIP) pp. 9-14, Monterey, CA, April 2003.
• A. B. Kahng and I. L. Markov, ``The Impact of Interoperability on CAD-IP Reuse: An Academic Viewpoint'', in Proc. Intl. Symp. on Quality Electronic Design (ISQED), pp. 208-213, San Jose, CA, March, 2003.
• S. N. Adya and I. L. Markov, ``Improving Min-cut Placement for VLSI Using Analytical Techniques,'' in Proc. IBM ACAS Conference, pp. 55-62, Austin, TX, February, 2003.
• G. F. Viamontes, M. Rajagopalan, I. L. Markov and J. P. Hayes, ``Gate-level Simulation of Quantum Circuits'' Proc. Asia and South-Pacific Design Automation Conf. (ASPDAC), pp. 295-301, Kitakyushu, Japan, January 2003.

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• F. A. Aloul, A. Ramani, I. L. Markov and K. A. Sakallah, ``Generic ILP versus Specialized 0-1 ILP: an Update'' in Proc. ACM/IEEE Intl. Conf. Comp.-Aided Design (ICCAD), pp. 450-457, November 2002.
• V. V. Shende, A. K. Prasad, I. L. Markov and J. P. Hayes, ``Reversible Logic Circuit Synthesis'' in Proc. ACM/IEEE Intl. Conf. Comp.-Aided Design (ICCAD), pp. 353-360, November 2002.
• F. A. Aloul, I. L. Markov and K. A. Sakallah, ``Improving the Efficiency of Circuit-to-BDD Conversion by Gate and Input Ordering'' in Proc. ACM/IEEE Intl. Conf. Computer Design (ICCD), pp. 64-69, September 2002, Freiburg, Germany.
• G. F. Viamontes, M. Rajagopolan, I. L. Markov and J. P. Hayes, ``High-Performance Simulation of Quantum Computation Using QuIDDs'' Proc. Quantum Communication, Measurement and Computation (QCMC) June 2002, pp. 311-314.
• F. A. Aloul, A. Ramani, I. L. Markov and K. A. Sakallah, ``Solving Difficult SAT Instances In The Presence of Symmetry'' slides: .ppt in Proc. ACM/IEEE Design Automation Conf. (DAC), pp. 731-736, June 2002.
• S. N. Adya and I. L. Markov, ``Consistent Placement of Macro-blocks Using Floorplanning and Standard-Cell Placement'' in Proc. ACM/IEEE Intl. Symp. on Physical Design (ISPD), pp. 12-17, April 2002.
• A. B. Kahng, S. Mantik and I. L. Markov, ``Min-max Placement For Large-scale Timing Optimization'' in Proc. ACM/IEEE Intl. Symp. on Physical Design (ISPD), pp. 143-148, April 2002.
• A. B. Kahng and I. L. Markov, ``Analytical Minimization of Signal Delays in VLSI Placement'' Proc. 3rd Annual IBM ACAS Conference, pp. 62-68, February, 2002.

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• F. A. Aloul, I. L. Markov and K. A. Sakallah ``Faster SAT and Smaller BDDs via Common Function Structure'' slides: (.ppt) in Proc. ACM/IEEE Intl. Conf. Computer-Aided Design (ICCAD), pp. 443-448, 2001.
• S. N. Adya and I. L. Markov, ``Fixed-outline Floorplanning Through Better Local Search'' slides: (.ppt) in Proc. ACM/IEEE Intl. Conf. Computer Design (ICCD), pp. 328-334, 2001.

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• A. E. Caldwell, Y Cao, A. B. Kahng, F. Koushanfar, H. Lu, I. L. Markov, M. R. Oliver, D. Stroobandt and D. Sylvester, "GTX: The MARCO GSRC Technology Extrapolation System" slides(.ppt) in Proc. ACM/IEEE Design Automation Conf. (DAC), Los Angeles, June 2000, pp. 693-698.
• A. E. Caldwell, A. B. Kahng and I. L. Markov, "Can Recursive Bisection Alone Produce Routable Placements?" , slides(.ppt) in Proc. ACM/IEEE Design Automation Conf. (DAC), Los Angeles, June 2000, pp. 477-482.
• O. Coudert, I. L. Markov, C. Meinel and E. Sentovich, ``Web-based frameworks to enable CAD R&D'', in Proc. ACM/IEEE Design Automation Conf. (DAC), Los Angeles, June 2000, p. 711-712.
• A. A. Kennings and I. L. Markov, "Analytical Minimization of Half-Perimeter Wirelength" (.slides) in Proc. IEEE/ACM Asia and South Pacific Design Automation Conf. (ASPDAC), Jan. 2000, pp. 179-184 (BPA nominee).
• A. E. Caldwell, A. B. Kahng, and I. L. Markov, "Improved Algorithms for Hypergraph Bipartitioning" (.slides) in Proc. IEEE/ACM Asia and South Pacific Design Automation Conf. (ASPDAC), Jan. 2000, pp. 661-666.

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• A. E. Caldwell, A. B. Kahng, A. A. Kennings and I. L. Markov, "Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting" Proc. ACM/IEEE Design Automation Conf. (DAC), June 1999, pp. 349-354.
• A. E. Caldwell, A. B. Kahng and I. L. Markov, "Hypergraph Partitioning With Fixed Vertices" Proc. ACM/IEEE Design Automation Conf. (DAC), June 1999, pp. 355-359.
• A. E. Caldwell, A. B. Kahng and I. L. Markov, "Optimal Partitioners and End-Case Placers for Standard-Cell Layout" (slides) Proc. ACM Intl. Symp. on Physical Design (ISPD), April 1999, pp. 90-96.
• C. J. Alpert, A. E. Caldwell, A. B. Kahng and I. L. Markov, "Partitioning With Terminals: A `New' Problem and New Benchmarks" (slides) Proc. ACM Intl. Symp. on Physical Design (ISPD), April 1999, pp. 151-157.
• R. Baldick, A. B. Kahng, A. Kennings and I. L. Markov, "Function Smoothing with Applications to VLSI Layout" (slides) Proc. IEEE/ACM Asia and South Pacific Design Automation Conf. (ASPDAC), Jan. 1999, pp. 225-228. (BPA nominee).

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• A. E. Caldwell, A. B. Kahng and I. L. Markov, "Relaxed Partitioning Balance Constraints in Top-Down Placement" (slides) Proc. IEEE ASIC Conference, September 1998, pp. 229-232.  
• A. B. Kahng, J. Lach, W. H. Mangione-Smith, S. Mantik, I. L. Markov, M. Potkonjak, P. Tucker, H. Wang and G. Wolfe, "Watermarking Techniques for Intellectual Property Protection" Proc. ACM/IEEE Design Automation Conference (DAC), San Francisco, June 1998, pp. 776-781. 
• A. B. Kahng, S. Mantik, I. L. Markov, M. Potkonjak, P. Tucker, H. Wang and G. Wolfe, "Robust IP Watermarking Methodologies for Physical Design" (slides) Proc. ACM/IEEE Design Automation Conference (DAC), San Francisco, June 1998, pp. 782-787. 
• A. E. Caldwell, A. B. Kahng, S. Mantik, I. L. Markov and A. Zelikovsky, "On Wirelength Estimations for Row-Based Placement" (slides) Proc. ACM/IEEE Intl. Symp. on Physical Design (ISPD), Monterey, April 1998, pp. 4-11. 
• A. E. Caldwell, A. B. Kahng, S. Mantik and I. L. Markov, "Implications of Area-Array I/O for Row-Based Placement Methodology" (slides) Proc. IEEE Symp. on IC/Package Design Integration (IPDI), Santa Cruz, February 1998, pp. 93-98. 

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• C. J. Alpert, T. Chan, D. J.-H. Huang, I. Markov and K. Yan "Quadratic Placement Revisited" (slides) Proc. ACM/IEEE Design Automation Conference (DAC), Anaheim, June 1997, pp. 752-757.  (BPA nominee)
• C. J. Alpert, T. Chan, D. J. Huang, A. B. Kahng, I. Markov, P. Mulet and K. Yan, "Faster Minimization of Linear Wirelength for Global Placement" (slides) Proc. ACM/IEEE Intl. Symp. on Physical Design (ISPD), Napa, April 1997, pp. 4-11.

Invited talks, tutorials and discussion panels (w/o proceedings)

1. I. L. Markov, ``Limits to Fundamental Computations'', (Mentor Graphics, Berkeley, University of Toronto, Stanford) 2013-2014.
2. I. L. Markov, ``Embedded Security and the Three Little Pigs,'' panel on Embedded Security at DAC, San Diego, CA, June 2011
3. I. L. Markov, ``Parallelization by SimPLification: A Case Study in VLSI Placement,'' Int'l Workshop on Parallel Algorithms and Parallel Architectures (PAPA), San Diego, CA, June 2011
4. I. L. Markov, ``SimPL: an Effective Algorithm for Placement,'' Michigan Technological University, April 2011
5. I. L. Markov, ``Recent Research on Clock Network Synthesis,'' Intel, Portland, OR, March 2011.
6. M.-C. Kim, D.-J. Lee and I. L. Markov, ``SimPL: an Effective Algorithm for Placement'', Mentor Graphics, San Jose, CA, November 2010
7. M.-C. Kim, D.-J. Lee and I. L. Markov, ``SimPL: an Effective Algorithm for Placement'', Synopsys, Mountain View, CA, November 2010
8. I. L. Markov, Natonal Science Foundation, Washington, DC, July 2009.
9. I. L. Markov, ``Recent Work on Bug Repair,'' Calypto, San Jose, CA, July 2008.
10. I. L. Markov, ``Recent Work on Physical Synthesis,'' Xilinx, San Jose, CA, July 2008.
11. I. L. Markov, ``The Many Shades of Post-Silicon Debug,'' Intel Research Symposium, Haifa, Israel, June 2008.
12. I. L. Markov and J. P. Hayes, Special Session on Quantum Computing, VTS, San Diego, CA, April 2008.
13. I. L. Markov, ``On Libraries, Reuse and the Value of EDA Software,'' EDP, Monterey, CA, April 2008.
14. I. L. Markov, ``Automating Post-silicon Debugging'', Intel, Santa Clara, CA, March 2008.
15. I. L. Markov, ``Why Study Quantum Circuits and What They are Good For,'' SASIMI, Sapporo, Japan, October 2007.
16. I. L. Markov, ``New Standards without New Parsers'', workshop on Electronic Design Processes (EDPS), Monterey, CA, April 2007.
17. I. L. Markov, ``ECO-system: Embracing the Change in Placement'', IBM Austin Research Laboratory, March 2007.
18. I. L. Markov, ``Post-silicon Debugging'', Rice University, March 2007 .
19. D. A. Papa, K.-H. Chang, I. L. Markov, and V. Bertacco, ``Fast Simulation and Equivalence Checking Using OpenAccess'' the Open Access conference (OA), San Jose, CA, November 2006.
20. I. L. Markov, ``Seeing the Forrest and the Trees: Steiner Optimization in Placement'', UT Austin, May 2006.
21. J. A. Roy, D. A. Papa, J. F. Lu, A. N. Ng, I. L. Markov, ``Tool Development For Multi-Million Gate Designs'' workshop on Electronic Design Processes, 2005.
22. I. L. Markov et al., ``Handling Symmetries in Computational Fields'', discussion panel at SymCon 2004.
23. I. L. Markov, ``Floorplacement'', invited talk at a one-day research symposium organized by Intel Corp. in Haifa, Israel, July 2004.
24. I. L. Markov, ``Handling Structure in Boolean Satisfiability'', a 3-lecture tutorial at a summer school on Symmetries in Constraint-Satisfaction Problems at St. Andrews, Scotland, June 2004.
25. S. N. Adya and I. L. Markov, ``Unification of Placement and Floorplanning'', Synplicity Inc., Sunnyvale, CA, May 2004.
26. I. L. Markov, ``Simulation and Synthesis of Quantum Circuits'' Theory Seminar, Columbia University, CS Department, March 2004.
27. I. L. Markov, ``Simulation and Synthesis of Quantum Circuits'' Distinguished Talk in Quantum Information Processing, National Institute of Standards(NIST), January 2004.
28. I. L. Markov, ``Symmetry-breaking for Boolean Satisfiability and 0-1 ILP,'' Electronic Systems Seminar, UC Berkeley, November 2003.
29. I. L. Markov, ``Symmetry-breaking for Boolean Satisfiability,'' Theory Seminar, Universita Roma I, La Sapienza , May 2003.
30. J. P. Hayes and I. L. Markov, ``Simulation, Synthesis and Testing of Quantum Circuits'' (.ppt), DARPA QuIST annual research review, Beverly Hills, CA, June 2003.
31. P. Kudva and I. L. Markov, ``Benchmarking For Physical Synthesis'' (.ppt), IWLS, Laguna Beach, CA, May 2003
32. I. L. Markov, ``Bookshelf.EXE'' (slides) GSRC Workshop, Pittsburg, PA, Dec 2002.
33. I. L. Markov and J. P. Hayes, ``Simulation and Synthesis of Quantum Circuits'' (.ppt), DARPA QuIST annual research review, Cambridge, MA, Sept 2002.
34. I. L. Markov, ``Bookshelf.EXE: Executable Extensions to the GSRC Bookshelf'', (slides) The GSRC Symposium, New Orleans, LA, June 2002.
35. I. L. Markov and P. G. Villarrubia, ``Lazy Timing-Driven Placement'', IBM Annual All-site Meeting, Fishkill, NY, April, 2001.
36. I. L. Markov, ``Large-scale Optimization in VLSI CAD'', CAD Seminar, UC Berkeley, November 2000
37. A. E. Caldwell, A. B. Kahng and I. L. Markov, ``CAD-IP Reuse via the Bookshelf for Fundamental VLSI CAD Algorithms'', (.ppt), (.ps), (), Proc. ACM/IEEE Design Automation Conf., Los Angeles, June 2000.
38. I. L. Markov ``The MARCO/GSRC Bookshelf For Fundamental VSLI CAD Algorithms'' (ppt) The Gigascale Silicon Research Center, Annual Review, San Jose, Dec 9, 1999;
39. A. B. Kahng, A. E. Kennings, I. L. Markov, "Effective Optimization Strategies for Large-scale Placement", Sixth SIAM Conference on Optimization (.ps), Minisymposium on Optimization in Circuit Placement for VLSI , Atlanta, Georgia, May, 1999.

Conference and Workshop Presentations (w/o proceedings)

1. D. MacLennan, P. Xie, A. Segavac, and I.L. Markov, ``Matching Subcircuits Macroblocks,'' IWLS, San Francisco, CA 2014.
2. K.-H. Chang, H.-Z. Chou, I. L. Markov, ``Improving At-speed Testability at Early Design Stages,'' IWLS, La Jolla, CA 2011.
3. M.-C. Kim, D.-J. Lee, I. L. Markov, ``Chop-SPICE: An Efficient SPICE Simulation Technique For Buffered RC Trees,'' TAU, Santa Barbara, CA 2011
4. D. A. Papa, S. Krishnaswamy, I. L. Markov, ``SPIRE: A Retiming-based Global Physical Synthesis Transformation System,'' IWLS, Irvine, CA 2010.
5. D. A. Papa, M. D. Moffitt, C. J. Alpert and I. L. Markov, ``Bounded Transactional Timing Analysis,'' TAU, San Francisco, CA 2010.
6. H. Garcia and I. L. Markov, ``High-performance Algorithms for Energy Minimization in Ising Spin-glasses,'' IWLS, Berkeley 2009.
7. S. Yamashita and I. L. Markov, ``Adaptive Equivalence-checking for Quantum Circuits,'' Int'l Reed-Muller Workshop (RM), Okinawa, Japan, 2009.
8. K.-H. Chang, V. Bertacco, I. L. Markov, A. Mishchenko, ``Synthesis with External Don't-Cares Using Shannon Entropy and Craig Interpolation,'' IWLS, Lake Tahoe, CA, 2008.
9. J.-S. Seo, I. L. Markov, D. Blaauw, D. Sylvester, ``On the Decreasing Significance of Large Standard Cells in Technology Mapping,'' IWLS, Lake Tahoe, CA, 2008.
10. S. Plaza, I. L. Markov, V. Bertacco, ``Low-latency SAT Solving on Multicore Processors with Priority Scheduling and XOR Partitioning,'' IWLS, Lake Tahoe, CA, 2008.
11. S. Yamashita, I. L. Markov, ``Equivalence-checking for Reversible Circuits'' IWLS, Lake Tahoe, CA, 2008.
12. D. Chatterjee, T. W. Manikas, and I. L. Markov, ``COOLER- A Fast Multiobjective Fixed-outline Thermal Floorplanner,'' Austin Conference on Integrated Systems and Circuits (ACISC), Austin, TX 2008.
13. K.-H. Chang, I. L. Markov, and V. Bertacco, ``Automating Post-Silicon Debugging and Repair'' IWLS, San Diego, CA, 2007.
14. K.-H. Chang, I. Wagner, V. Bertacco, and I. L. Markov, ``Automatic Error Diagnosis and Correction for RTL Designs'' IWLS, San Diego, CA, 2007.
15. S. Krishnaswamy, S. M. Plaza, I. L. Markov, and J. P. Hayes, ``Reliability-aware Synthesis using Logic Simulation'' IWLS, San Diego, CA, 2007.
16. S. M. Plaza, I. L. Markov, and V. Bertacco, ``Automatic Coverage Analysis and Refinement using Entropy and Uniformly-Randomized SAT'' IWLS, San Diego, CA, 2007.
17. K.-H. Chang, I. L. Markov, and V. Bertacco, ``Fast Verification of Retiming'' IWLS, San Diego, CA, 2007.
18. S. Krishnaswamy, S. M. Plaza, I. L. Markov, and J. P. Hayes, ``AnSER: A Lightweight Reliability Evaluator for use in Logic Synthesis'' IWLS, San Diego, CA, 2007.
19. K.-H. Chang, D. A. Papa, I. L. Markov and V. Bertacco, ``Fast Simulation and Equivalence Checking Using OAGear'' IWLS, pp. 270-271, Denver, CO, June 2006.
20. K.-H. Chang, I. L. Markov and V. Bertacco, ``Keeping Physical Synthesis Safe and Sound'', IWLS, pp. 86-93, Denver, CO, June 2006.
21. S. Krishnaswamy, I. L. Markov, J. P. Hayes, ``When Are Multiple Gate Errors Significant in Logic Circuits?'' System Effects of Logic Soft Errors (SELSE), Urbana-Champaign, IL 2006.
22. I. L. Markov and Y. Shi, ``Simulating quantum computation by contracting tensor networks'', Quantum Information and Computation (QIP), (quant-ph) Paris, France 2006
23. I. L. Markov, ``Algebraic Structure Helps in Finding and Using Almost-Symmetries'', Symmetries in Constraints (SymCon), Sitges, Spain 2005.
24. Y. Oh, E. Ernst, K. A. Sakallah, I. L. Markov, ``Constructive Logic and Layout Synthesis Does Not Work'', IWLS, pp. 367-374, Lake Arrowhead, CA, June 2005.
25. K.-H. Chang, I. L. Markov, V. Bertacco, ``Post-Placement Rewiring by Exhaustive Search for Functional Symmetries'' IWLS, pp. 469-476, Lake Arrowhead, CA, June 2005.
26. A. Ramani and I. L. Markov, ``Automatically Exploiting Symmetries in Constraint Programming'' Symmetries in Constraints (SymCon) Toronto 2004.
27. K. M. Svore, A. W. Cross, A. V. Aho, I. L. Chuang, I. L. Markov, "Toward a software architecture for quantum computing design tools" Workshop on Quantum Programming Languages, July 2004, Turku, Finland.
28. G. F. Viamontes, I. L. Markov and J. P. Hayes, ``Is Quantum Search Practical?'' (slides) IWLS, Temecula Creek CA, June 2004, pp. 478-485.
29. K. N. Patel, I. L. Markov and J. P. Hayes, ``Efficient Synthesis of Linear Reversible Circuits'' (slides) IWLS, Temecula Creek CA, June 2004, pp. 470-477.
30. J. A. Roy, I. L. Markov and V. Bertacco, ``Restoring Circuit Structure from SAT Instances'' (slides) IWLS, Temecula Creek CA, June 2004 , pp. 361-368.
31. H. H. Chan and I. L. Markov, ``Symmetries in Rectangular Block-Packing'' Intl. Workshop on Symmetry in Constraint-Satisfaction Problems (SymCon), 2003, pp. 27-40.
32. F. A. Aloul, A. Ramani, I. L. Markov and K. A. Sakallah ``Symmetry-Breaking for Pseudo-Boolean Formulas'' Intl. Workshop on Symmetry in Constraint-Satisfaction Problems (SymCon), 2003, pp. 1-12.
33. K. N. Patel, I. L. Makov, and J. P. Hayes, ``Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models'' (.ppt) IWLS, pp. 59-64, Laguna Beach, CA, May 2003.
34. I. L. Markov, ``An Introduction to Reversible Circuits'' (.ppt), IWLS, Laguna Beach, CA, May 2003 (invited)
35. J. A. Roy and I. L. Markov, ``On Sub-optimality and Scalability of Logic Synthesis Tools'' (.ppt) IWLS, Laguna Beach, CA, May 2003.
36. V. V. Shende, A. K. Prasad, K. N. Patel, I. L. Markov, and J. P. Hayes (.ppt) ``Scalable Simplification of Reversible Logic Circuits,'' IWLS, Laguna Beach, CA, May 2003.
37. F. A. Aloul, I. L. Markov, K. A. Sakallah, ``Symmetry-breaking for Boolean Satisfiability: The Mysteries of Logic Minimization'' Intl. Workshop on Symmetry on Constraint Satisfaction Problems (SymCon), slides, paper, Ithaca, NY, Sept 2002, pp. 37-46.
38. V. V. Shende, A. K. Prasad, I. L. Markov and J. P. Hayes, ``Synthesis of Optimal Reversible Logic Circuits'', IWLS, slides, paper, New Orleans, LA, June 2002, pp. 125-130. Available online as http://xxx.lanl.gov/abs/quant-ph/0207001 .
39. F. A. Aloul, I. L. Markov, K. A. Sakallah, ``Efficient Gate and Input Ordering for Circuit-to-BDD Conversion'', slides, paper, IWLS, New Orleans, LA, June 2002, pp. 137-142.
40. D. B. Motter and I. L. Markov ``Overcoming Resolution-Based Lower Bounds for SAT Solvers'' slides IWLS, New Orleans, LA, June 2002, pp. 373-378.
41. F. A. Aloul, A. Ramani, I. L. Markov and K. A. Sakallah, ``PBS: A Pseudo-Boolean Solver and Optimizer", slides (.ppt ), , SAT, Cincinnati, OH, May 2002, pp. 346-353.
42. D. B. Motter and I. L. Markov, ``On Proof Systems Behind Efficient SAT Solvers'', slides (.ppt ), SAT, Cincinnati, OH, May 2002, pp. 206-213.
43. F. A. Aloul, A. Ramani, I. L. Markov and K. A. Sakallah, ``Solving Difficult SAT Instances In The Presence of Symmetry'', slides (.ppt ), SAT, Cincinnati, OH, May 2002, pp. 338-345.
44. D. B. Motter and I. L. Markov, ``A Breadth-First Search For Satisfiabiliy'', slides (.ppt ) ALENEX, San Francisco, CA, January 2002
45. F. A. Aloul, I. L. Markov and K. A. Sakallah ``MINCE: A Static Global Variable-Ordering for SAT and BDD'', IWLS, Lake Tahoe, CA, June 2001 sildes
46. I. L. Markov and P. G. Villarrubia, ``Methods for Top-Down Timing-Driven Placement'', 2nd IBM ACAS Conference, Austin, TX, February, 2001
47. A. E. Caldwell, A. B. Kahng and I. L. Markov, "Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist Partitioning", (slides) ACM/SIAM Workshop on Algorithm Engineering and Experimentation (ALENEX), Jan. 1999

Quantum Physics Abstracts @http://xxx.lanl.gov/ quant-ph

1. http://xxx.lanl.gov/abs/quant-ph/0207001
2. http://xxx.lanl.gov/abs/quant-ph/0208003
3. http://xxx.lanl.gov/abs/quant-ph/0211002
4. http://xxx.lanl.gov/abs/quant-ph/0302002
5. http://xxx.lanl.gov/abs/quant-ph/0303039
6. http://xxx.lanl.gov/abs/quant-ph/0308033
7. http://xxx.lanl.gov/abs/quant-ph/0308045
8. http://xxx.lanl.gov/abs/quant-ph/0309060
9. http://xxx.lanl.gov/abs/quant-ph/0401162
10. http://xxx.lanl.gov/abs/quant-ph/0403114
11. http://xxx.lanl.gov/abs/quant-ph/0404003
12. http://xxx.lanl.gov/abs/quant-ph/0405001
13. http://xxx.lanl.gov/abs/quant-ph/0406176
14. http://xxx.lanl.gov/abs/quant-ph/0511069
15. http://lanl.arxiv.org/abs/0705.0017
16. http://lanl.arxiv.org/abs/0707.3622
17. arXiv:0803.2316
18. arXiv:0909.4119
19. arXiv:0912.3912
20. arXiv:1110.2574

Technical Reports @UMich

1. F. A. Aloul, I. L. Markov and K. A. Sakallah, ``Faster SAT and Smaller BDDs via Common Function Structure'', CSE-TR-445-01, University of Michigan, December 2001.
2. A. Ramani and I. L. Markov, ``The FMSAT Satisfiability Solver: Hypergraph Partitioning Meets Boolean Satisfiability'', CSE-TR-448-02, University of Michigan, February 2002.
3. F. A. Aloul, I. L. Markov and K. A. Sakallah, ``Generic ILP versus Specialized 0-1 ILP: An Update'', CSE-TR-461-02.pdf, University of Michigan, August 2002.
4. F. A. Aloul, A. Ramani, Igor L. Markov and K. A. Sakallah, ``Solving Difficult Instances of Boolean Satisfiability in the Presence of Symmetry'' (), CSE-TR-463-02, University of Michigan, September 2002.
5. H. H. Chan and I. L. Markov, ``Practical Slicing and Non-slicing Block-Packing without Simulated Annealing'', CSE-TR-487-04, University of Michigan, December 2004.

Technical Reports @UCLA

1. C.J. Alpert, T. Chan, D.J.-H. Huang, I. Markov, and K. Yan, Quadratic Placement Revisited, TR 97-48, UCLA, UCLA Mathematics Department, September 1997
2. Charles J. Alpert, Tony F. Chan, Dennis J.-H. Huang, Andrew B. Kahng, Igor L. Markov, Pep Mulet, and Kenneth Yan, Faster Minimization of Linear Wirelength for Global Placement, TR 97-49, UCLA, Mathematics Department, September 1997

1. A. E. Caldwell, A. B. Kahng and I. L. Markov, "Optimal End-Case Partitioners and Placers for Standard-Cell Layout" TR-990013, March 1999.
2. A.E. Caldwell, A.B. Kahng and I.L. Markov, "Design and implementation of move-based partitioners" TR-990015, March 1999.
3. A.A. Kennings and I.L. Markov, "Analytic Placement of Hypergraphs - I" TR-990020, March 1999.
4. A. E. Caldwell and I. L. Markov, "Hierarchical Whitespace Allocation", TR-200002, January 2000.