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Currently, the major topic of my research is about exploring the new capabilities of terahertz electronics. Basically, it includes:

The following projects are some examples:


A 210GHz Efficient Compact Oscillator with 10.6% Tuning Range

Low-cost and effective signal generation above 200GHz is very chanllenging. For a millimeter-wave or terahertz system, a high power high efficient source with wide tuning range and good phase noise is very critical. A small physical size is also important to reduce on-chip area and interconnection loss. In this project, a 210GHz oscillator with more than 10% tuning range and more than 1mW is designed, which only occupies an area of 290*95 μm2.

210_Osc


A 320GHz Coherent Imaging Transceiver

Terahertz imaging has been gaining increasing attention for its emerging applications in security, biomedical and material characterization. Unfortunately, most previous imagers are based on incoherent direct detection, which causes low sensitivity due to the output droping quickly with input power, and as a result, need exceedingly high power sources for illumination. In this project, a 320GHz coherent imaging transceiver chipset is designed. In the transmitter chip, a 4 by 4 radiator array is inject-locked to an on-chip phase-locked loop to provide terahertz illumination. In the receiver chip, an 8-cell subharmonic mixing detector array is used to perform a coherent heterodyne detection to enhance the sensitivity. Using the PLL-based structure, this work demonstrates the first fully-integrated coherent terahertz imaging transceiver chipset on silicon.

340G_Imager


Before Cornell

Before joining Cornell, I worked in the Integrated Circuit Design Laboratory (ICD Lab), Fudan University, China, under the guidance of Prof. Zhiliang Hong. Below are some of my projectes:


A Low-Noise 10-GHz All-Digital Frequency Synthesizer

This is a low-noise 8.95~11GHz fractional-N all-digital frequency synthesizer with a spurious-free first-order noise-shaping time-to-digital converter (TDC) and a high-frequency-resolution digitally-controlled oscillator (DCO) . A meta-stability free phase detection architecture is proposed to solve the problem of meta-stability. Based on this meta-stability free phase detection, a specific technique is used to power down the high-speed counter as soon as the ADPLL is about to lock for power saving consideration. The ADPLL is fabricated with the TSMC 65nm CMOS Technology and the core area is 0.385mm2. With about 8.5μs locking time, the measured phase noise performance at 1MHz offset is -106.4dBc/Hz from a carrier of 10GHz. The ADPLL core consumes 17.52mW from a supply of 1V.

ADPLL


A Time-to-Digital Converter with an Equivalent 2x Time Amplification

This is a multi-path gated-ring oscillator based time-to-digital converter. To enhance the resolution of the TDC, a multi-path structure for the GRO is used to achieve a higher oscillation frequency and an input stage is also presented to equivalently amplify the input time difference with a gain of 2. The GRO based TDC circuit is fabricated with the TSMC 65nm CMOS technology and the core area is about 0.02mm2. According to the measurement results, the effective resolution of this circuit is better than 4.22ps under a 50MHz clock frequency. With a 1ns input range, the maximum clock frequency of this circuit is larger than 200MHz. Under a 1V power supply, with a 200~800ps input time difference, the measured power consumption is 1.24mW to 1.72mW at 50MHz clock frequency and 1.73mW to 2.20mW at 200MHz clock frequency.

GRO_TDC