Yiqun Zhang

I am a Ph.D candidate at the University of Michigan, Ann Arbor. My advisor is Prof. Dennis Sylvester and I also work closely with Prof. David Blaauw in the Michigan Integrated Circuits Lab . I received my B.S. in Electrical Engineering from Shanghai Jiaotong University and University of Michigan in 2013.

My research interests include low power/high performance digital integrated circuit design, error resilient circuit and hardware security.


VLSI systems must be built to tolerate unpredictable variations in operating temperature and voltage, variations in the manufacturing process, and transistor aging. My iRazor work proposed a new error-tolerant register design that currently achieves the smallest area overhead – only 3 additional transistors per bit.

iRazor has been validated by the implementation of a commercial chip design – the ARM Cortex-R4. We compared this adaptive approach against competing industrial techniques such as frequency binning, critical path monitors and canary circuits, and found that iRazor outperforms all techniques in terms of energy and performance.

A Reconfigurable In-Memory Cryptographic Processor: Recryptor proposes a new architecutre with in-memory and near-memory computing, to accelerates cryptographic primitives. This architecture occupies a middle-ground between dedicated ASICs and general-purpose microcontrollers.

Recryptor is integrated into a 32-bit ARM Cortex-M0, which can directly program the special memory bank. I evaluated a large range of cryptographic primitives, including hash functions and symmetric/asymmetric cryptography algorithms, and found that Recryptor achieves over 4.1× higher energy efficiency across crypto algorithms than the current state-of-the-art.

Advanced Encryption Standard (AES) is a widely-used block cipher algorithm for symmetric encryption in a wide range of applications. By analyzing the algorithm, I discovered a way to manipulate two internal steps to either eliminate storage registers or replace flip-flops with latches to save area. My proposed AES accelerator provides 50-500Mbps throughput across a range of voltages in just 4.3k µm2, achieving best-in-class area and energy efficiency.


Recryptor: A Reconfigurable In-Memory Cryptographic Cortex-M0 Processor for IoT
Y. Zhang, L. Xu, K. Yang, Q. Dong, S. Jeloka, D. Blaauw, D. Sylvester.
To appear in IEEE Symposium on VLSI Circuits (VLSI'17), June 2017. (Highlighted)

A 6×5×4 mm3 General Purpose Audio Sensor Node with a 4.7μW Audio Processing IC
M. Cho, S. Oh, S. Jeong, Y. Zhang, I. Lee, Y. Kim, L. Chuo, D. Kim, Q. Dong, Y. Chen, M. Lim, M. Daneman, D. Blaauw, D. Sylvester.
To appear in IEEE Symposium on VLSI Circuits (VLSI'17), June 2017.

A 0.6nJ -0.22/0.19°C inaccuracy temperature sensor using exponential sub-threshold oscillation dependence
K. Yang, Q. Dong W. Jung, Y. Zhang, M. Choi, D. Blaauw, D. Sylvester.
in IEEE International Solid-State Circuits Conference (ISSCC'17), Feb 2017.

A compact 446 Gbps/W AES accelerator for mobile SoC and IoT in 40nm
Y. Zhang, K. Yang, M. Saligane, D. Blaauw, D. Sylvester.
in IEEE Symposium on VLSI Circuits (VLSI'16), June 2016.

iRazor: 3-Transistor Current-Based Error Detection and Correction in an ARM Cortex-R4 Processor
Y. Zhang, M. Khayatzadeh, K. Yang, M. Saligane, N. Pinckney, M. Alioto, D. Blaauw, D. Sylvester.
in IEEE International Solid-State Circuits Conference (ISSCC'16), Feb 2016. (Highlighted)

All-digital SoC thermal sensor using on-chip high order temperature curvature correction
M. Saligane, M. Khayatzadeh, Y. Zhang, S. Jeong, D. Blaauw, D. Sylvester.
in Custom Integrated Circuits Conference (CICC'15), Sept 2015.

An Ultra-Low Power Fully Integrated Energy Harvester Based on Self-Oscillating Switched-Capacitor Voltage Doubler
W. Jung, S. Oh, S. Bang, Y. Lee, Z. Foo, G. Kim, Y. Zhang, D. Sylvester, D. Blaauw.
in IEEE Journal of Solid-State Circuits (JSSC), Dec 2014.



(ADI Design Contest, 1st Place link)

Designed a 1GS/s 7-bit low power, time interleaved Asynchronous ADC with analog calibration techniques for inter-channel mismatch.

Viterbi decoder

(AMD Design Contest, 2nd Place)

Designed a novel group-wise intra-loop pipelined add-compare-select unit, and a custom soft memory with low voltage design techniques.

Processor Design

Designed a 2-way superscalar R10k out-of-order processor with early branch resolution to hide branch mis-prediction penalty.


Implemented radix-2, 4, 8 algorithms both in and out of place in C on OpenMAX DL of Intel Architecture, and built third-party codes process for Google Chromium. (Cooperated with Intel)

Cache Design

Implemented load-store queue, pre-fetching and non-blocking cache to hide memory access latency.

Custom ALU

Implemented 64-bit sparse tree using Static OPL and self-calibrated clock scheme.

Contact Information.


1301 Beal Ave. Ann Arbor, MI, 48109, USA


zhyiqun [at] umich [dot] edu