**Journals**

[J16] C.-H. Chen, S. Song, and Z. Zhang, "An FPGA-based transient error simulator for resilient circuit and system design and evaluation," *IEEE Trans. Circuits Syst. II, Exp. Briefs*, vol. 62, no. 5, pp. 471-475, May 2015.

[J15] P. Knag, J. K. Kim, T. Chen, and Z. Zhang, "A sparse coding neural network ASIC with on-chip learning for feature extraction and encoding," *IEEE J. Solid-State Circuits*, vol. 50, no. 4, pp. 1070-1079, Apr. 2015.

[J14] Y. S. Park, Y. Tao, and Z. Zhang, "A fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating," *IEEE J. Solid-State Circuits*, vol. 50, no. 2, pp. 464-475, Feb. 2015.

[J13] Y.-P. Chen, D. Jeon, Y. Lee, Y. Kim, Z. Foo, I. Lee, N. Langhals, G. Kruger, H. Oral, O. Berenfeld, Z. Zhang, D. Blaauw, and D. Sylvester, "An injectable 64nW ECG mixed-signal SoC in 65nm for arrhythmia monitoring," *IEEE J. Solid-State Circuits*, vol. 50, no. 1, pp. 375-390, Jan. 2015.

[J12] C.-H. Chen, P. Knag, and Z. Zhang, "Characterization of heavy-ion-induced single-event effects in 65 nm bulk CMOS ASIC test chips," *IEEE Trans. Nucl. Sci.*, vol. 61, no. 5, pp. 2694-2701, Oct. 2014.

[J11] J. K. Kim, P. Knag, T. Chen, and Z. Zhang, "Efficient hardware architecture for sparse coding," *IEEE Trans. Signal Process.*, vol. 62, no. 16, pp. 4173-4186, Aug. 2014.

[J10] C.-H. Chen, D. Blaauw, D. Sylvester, and Z. Zhang, "Design and evaluation of confidence-driven error-resilient systems," *IEEE Trans. Very Large Scale Integr. (VLSI) Syst.*, vol. 22, no. 8, pp. 1727-1737, Aug. 2014.

[J9] D. Jeon, M. Henry, Y. Kim, I. Lee, Z. Zhang, D. Blaauw, and D. Sylvester, "An energy efficient full-frame feature extraction accelerator with shift-latch FIFO in 28nm CMOS," *IEEE J. Solid-State Circuits*, vol. 49, no. 5, pp. 1247-1284, May 2014.

[J8] Y. S. Park, D. Blaauw, D. Sylvester, and Z. Zhang, "Low-power high-throughput LDPC decoder using non-refresh embedded DRAM," *IEEE J. Solid-State Circuits*, vol. 49, no. 3, pp. 783-794, Mar. 2014.

[J7] P. Knag, W. Lu, and Z. Zhang, "A native stochastic computing architecture enabled by memristors," *IEEE Trans. Nanotechnol.*, vol. 13, no. 2, pp. 283-293, Mar. 2014.

[J6] D. Jeon, M. Seok, Z. Zhang, D. Blaauw, and D. Sylvester, "Design methodology for voltage-overscaled ultra-low-power systems," *IEEE Trans. Circuits Syst. II, Exp. Briefs*, vol. 59, no. 12, pp. 952-956, Dec. 2012.

[J5] J. K. Kim, J. A. Fessler, and Z. Zhang, "Forward-projection architecture for fast iterative image reconstruction in X-ray CT," *IEEE Trans. Signal Process.*, vol. 60, no. 10, pp. 5508-5518, Oct. 2012.

[J4] Z. Zhang, V. Anantharam, M. J. Wainwright, and B. Nikolic, "An efficient 10GBASE-T Ethernet LDPC decoder design with low error floors," *IEEE J. Solid-State Circuits*, vol. 45, no. 4, pp. 843-855, Apr. 2010.

[J3] L. Dolecek, Z. Zhang, V. Anantharam, M. J. Wainwright, and B. Nikolic, "Analysis of absorbing sets and fully absorbing sets of array-based LDPC codes," *IEEE Trans. Inf. Theory*, vol. 56, no. 1, pp. 181-201, Jan. 2010.

[J2] Z. Zhang, L. Dolecek, B. Nikolic, V. Anantharam, and M. J. Wainwright, "Design of LDPC decoders for improved low error rate performance: quantization and algorithm choices," *IEEE Trans. Commun.*, vol. 57, no. 11, pp. 3258-3268, Nov. 2009.

[J1] L. Dolecek, P. Lee, Z. Zhang, V. Anantharam, B. Nikolic, and M. Wainwright, "Predicting error floors of LDPC codes: deterministic bounds and estimates," *IEEE J. Sel. Areas Commun.*, vol. 27, no. 6, pp. 908-917, Aug. 2009.

**Conference Proceedings**

[C32] S. Lu, Z. Zhang, and M. Papaefthymiou, "1.32GHz high-throughput charge-recovery AES core with resistance to DPA attacks," in *Symp. VLSI Circuits*, Kyoto, Japan, Jun. 2015, pp. 246-247.

[C31] J. K. Kim, P. Knag, T. Chen, and Z. Zhang, "A 640M pixel/s 3.65mW sparse event-driven neuromorphic object recognition processor with on-chip learning," in *Symp. VLSI Circuits*, Kyoto, Japan, Jun. 2015, pp. 50-51.

[C30] C.-H. Chen, W. Tang, and Z. Zhang, "A 2.4mm2 130mW MMSE-nonbinary LDPC iterative detector-decoder for 4x4 256-QAM MIMO in 65nm CMOS," in *IEEE Int. Solid-State Circuits Conf.* (*ISSCC*), San Francisco, CA, Feb. 2015, pp. 338-339.

[C29] F. Sheikh, C.-H. Chen, D. Yoon, B. Alexandrov, K. Bowman, A. Chun, H. Alavi, and Z. Zhang, "3.2Gbps channel-adaptive configurable MIMO detector for multi-mode wireless communication," in *IEEE Workshop Signal Process. Syst.* (*SIPS*), Belfast, UK, Oct. 2014.

[C28] Y. S. Park, Y. Tao, S. Sun, and Z. Zhang, "A 4.68Gb/s belief propagation polar decoder with bit-splitting register file," in *Symp. VLSI Circuits*, Honolulu, HI, Jun. 2014, pp. 117-118.

[C27] J. K. Kim, P. Knag, T. Chen, and Z. Zhang, "A 6.67mW sparse coding ASIC enabling on-chip learning and inference," in *Symp. VLSI Circuits*, Honolulu, HI, Jun. 2014, pp. 61-62.

[C26] S. Gaba, P. Knag, Z. Zhang, and W. Lu, "Memristive devices for stochastic computing," in *IEEE Int. Symp. Circuits Syst.* (*ISCAS*), Melbourne, Australia, Jun. 2014, pp. 2592-2595.

[C25] T.-C. Ou, Z. Zhang, and. M. C. Papaefthymiou, "An 821MHz 7.9Gb/s 7.3pJ/b/iteration charge-recovery LDPC decoder," in *IEEE Int. Solid-State Circuits Conf.* (*ISSCC*), San Francisco, CA, Feb. 2014, pp. 462-463.

[C24] D. Jeon, Y.-P. Chen, Y. Lee, Y. Kim, Z. Foo, G. Kruger, H. Oral, O. Berenfeld, Z. Zhang, D. Blaauw, and D. Sylvester, "An implantable 64nW ECG-monitoring mixed-signal SoC for arrhythmia diagnosis," in *IEEE Int. Solid-State Circuits Conf.* (*ISSCC*), San Francisco, CA, Feb. 2014, pp. 416-417.

[C23] C.-H. Chen, K. Bowman, C. Augustine, Z. Zhang, and J. Tschanz, "Minimum supply voltage for sequential logic circuits in a 22nm technology," in *IEEE Int. Symp. Low Power Electron. Des.* (*ISLPED*), Beijing, China, Sep. 2013, pp. 181-186.

[C22] D. Jeon, Y. Kim, I. Lee, Z. Zhang, D. Blaauw, and D. Sylvester, "A low-power VGA full-frame feature extraction processor," in *IEEE Int. Conf. Acoust., Speech, Signal Process.* (*ICASSP*), Vancouver, Canada, May 2013, pp. 2726-2730.

[C21] C.-H. Chen, Y. Tao, and Z. Zhang, "Efficient in situ error detection enabling diverse path coverage," in *IEEE Int. Symp. Circuits Syst.* (*ISCAS*), Beijing, China, May 2013, pp. 773-776. (**Best Student Paper Award Finalist**)

[C20] Y. S. Park, Y. Tao, and Z. Zhang, "A 1.15Gb/s fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating," in *IEEE Int. Solid-State Circuits Conf.* (*ISSCC*), San Francisco, CA, Feb. 2013, pp. 422-423.

[C19] D. Jeon, Y. Kim, I. Lee, Z. Zhang, D. Blaauw, and D. Sylvester, "A 470mV 2.7mW feature extraction accelerator for micro-autonomous vehicle navigation in 28nm CMOS," in *IEEE Int. Solid-State Circuits Conf.* (*ISSCC*), San Francisco, CA, Feb. 2013, pp. 166-167.

[C18] J. K. Kim, J. A. Fessler, and Z. Zhang, "Perburbation-based error analysis of iterative image reconstruction algorithm for X-ray computed tomography," in *Int. Conf. Image Formation in X-Ray Computed Tomography*, Salt Lake City, UT, Jun. 2012, pp. 194-197.

[C17] Y. S. Park, D. Blaauw, D. Sylvester, and Z. Zhang, "A 1.6-mm2 38-mW 1.5-Gb/s LDPC decoder enabled by refresh-free embedded DRAM," in *Symp. VLSI Circuits*, Honolulu, HI, Jun. 2012, pp. 114-115.

[C16] Y. Tao, Y. S. Park, and Z. Zhang, "High-throughput architecture and implementation of regular (2, dc) nonbinary LDPC decoders," in *IEEE Int. Symp. Circuits Syst.* (*ISCAS*), Seoul, Korea, May 2012, pp. 2625-2628.

[C15] H. Li, Y. S. Park, and Z. Zhang, "Reconfigurable architecture and automated design flow for rapid FPGA-based LDPC code emulation," in *ACM Int. Symp. Field-Programmable Gate Arrays* (*FPGA*), Monterey, CA, Feb. 2012, pp. 167-170.

[C14] J. Wang, L. Dolecek, Z. Zhang, and R. Wesel, "Absorbing set spectrum approach for practical code design," in *IEEE Int. Symp. Inf. Theory* (*ISIT*), Saint Petersburg, Russia, Aug. 2011, pp. 2726-2730.

[C13] J. K. Kim, Z. Zhang, and J. A. Fessler, "Hardware acceleration of iterative image reconstruction for X-ray computed tomography," in *IEEE Int. Conf. Acoust., Speech, Signal Process.* (*ICASSP*), Prague, Czech Republic, May 2011, pp. 1697-1700.

[C12] M. Weiner, B. Nikolic, and Z. Zhang, "LDPC decoder architecture for high-data rate personal-area networks," in *IEEE Int. Symp. Circuits Syst.* (*ISCAS*), Rio de Janeiro, Brazil, May 2011, pp. 1784-1787. (Invited)

[C11] C.-H. Chen, Y. Kim, Z. Zhang, D. Blaauw, D. Sylvester, H. Naeimi, and S. Sandhu, "A confidence-driven model for error-resilient computing," in *Design, Autom. Test in Europe Conf.* (*DATE*), Grenoble, France, Mar. 2011.

[C10] L. Dolecek, J. Wang, and Z. Zhang, "Towards improved LDPC code designs using absorbing set spectrum properties," in *Int. Symp. Turbo Codes Iterative Inform. Process.* (*ISTC*), Brest, France, Sep. 2010, pp. 477-481.

[C9] Z. Zhang, L. Dolecek, P. Lee, V. Anantharam, M. J. Wainwright, B. Richards, and B. Nikolic, "Low error rate LDPC decoders," in *Asilomar Conf. Signals, Syst., Comput*., Pacific Grove, CA, Nov. 2009, pp. 1278-1282. (Invited)

[C8] Z. Zhang, V. Anantharam, M. J. Wainwright, and B. Nikolic, "A 47 Gb/s LDPC decoder with improved low error rate performance," in *Symp. VLSI Circuits*, Kyoto, Japan, Jun. 2009, pp. 286-287. (**Best Student Paper Award**)

[C7] Z. Zhang, L. Dolecek, B. Nikolic, V. Anantharam, and M. J. Wainwright, "Lowering LDPC error floors by postprocessing," in *IEEE Global Commun. Conf. * (*GLOBECOM*), New Orleans, LA, Nov. 2008.

[C6] P. Lee, L. Dolecek, Z. Zhang, V. Anantharam, B. Nikolic, and M. Wainwright, "Error floors in LDPC codes: fast simulation, bounds and hardware emulation," in *IEEE Int. Symp. Inf. Theory * (*ISIT*), Toronto, Canada, Jul. 2008, pp. 444-448.

[C5] Z. Zhang, R. Winoto, A. Bahai, and B. Nikolic, "Peak-to-average power ratio reduction in an FDM broadcast system," in *IEEE Workshop Signal Process. Syst.* (*SIPS*), Shanghai, China, Oct. 2007, pp. 25-30.

[C4] L. Dolecek, Z. Zhang, M. Wainwright, V. Anantharam, and B. Nikolic, "Evaluation of the low frame error rate performance of LDPC codes using importance sampling," in *IEEE Inf. Theory Workshop *(*ITW*), Tahoe City, CA, Sep. 2007, pp. 202-207.

[C3] L. Dolecek, Z. Zhang, V. Anantharam, M. Wainwright, and B. Nikolic, "Analysis of absorbing sets for array-based LDPC codes," in *IEEE Int. Conf. Commun.* (*ICC*), Glasgow, UK, Jun. 2007, pp. 6261-6268.

[C2] Z. Zhang, L. Dolecek, M. Wainwright, V. Anantharam, and B. Nikolic, "Quantization effects in low-density parity-check decoders," in *IEEE Int. Conf. Commun.* (*ICC*), Glasgow, UK, Jun. 2007, pp. 6231-6237.

[C1] Z. Zhang, L. Dolecek, B. Nikolic, V. Anantharam, and M. Wainwright, "Investigation of error floors of structured low-density parity-check codes by hardware emulation," in *IEEE Global Commun. Conf.* (*GLOBECOM*), San Francisco, CA, Nov. 2006. (**Best Student Paper Award Finalist**)

**Book Chapters**

[B2] S. Sun and Z. Zhang, "Design of high-performance error-correcting codes using FPGA," in *Reconfigurable Logic: Architecture, Tools and Applications*, P.-E. Gaillardon, Ed. Boca Raton, FL: CRC Press, 2015.

[B1] C.-H. Chen, P. Knag, and Z. Zhang, "Soft error resilient circuit design," in *VLSI: Circuits for Emerging Applications*, T. Wojcicki, Ed. Boca Raton, FL: CRC Press, 2014.

**Technical Reports**

[T2] Z. Zhang, "Design of LDPC decoders for improved low error rate performance," Ph.D. dissertation, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA, 2009.

[T1] Q. Zhu, Z. Zhang, A. Pinto, and A. L. Sangiovanni-Vincentelli, "On-chip networks modeling and simulation," Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, Technical Report EECS-2006-126, Oct. 2006.