Prof. Wei Lu
office : 2417-A EECS Building
regular office hours: MW 10:30-11:30am
phone : (734) 615-2306
fax : (734) 763-9324
email : firstname.lastname@example.org
This is a graduate level course aimed to provide students a comprehensive understanding on nanoelectronics, and covers both novel MOSFET device structures and emerging research device structures based on the bottom-up paradigm.
We plan to fill the gap between the fast pacing research in nanotechnology and the current graduate curricula which focus on conventional CMOS devices. We will begin by first performing an in-depth analysis of the device principles and factors that affect the performance of MOSFET, followed by discussions on the challenges and technological innovations (boosters) that are currently being developed to sustain the historical trend of transistor scaling. Following that, we will carry out a critical survey of emerging research devices that may drive technology beyond CMOS.
Topics include transistor device principles and scaling rules, high-k dielectrics, mobility enhancement factors, SOI devices, ballistic and single-electron devices, nanowires and nanotubes, and molecule and spin based devices.
Prerequisite: EECS 421 or permission by instructor.
|Announcements and handouts will be available on CTOOLS|