Conference Publications

    2014

  • "High-Radix On-chip Networks with Low-Radix Routers"
    Animesh Jain, Ritesh Parikh and Valeria Bertacco
    International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2014
    PDF File

  • "DiAMOND: Distributed Alteration of Messages for On-Chip Network Debug"
    Rawan Abdel-Khalek and Valeria Bertacco
    International Symposium on Networks-on-Chip (NoCs), Ferrara, Italy, September 2014
    PDF File
    Best Paper Award Finalist (2 finalists in conference)

  • "Power-Aware NoCs Through Routing and Topology Reconfiguration"
    Ritesh Parikh, Reetuparna Das and Valeria Bertacco
    Design Automation Conference (DAC), San Francisco, CA, June 2014
    PDF File

  • "Brisk and Limited-Impact NoC Routing Reconfiguration"
    Doowon Lee, Ritesh Parikh and Valeria Bertacco
    Design Automation and Test in Europe (DATE), Dresden, Germany, March 2014
    PDF File

  • "ArChiVED: Architectural Checking via Event Digests for High Performance Validation"
    Chang-Hong Hsu, Debapriya Chatterjee, Ronny Morad, Raviv Gal and Valeria Bertacco
    Design Automation and Test in Europe (DATE), Dresden, Germany, March 2014
    PDF File

    2013

  • "uDIREC: Unified Diagnosis and Reconfiguration for Frugal Bypass of NoC faults"
    Ritesh Parikh and Valeria Bertacco
    International Symposium on Microarchitecture (MICRO), Davis, CA, December 2013
    PDF File

  • "Hybrid Checking for Microarchitectural Validation of Processor Designs on Acceleration Platforms"
    Debapriya Chatterjee, Biruk Mammo, Doowon Lee, Raviv Gal, Ronny Morad, Amir Nahir, Avi Ziv and Valeria Bertacco
    International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2013
    PDF File

  • "Cobra: a Comprehensive Bundled-based Reliable Architecture"
    Andrea Pellegrini and Valeria Bertacco
    International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Samos, Greece, July 2013
    PDF File

  • "Machine Learning-based Anomaly Detection for Post-silicon Bug Diagnosis"
    Andrew DeOrio, Qingkun Li, Matthew Burgess and Valeria Bertacco
    Design Automation and Test in Europe (DATE), Grenoble, France, March 2013
    PDF File

  • "On the Use of GP-GPUs for Accelerating Compute-intensive EDA Applications"
    Valeria Bertacco, Debapriya Chatterjee, Nicola Bombieri, Franco Fummi, Sara Vinco, Anirudh Kaushik and Hiren Patel
    Design Automation and Test in Europe (DATE), Grenoble, France, March 2013
    PDF File

  • "Schnauzer: Scalable Profiling for Likely Security Bug Site"
    William Arthur, Biruk Mammo, Ricardo Rodriguez, Todd Austin and Valeria Bertacco
    International Symposium on Code Generation and Optimization (CGO), Shenzhen, China, February 2013
    PDF File

    2012

  • "SystemC simulation on GP-GPUs: CUDA vs. OpenCL"
    Nicola Bombieri, Sara Vinco, Valeria Bertacco and Debapriya Chatterjee
    International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Tampere, Finland, October 2012
    PDF File

  • "Functional Post-Silicon Diagnosis and Debug for Networks-on-Chip"
    Rawan Abdel-Khalek and Valeria Bertacco
    International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2012
    PDF File

  • "Bridging Pre- and Post-silicon Debugging with BiPeD"
    Andrew DeOrio, Jialin Li and Valeria Bertacco
    International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2012
    PDF File

  • "Viper: Virtual Pipelines for Enhanced Reliability"
    Andrea Pellegrini, Joseph Greathouse and Valeria Bertacco
    International Symposium on Computer Architecture (ISCA), Portland, OR, June 2012
    PDF File

  • "SAGA: SystemC Acceleration on GPU Architectures"
    Sara Vinco, Debapriya Chatterjee, Valeria Bertacco and Franco Fummi
    Design Automation Conference (DAC), San Francisco, CA, June 2012
    PDF File

  • "Checking Architectural Outputs Instruction-By-Instruction on Acceleration Platforms"
    Debapriya Chatterjee, Anatoly Koyfman, Ronny Morad, Avi Ziv and Valeria Bertacco
    Design Automation Conference (DAC), San Francisco, CA, June 2012
    PDF File

  • "Humans for EDA and EDA for Humans"
    Valeria Bertacco
    Design Automation Conference (DAC), San Francisco, CA, June 2012
    PDF File

  • "Comprehensive Online Defect Diagnosis in On-Chip Networks"
    Amirali Ghofrani, Ritesh Parikh, Saeed Shamshiri, Andrew DeOrio, Kwang-Ting Cheng and Valeria Bertacco
    VLSI Test Symposium (VTS), Maui, HI, April, 2012
    PDF File

  • "CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions"
    Andrea Pellegrini, Rob Smolinski, Lei Chen, Xin Fu, Siva Kumar Sastry Hari, Junhao Jiang, Sarita Adve, Todd Austin and Valeria Bertacco
    Design Automation and Test in Europe (DATE), Dresden, Germany, March 2012
    PDF File

  • "Approximating Checkers for Simulation Acceleration"
    Biruk Mammo, Debapriya Chatterjee, Dmitry Pidan, Amir Nahir, Avi Ziv, Ronny Morad and Valeria Bertacco
    Design Automation and Test in Europe (DATE), Dresden, Germany, March 2012
    PDF File

    2011

  • "Formally Enhanced Runtime Verification to Ensure NoC Functional Correctness"
    Ritesh Parikh and Valeria Bertacco
    International Symposium on Microarchitecture 2011 (MICRO), Porto Alegre, Brazil, December 2011
    PDF File

  • "Simulation-based Signal Selection for State Restoration in Silicon Debug"
    Debapriya Chatterjee, Calvin McCarter and Valeria Bertacco
    International Conference on Computer-Aided Design (ICCAD), San Jose, CA,November 2011
    PDF File

  • "Post-Silicon Bug Diagnosis with Inconsistent Executions"
    Andrew DeOrio, Daya Shanker Khudia and Valeria Bertacco
    International Conference on Computer-Aided Design (ICCAD), San Jose, CA,November 2011
    PDF File

  • "Functional Correctness for CMP Interconnects"
    Rawan Abdel-Khalek, Ritesh Parikh, Andrew DeOrio and Valeria Bertacco
    International Conference on Computer Design (ICCD), Amherst, MA, October 2011
    PDF File

  • "ARIADNE: Agnostic Reconfiguration In A Disconnected Network Environment"
    Kostas Aisopos, Andrew DeOrio, Li-Shiuan Peh and Valeria Bertacco
    International Conference on Parallel Architectures and Compilation Techniques (PACT), Galveston Island, TX, October 2011
    PDF File

  • "DRAIN: Distributed Recovery Architecture for Inaccessible Nodes in Multi-Core Chips"
    Andrew DeOrio, Kostas Aisopos, Valeria Bertacco and Li-Shiuan Peh
    Design Automation Conference (DAC), San Diego, CA, June 2011
    PDF File

  • "A Distributed and Topology-Agnostic Approach for On-line NoC Testing"
    Mohammad Reza Kakoee, Valeria Bertacco and Luca Benini
    International Symposium on Networks-on-Chip (NOCS), Pittsburgh, PA, May 2011

  • "Highly scalable distributed dataflow analysis"
    Joseph Greathouse, Chelsea LeBlanc, Todd Austin and Valeria Bertacco
    International Symposium on Code Generation and Optimization (CGO), Chamonix, Switzerland, April 2011
    PDF File

  • "High Performance Gate-Level Simulation with GP-GPUs"
    Valeria Bertacco and Debapriya Chatterjee
    International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 2011
    PDF File

  • "ReliNoC: A Reliable Network for Priority-Based On-Chip Communication"
    Mohammad Reza Kakoee, Valeria Bertacco and Luca Benini
    Design Automation and Test in Europe (DATE), Grenoble, France, March 2011
    PDF File

    2010

  • "Application-Aware Diagnosis of Runtime Hardware Faults"
    Andrea Pellegrini and Valeria Bertacco
    International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2010
    PDF File

  • "EQUIPE: Parallel Equivalence Checking with GP-GPUs"
    Debapriya Chatterjee and Valeria Bertacco
    International Conference on Computer Design (ICCD), Amsterdam, the Netherlands, October 2010
    PDF File

  • "SoCGuard: A Runtime Verification Solution for the Functional Correctness of SoCs"
    Rawan Abdel-Khalek and Valeria Bertacco
    International Conference on VLSI and System-on-Chip (VLSI-SoC), Madrid, Spain, September 2010
    PDF File

  • "Electronic Design Automation for Social Networks"
    Andrew DeOrio and Valeria Bertacco
    Design Automation Conference (DAC) (invited paper), Anaheim, CA, June 2010
    PDF File

  • "Fault-Based Attack of RSA Authentication"
    Andrea Pellegrini, Valeria Bertacco and Todd Austin
    Design Automation and Test in Europe (DATE), Dresden, Germany, March 2010
    PDF File

  • "Post-silicon Debugging for Multi-core Designs"
    Valeria Bertacco
    Asia-South Pacific Design Automation Conference (ASP-DAC) (invited paper), Taipei, Taiwan, January 2010
    PDF File

    2009

  • "Event-Driven Gate-Level Simulation with GP-GPUs"
    Debapriya Chatterjee, Andrew DeOrio and Valeria Bertacco
    Design Automation Conference (DAC), San Francisco, CA, July 2009
    PDF File

  • "Vicis: A Reliable Network for Unreliable Silicon"
    David Fick, Andrew DeOrio, Jin Hu, Valeria Bertacco, Dennis Sylvester and David Blaauw
    Design Automation Conference (DAC), San Francisco, CA, July 2009
    PDF File

  • "Human Computing for EDA"
    Andrew DeOrio and Valeria Bertacco
    Design Automation Conference (DAC), San Francisco, CA, July 2009
    PDF File

  • "Debugging Strategies for Mere Mortals"
    Valeria Bertacco
    Design Automation Conference (DAC) (invited paper), San Francisco, CA, July 2009
    PDF File

  • "GCS: High Performance Gate-Level Simulation with GP-GPUs"
    Debapriya Chatterjee, Andrew DeOrio and Valeria Bertacco
    Design Automation and Test in Europe (DATE), Nice, France, April 2009
    PDF File

  • "A Highly Resilient Routing Algorithm for Fault-Tolerant NoCs"
    David Fick, Andrew DeOrio, Valeria Bertacco, Dennis Sylvester and David Blaauw
    Design Automation and Test in Europe (DATE), Nice, France, April 2009
    PDF File

  • "CASPAR: Hardware Patching for Multi-core Processors"
    Ilya Wagner and Valeria Bertacco
    Design Automation and Test in Europe (DATE), Nice, France, April 2009
    PDF File

  • "Customizing IP Cores for System-on-Chip Designs"
    Kai-hui Chang, Valeria Bertacco and Igor Markov
    Design Automation and Test in Europe (DATE), Nice, France, April 2009
    PDF File

  • "DACOTA: Post-silicon Validation of the Memory Subsystem in Multi-Core Designs"
    Andrew DeOrio, Ilya Wagner and Valeria Bertacco
    International Symposium on High-Performance Computer Architecture (HPCA), Raleigh, NC, February 2009
    PDF File

    2008

  • "Testudo: Heavyweight Security Analysis via Statistical Sampling"
    Joseph L. Greathouse, Ilya Wagner, David A. Ramos, Gautam Bhatnagar, Todd Austin, Valeria Bertacco and Seth Pettie
    International Symposium on Microarchitecture (MICRO), Lake Como, Italy, November 2008
    PDF File

  • "Reversi: Post-Silicon Validation System for Modern Microprocessors"
    Ilya Wagner and Valeria Bertacco
    IEEE International Conference on Computer Design (ICCD), Lake Tahoe, CA, October 2008
    Best Paper Award
    PDF File

  • "Post-Silicon Verification for Cache Coherence"
    Andrew DeOrio, Adam Bauserman and Valeria Bertacco
    IEEE International Conference on Computer Design (ICCD), Lake Tahoe, CA, October 2008
    PDF File

  • "CrashTest: A fast High-Fidelity FPGA-based Resiliency Analysis Framework"
    Andrea Pellegrini, Kypros Constantinides, Dan Zhang, Shobana Sudhakar, Valeria Bertacco and Todd Austin
    IEEE International Conference on Computer Design (ICCD), Lake Tahoe, CA, October 2008
    PDF File

  • "Reap what you sow: spare cells for post-silicon metal fix"
    Kai-hui Chang, Igor Markov and Valeria Bertacco
    International Symposium on Physical Design (ISPD), Portland, OR, April 2008
    PDF File

  • "Optimizing Non-Monotonic Interconnect using Functional Simulation and Logic Restructuring"
    Stephen Plaza, Igor Markov and Valeria Bertacco
    International Symposium on Physical Design (ISPD), Portland, OR, April 2008
    Best Paper Award
    PDF File

  • "MCjammer: Adaptive Verification for Multi-core Designs"
    Ilya Wagner and Valeria Bertacco
    Design Automation and Test in Europe (DATE), Munich, Germany, March 2008
    PDF File

  • "Random Stimulus Generation using Entropy and XOR constraints"
    Stephen Plaza, Igor Markov and Valeria Bertacco
    Design Automation and Test in Europe (DATE), Munich, Germany, March 2008
    PDF File

    2007

  • "Software-Based Defect Tolerance for Chip-Multiprocessors"
    Kypros Constantinides, Onur Mutlu, Todd Austin and Valeria Bertacco
    International Symposium on Microarchitecture (MICRO), Chicago, IL, December 2007
    PDF File

  • "Automating Post-Silicon Debugging and Repair"
    Kai-hui Chang, Igor Markov and Valeria Bertacco
    International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2007
    PDF File

  • "Engineering Trust with Semantic Guardians"
    Ilya Wagner and Valeria Bertacco
    Design Automation and Test in Europe (DATE), Nice, France, April 2007
    PDF File

  • "Low-Cost Protection Against SER Upsets and Silicon Defects"
    Mojtaba Mehrara, Mona Attarian, Smitha Shyam, Kypros Constantinides, Valeria Bertacco and Todd Austin
    Design Automation and Test in Europe (DATE), Nice, France, April 2007
    PDF File

  • "InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization"
    Kai-hui Chang, David Papa, Igor Markov and Valeria Bertacco
    International Symposium on Quality Elecronic Design (ISQED), San Jose, CA, March 2007
    PDF File

  • "Low Maintenance Verification"
    Valeria Bertacco
    Design Verification Conference (DVCON), (invited paper), San Jose, CA, February 2007
    PDF File

  • "Node Mergers in the Presence of Don't Cares"
    Stephen Plaza, Kai-hui Chang, Igor Markov and Valeria Bertacco
    Asia-South Pacific Design Automation Conference (ASP-DAC), Yokohama City, Japan, January 2007
    PDF File

  • "Safe Delay Optimization for Physical Synthesis"
    Kai-hui Chang, Igor Markov and Valeria Bertacco
    Asia-South Pacific Design Automation Conference (ASP-DAC), Yokohama City, Japan, January 2007
    PDF File

  • "Fixing Design Errors with Counterexamples and Resynthesis"
    Kai-hui Chang, Igor Markov and Valeria Bertacco
    Asia-South Pacific Design Automation Conference (ASP-DAC), Yokohama City, Japan, January 2007
    PDF File

    2006

  • "Verification Through the Principle of Least Astonishment"
    Beth Isaksen and Valeria Bertacco
    International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2006
    PDF File

  • "Ultra Low-Cost Defect Protection for Microprocessor Pipelines"
    Kypros Constantinides, Smitha Shyam, Sujay Phadke, Valeria Bertacco and Todd Austin
    International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), San Jose, CA, October 2006
    PDF File

  • "Shielding Against Design Flaws with Field Repairable Control Logic"
    Ilya Wagner, Valeria Bertacco and Todd Austin
    Design Automation Conference (DAC), San Francisco, CA, July 2006
    PDF File

  • "Distance-Guided Hybrid Verification with GUIDO"
    Smitha Shyam and Valeria Bertacco
    Design Automation and Test in Europe (DATE), Munich, Germany, March 2006
    PDF File

  • "BulletProof: A Defect-Tolerant CMP Switch Architecture"
    Kypros Constantinides, Stephen Plaza, Jason Blome, Bin Zhang, Valeria Bertacco, Scott Mahlke, Todd Austin and Michael Orshansky
    International Symposium on High-Performance Computer Architecture (HPCA), Austin, TX, February 2006
    PDF File

  • "Depth-Driven Verification of Simultaneous Interfaces"
    Ilya Wagner, Valeria Bertacco and Todd Austin
    Asia-South Pacific Design Automation Conference (ASP-DAC), Yokohama City, Japan, January 2006
    PDF File

    2005

  • "Simulation-based Bug Trace Minimization with BMC-based refinement"
    Kai-hui Chang, Valeria Bertacco and Igor Markov
    International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2005
    PDF File

  • "Post-Placement Rewiring and Rebuffering by Exhaustive Search for Functional Symmetries"
    Kai-hui Chang, Igor Markov and Valeria Bertacco
    International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2005
    PDF File

  • "Deployment of Better Than Worst-Case Design: Solutions and Needs"
    Todd Austin and Valeria Bertacco
    International Conference on Computer Design (ICCD), (invited paper), San Jose, CA, October 2005
    PDF File

  • "StressTest: An Automatic Approach to Test Generation Via Activity Monitors"
    Ilya Wagner, Valeria Bertacco and Todd Austin
    Design Automation Conference (DAC), Anaheim, CA, June 2005
    PDF File

  • "STACCATO: Disjoint Support Decompositions from BDDs through Symbolic Kernels"
    Stephen Plaza and Valeria Bertacco
    Asia-South Pacific Design Automation Conference (ASPDAC), Shanghai, China, January 2005
    PDF File

  • "Opportunities and Challenges for Better Than Worst-Case Design"
    Todd Austin, Valeria Bertacco, David Blaauw and Trevor Mudge
    Asia-South Pacific Design Automation Conference (ASPDAC), (invited paper), Shanghai, China, January 2005
    PDF File

    2004

  • "Microarchitectural Power Modeling Techniques for Deep Sub-Micron Microprocessors"
    Nam Sung Kim, Tae Ho Kgil, Valeria Bertacco, Todd Austin and Trevor Mudge
    International Symposium on Low Power Electronics and Design (ISLPED), Newport, CA, August 2004
    PDF File

  • "Circuit-Aware Architectural Simulation"
    Seokwoo Lee, Shidhartha Das, Valeria Bertacco, Todd Austin, David Blaauw and Trevor Mudge
    Design Automation Conference (DAC), San Diego, CA, June 2004
    PDF File

    2002

  • "Efficient State Representation for Symbolic Simulation"
    Valeria Bertacco and Kunle Olukotun
    Design Automation Conference (DAC), New Orleans, LA, June 2002
    PDF File

    2000

  • "Smart Simulation Using Collaborative Formal and Simulation Engines"
    Pei-Hsin Ho, Thomas Shiple, Kevin Harer, James Kukula, Robert Damiano, Valeria Bertacco, Jerry Taylor and Jiang Long
    International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2000
    PDF File

    <2000

  • "Cycle-based Symbolic Simulation of Gate-level Synchronous Circuits"
    Valeria Bertacco, Maurizio Damiani and Stefano Quer
    Design Automation Conference (DAC), New Orleans, LA, June 1999
    PDF File

  • "The Disjunctive Decomposition of Logic Functions"
    Valeria Bertacco and Maurizio Damiani
    International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 1997
    PDF File

  • "Boolean Function Representation Based on Disjoint-Support Decompositions"
    Valeria Bertacco and Maurizio Damiani
    International Conference on Computer Design (ICCD), Austin, TX, October 1996
    PDF File
    PDF File - long version

  • "Boolean Function Representation Using Parallel-Access Diagrams"
    Valeria Bertacco and Maurizio Damiani
    6th Great Lakes Symposium on VLSI (GLS-VLSI), Des Moines, IA, March 1996
    PDF File

Book Chapters and Journal Articles

  • "Post-silicon Validation of Multi-Processor Memory Consistency"
    Biruk Mammo, Valeria Bertacco, Andrew DeOrio and Ilya Wagner
    IEEE Transactions on Computer-aided Design (TCAD)
    under review

  • "At-speed Distributed Functional Testing To Detect Logic and Delay Faults In NoCs"
    Mohammad Reza Kakoee, Valeria Bertacco and Luca Benini
    IEEE Transactions on Computers (TC), Volume 63-3, March 2014
    PDF File

  • "Formally Enhanced Runtime Verification to Ensure NoC Functional Correctness"
    Ritesh Parikh and Valeria Bertacco
    ACM Transactions on Embedded Computing Systems (TECS), Volume 13-3s, March 2014
    PDF File

  • "Post-Silicon Platform for the Functional Diagnosis and Debug of Networks-on-Chip"
    Rawan Abdel-Khalek and Valeria Bertacco
    ACM Transactions on Embedded Computing Systems (TECS), Volume 13-3s, March 2014
    PDF File

  • "Cardio: CMP Adaptation for Reliability through Dynamic Introspective Operation"
    Andrea Pellegrini and Valeria Bertacco
    IEEE Transactions on Computer-aided Design (TCAD) Volume 33-2, February 2014
    PDF File

  • "A Reliable Routing Architecture and Algorithm for NoCs"
    Andrew DeOrio, David Fick, Valeria Bertacco, Dennis Sylvester, David Blaauw, Jin Hu and Gregory Chen
    IEEE Transactions on Computer-aided Design (TCAD), Volume 31-5, May 2012
    PDF File

  • "Gate-Level simulation with GPU Computing"
    Debapriya Chatterjee, Andrew DeOrio and Valeria Bertacco
    ACM Transactions on Design Automation of Electronic Systems (TODAES) Volume 16-3, June 2011
    PDF File

  • GPU Computing Gems - Chapter 23
    High Performance Gate-Level Simulation with GP-GPUs
    Debapriya Chatterjee, Andrew DeOrio and Valeria Bertacco
    published by Morgan Kaufmann, 2011 - ISBN: 978-0123849885
    order through Amazon

  • "Logic Synthesis and Circuit Customization Using Extensive External Don't-Cares"
    Kai-hui Chang, Valeria Bertacco, Igor Markov and Alan Mishchenko
    ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 15, Issue 3, May 2010
    PDF File

  • "A Flexible Software-Based Framework for Online Detection of Hardware Defects"
    Kypros Constantinides, Onur Mutlu, Todd Austin and Valeria Bertacco
    IEEE Transactions on Computers (TC), Volume 58, Issue 8, August 2009
    PDF File

  • "INFERNO: Streamlining Verification with Inferred Semantics"
    Andrew DeOrio, Adam Bauserman, Valeria Bertacco and Beth Isaksen
    IEEE Transactions on Computer-Aided Design (TCAD), Volume 28, Issue 5, May 2009
    PDF File

  • "Incremental Verification System for Error Detection, Diagnosis, and Visualization"
    Kai-hui Chang, David Papa, Igor Markov and Valeria Bertacco
    IEEE Design & Test (D&T), Volume 26, Issue 2, March/April 2009
    PDF File

  • "Optimizing Non-Monotonic Interconnect using Functional Simulation and Logic Restructuring"
    Stephen Plaza, Igor Markov and Valeria Bertacco
    IEEE Transactions on Computer-Aided Design (TCAD), Volume 27, Issue 12, December 2008
    PDF File

  • "Reliable Systems on Unreliable Fabrics"
    Todd Austin, Valeria Bertacco, Scott Mahlke and Yu Cao
    IEEE Design & Test (D&T), Volume 25, Issue 4, July/August 2008
    PDF File

  • "SafeResynth: A New Technique for Physical Synthesis"
    Kai-hui Chang, Igor Markov and Valeria Bertacco
    Integration, The VLSI Journal - Elsevier, Volume 41, Issue 4, July 2008
    PDF File

  • "Automating Post-Silicon Debugging and Repair"
    Kai-hui Chang, Igor Markov and Valeria Bertacco
    IEEE Computer, Volume 41, Issue 7, July 2008
    PDF File

  • "Using Field-Repairable Control Logic to Correct Design Errors in Microprocessor Pipelines"
    Ilya Wagner, Valeria Bertacco and Todd Austin
    IEEE Transactions on Computer-Aided Design (TCAD), Volume 27, Issue 2, February 2008
    PDF File

  • "Fixing Design Errors with Counterexamples and Resynthesis"
    Kai-hui Chang, Igor Markov and Valeria Bertacco
    IEEE Transactions on Computer-Aided Design (TCAD), Volume 27, Issue 1, January 2008
    PDF File

  • "Post-Placement Rewiring by Exhaustive Search for Functional Symmetries"
    Kai-hui Chang, Igor Markov and Valeria Bertacco
    ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 12, Issue 3, August 2007
    PDF File

  • "Microprocessor Verification via Feedback-Adjusted Markov Models"
    Ilya Wagner, Valeria Bertacco and Todd Austin
    IEEE Transactions on Computer-Aided Design (TCAD), Volume 26, Issue 6, June 2007
    PDF File

  • "Architecting a Reliable CMP Switch Architecture"
    Kypros Constantinides, Stephen Plaza, Jason Blome, Valeria Bertacco, Scott Mahlke, Todd Austin, Bin Zhang and Michael Orshansky
    ACM Transactions on Architecture and Code Optimization (TACO), Volume 4, Issue 1, March 2007
    PDF File

  • "Simulation-based Bug Trace Minimization with BMC-based Refinement"
    Kai-hui Chang, Valeria Bertacco and Igor Markov
    IEEE Transactions on Computer-Aided Design (TCAD), Volume 26, Issue 1, January 2007
    PDF File

Workshop Publications

    2014

  • "High Radix On-chip Networks at Incremental Reconfiguration Cost"
    Ritesh Parikh, Animesh Jain and Valeria Bertacco
    Semiconductor Research Corp - TECHCON, Austin, TX, September 2014
    PDF File

  • "Debug Data Collection for Functional Validation of Control-Flow in NoCs"
    Rawan Abdel-Khalek and Valeria Bertacco
    Semiconductor Research Corp - TECHCON, Austin, TX, September 2014
    PDF File

  • "High-Radix On-chip Networks at Incremental Reconfiguration Cost"
    Animesh Jain, Ritesh Parikh and Valeria Bertacco
    International Workshop on Logic and Synthesis (IWLS), San Fransisco, CA, June 2014
    PDF File

    2013

  • "ArChIVED: High Performance Validation of Microprocessors Using Event Digests"
    Chang-Hong Hsu, Debapriya Chatterjee, Ronny Morad, Raviv Gal and Valeria Bertacco
    International Workshop on Logic and Synthesis (IWLS), Austin, TX, June 2013
    PDF File

    2012

  • "Architectural Trace-Based Functional Coverage for Multiprocessor Verification"
    Biruk Mammo, Jim Larimer, Matthew Morgan, Dave Fan, Eric Hennenhoefer and Valeria Bertacco
    International Workshop on Microprocessor Test and Verification (MTV), Austin, TX, December 2012
    PDF File

  • "LinkMiser: Resource Conscious Routing and Reconfiguration in Faulty On-Chip Networks"
    Ritesh Parikh and Valeria Bertacco
    International Workshop on Logic and Synthesis (IWLS), Berkeley, CA, June 2012
    PDF File

    2011

  • "Cardio: Adaptive CMPs for Reliability Through Dynamic Introspective Operation"
    Andrea Pellegrini and Valeria Bertacco
    High-Level Design and Validation Workshop (HLDVT), Napa, CA, November 2011
    PDF File

  • "Simulation-based Signal Selection for State Restoration in Silicon Debug"
    Debapriya Chatterjee and Valeria Bertacco
    International Workshop on Logic and Synthesis (IWLS), La Jolla, CA, June 2011
    PDF File

  • "Cardio: Adaptive CMPs for Reliability through Dynamic Introspective Operation"
    Andrea Pellegrini and Valeria Bertacco
    International Workshop on Logic and Synthesis (IWLS), La Jolla, CA, June 2011
    PDF File

  • "Formally Enhanced Verification at Runtime to Ensure NoC Functional Correctness"
    Ritesh Parikh, Rawan Abdel-Khalek and Valeria Bertacco
    International Workshop on Logic and Synthesis (IWLS), La Jolla, CA, June 2011
    PDF File

  • "CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions"
    Andrea Pellegrini, Rob Smolinski, Lei Chen, Xin Fu, Siva Kumar Sastry Hari, Junhao Jiang, Sarita Adve, Todd Austin and Valeria Bertacco
    Silicon Errors in Logic - System Effects Workshop (SELSE), Champaign-Urbana, IL, March 2011
    PDF File

    2010

  • "EQUIPE: Parallel Equivalence Checking with GPU's"
    Debapriya Chatterjee and Valeria Bertacco
    International Workshop on Logic Synthesis (IWLS), Irvine, CA, June 2010
    PDF File

  • "Application-Aware Diagnosis of Runtime Hardware Faults"
    Andrea Pellegrini and Valeria Bertacco
    International Workshop on Logic Synthesis (IWLS), Irvine, CA, June 2010
    PDF File

    2009

  • "Activity-Based Refinement for Abstraction-Guided Simulation"
    Debapriya Chatterjee and Valeria Bertacco
    High-Level Design and Validation Workshop (HLDVT), San Francisco, CA, November 2009
    PDF File

  • "PowerRanger: Assessing Circuit Vulnerability to Power Attacks Using SAT-Based Static Analysis"
    Jeff Hao and Valeria Bertacco
    High-Level Design and Validation Workshop (HLDVT), San Francisco, CA, November 2009
    PDF File

    2008

  • "Low-latency SAT Solving on Multicore Processors with Priority Scheduling and XOR Partitioning"
    Stephen Plaza, Igor Markov and Valeria Bertacco
    International Workshop on Logic Synthesis (IWLS), Lake Tahoe, CA, June 2008
    PDF File

  • "Synthesis with External Don't-Cares Using Shannon Entropy and Craig Interpolation"
    Kai-hui Chang, Valeria Bertacco, Igor Markov and Alan Mishchenko
    International Workshop on Logic Synthesis (IWLS), Lake Tahoe, CA, June 2008
    PDF File

    2007

  • "Chico: An On-Chip Hardware Checker for Pipeline Control Logic"
    Andrew DeOrio, Adam Bauserman and Valeria Bertacco
    International Workshop on Microprocessor Test and Verification (MTV), Austin, TX, December 2007
    PDF File

  • "Automatic Error Diagnosis and Correction for RTL Designs"
    Kai-hui Chang, Ilya Wagner, Valeria Bertacco and Igor Markov
    High-Level Design and Validation Workshop (HLDVT), Irvine, CA, November 2007
    PDF File

  • "MCjammer: An Adaptive Verification Tool for Multi-core and Multi-processor Designs"
    Ilya Wagner and Valeria Bertacco
    International Workshop on Logic Synthesis (IWLS), San Diego, CA, June 2007
    PDF File

  • "Automatic Error Diagnosis and Correction for RTL Designs"
    Kai-hui Chang, Ilya Wagner, Valeria Bertacco and Igor Markov
    International Workshop on Logic Synthesis (IWLS), San Diego, CA, June 2007
    PDF File

  • "Automatic Post-Silicon Debugging and Repair"
    Kai-hui Chang, Igor Markov and Valeria Bertacco
    International Workshop on Logic Synthesis (IWLS), San Diego, CA, June 2007
    PDF File

  • "Toggle: A Coverage-guided Random Stimulus Generator"
    Stephen Plaza, Igor Markov and Valeria Bertacco
    International Workshop on Logic Synthesis (IWLS), San Diego, CA, June 2007
    PDF File

    2006

  • "Keeping Physical Synthesis Safe and Sound"
    Kai-hui Chang, Igor Markov and Valeria Bertacco
    International Workshop on Logic Synthesis (IWLS), Vail, CO, June 2006
    PDF File

  • "Advances and Insights into Parallel SAT Solving"
    Stephen Plaza, Ian Kountanis, Zaher Andraus, Valeria Bertacco and Trevor Mudge
    International Workshop on Logic Synthesis (IWLS), Vail, CO, June 2006
    PDF File

  • "Fast Simulation and Equivalence Checking using OAGear"
    Kai-hui Chang, David Papa, Igor Markov and Valeria Bertacco
    International Workshop on Logic Synthesis (IWLS), Vail, CO, June 2006
    PDF File

  • "VOLTaiRE: Low-Cost Fault Detection Solutions for VLIW Microprocessors"
    Smitha Shyam, Sujay Phadke, Benjamin Lui, Hitesh Gupta, Valeria Bertacco, David Blaauw
    Workshop on Introspective Architecture (WISA06), Austin, TX, February 2006
    PDF File

    2005

  • "Assessing SEU Vulnerability via Circuit-Level Timing Analysis"
    Kypros Constantinide,s Stephen Plaza, Jason Blome, Bin Zhang, Valeria Bertacco, Scott Mahlke, Todd Austin and Michael Orshansky
    Workshop on Architectural Reliability (WAR-1), Barcelona, Spain, November 2005
    PDF File

  • "GUIDO: Hybrid Verification by Distance-Guided Simulation"
    Smitha Shyam and Valeria Bertacco
    International Workshop on Logic Synthesis (IWLS), Lake Arrowhead, CA, June 2005
    PDF File

  • "Post-Placement Rewiring and Rebuffering by Exhaustive Search for Functional Symmetries"
    Kai-hui Chang, Igor Markov and Valeria Bertacco
    International Workshop on Logic Synthesis (IWLS), Lake Arrowhead, CA, June 2005
    PDF File

  • "Boolean Operations on Decomposed Functions"
    Stephen Plaza and Valeria Bertacco
    International Workshop on Logic Synthesis (IWLS), Lake Arrowhead, CA, June 2005
    PDF File

    2004

  • "Restoring Circuit Structure from SAT Instances"
    Jarrod Roy, Igor Markov and Valeria Bertacco
    International Workshop on Logic Synthesis (IWLS), Temecula Creek, CA, June 2004
    PDF File

    <2000

  • "Finding complex disjunctive decompositions of logic functions"
    Maurizio Damiani and Valeria Bertacco
    International Workshop on Logic Synthesis (IWLS), Lake Tahoe, CA, June 1998
    PDF File

  • "The disjunctive decomposition of logic functions"
    Valeria Bertacco and Maurizio Damiani
    International Workshop on Logic Synthesis (IWLS), Lake Tahoe, CA, June 1997
    PDF File

  • "Decision Diagrams and Pass Transistor Logic Synthesis"
    Valeria Bertacco, Shin-ichi Minato, Peter Verplaetse, Luca Benini, Giovanni DeMicheli
    International Workshop on Logic Synthesis (IWLS), Lake Tahoe, CA, June 1997
    PDF File

  • "An efficient canonical representation of logic functions based on disjoint-support decomposition"
    Valeria Bertacco and Maurizio Damiani
    Workshop on DFT/BIST, Vail, CO, April 1996
    PDF File