CSE #4808 - ACAL Lab
- Teaching this semester
EECS 578 - Correct Operation for Processors and Embedded Systems
- Recent publications
- "High-Radix On-chip Networks with Low-Radix Routers"
- Animesh Jain, Ritesh Parikh and Valeria Bertacco
International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2014
- "DiAMOND: Distributed Alteration of Messages for On-Chip Network Debug"
- Rawan Abdel-Khalek and Valeria Bertacco
International Symposium on Networks-on-Chip (NoCs), Ferrara, Italy, September 2014
Best Paper Award Finalist
(2 finalists in conference)
- "Brisk and Limited-Impact NoC Routing Reconfiguration"
- Doowon Lee, Ritesh Parikh and Valeria Bertacco
Design Automation and Test in Europe (DATE), Dresden, Germany, March 2014
- "uDIREC: Unified Diagnosis and Reconfiguration for Frugal Bypass of NoC faults"
- Ritesh Parikh and Valeria Bertacco
International Symposium on Microarchitecture (MICRO), Davis, CA, December 2013
I am interested in the functional correctness of hardware designs, addressing the challenges posed by fragile silicon and extreme design complexity. I focus on the creation of novel techniques to guarantee correctness against functional errors, temporary and permanent transistor failures and security attacks. A large part of my effort targets processor designs, particularly multi-core systems, both homogeneus and heteregenous, and their uncore components.
My present research and my professional experience are centered on the development of new algorithms and on-chip units for pre-silicon, post-silicon and runtime validation and debug. This focus is extended to support the correctness of designs in the face of transistor failures, through techniques that use novel reliability mechanisms to extend the system's lifetime and to provide guarantees of its correct behavior.
I am part of the Advanced Computer Architecture Lab in the EECS Department of the University of Michigan. The lab includes 15 faculty members and approximately 70 students. The Lab is part of the Computer Science and Engineering Division.
Short biographyValeria Bertacco is Professor of Electrical Engineering and Computer Science at the University of Michigan since 2003. Her research interests are in the area of computer design, with emphasis on reliability, design correctness and hardware-security assurance. Prior to joining the University of Michigan, Valeria was with the Advanced Technology Group of Synopsys for four years as a lead developer of the industry-standard Vera and Magellan tools. She came to Synopsys via the acquisition of Systems Science Inc., where she was working at the time. During the Winter of 2012, she was on sabbatical at the Addis Ababa Institute of Technology.
Valeria has served in several conference program committees, including DATE, DAC and DSN, and has been an Associated Editor for the IEEE Transactions on CAD and the Microelectronics Journal. She is the author of three books on design's functional correctness. She received her M.S. and Ph.D. degrees in Electrical Engineering from Stanford University in 1998 and 2003; and a Computer Engineering degree ("Dottore in Ingegneria") summa cum laude from the University of Padova, Italy in 1995. Valeria is the recipient of the IEEE CEDA Early Career Award, NSF CAREER award, the Air Force Office of Scientific Research's Young Investigator award, the IBM Faculty Award and the Vulcans Education Excellence Award and Rackham Faculty Recognition Award from the University of Michigan. Valeria is an ACM Distinguished Scientist.