Shruti Padmanabha
shrupad at umich.edu
University of Michigan (EECS)
2260 Hayward Street Ann Arbor, MI, 48109
Office: 4849 CSE
Affiliated to
Compilers Creating Custom Processors
Advanced Computer Architecture Lab
About me
My research interests lie in the design of energy efficient processor and memory architectures including heterogeneous multicore systems. I completed my BTech(Hons) degree from BITS Pilani, Goa in 2011. Following which, I started my Masters+PhD program in Fall 2011. I completed my Masters degree in May 2013, and became a PhD candidate in Fall of the same year. Currently I'm engaged full-time in my thesis research.
I work with Prof. Scott Mahlke on a project that envisions a processor with multiple heterogeneous energy efficient backends on a core. My project aims to achieve energy-efficient execution of general-purpose applications by rethinking the microarchitecture of a core -- from a monolithic computing unit to a combination of heterogeneous core pipelines. The runtime layer of this system must determine fine-grained execution slices and pro-actively map it to the most efficient engine. I have examined the sustainability and predictability of performance and metrics affecting performance in fine-grained application slices or traces to aid the runtime management system at making fast and accurate switching decisions. I'm currently working on exploring and designing customized backends that provide efficiency across diverse applications and their characteristics at phases of a fine-granularity.
It’s a magical world, Hobbes, ol’ buddy…Let’s go exploring! -- Calvin, Calvin & Hobbes
Publications
Conferences
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DynaMOS: Dynamic Schedule Migration for Heterogeneous Cores
Shruti Padmanabha, Andrew Lukefahr, Reetuparna Das, and Scott Mahlke
The International Symposium on Microarchitecture (MICRO-48), Dec. 2015
Paper, Slides
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Heterogeneous Microarchitectures Trump Voltage Scaling for Low-Power Cores
Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Faissal M. Sleiman, Ronald Dreslinski, Thomas F. Wenisch, and Scott Mahlke
The International Conference on Parallel Architectures and Compilation Techniques (PACT-23), Aug. 2014
Paper, Slides -
Trace Based Phase Prediction For Tightly-Coupled Heterogeneous Cores
Shruti Padmanabha, Andrew Lukefahr, Reetuparna Das, and Scott Mahlke
The International Symposium on Microarchitecture (MICRO-46), Dec. 2013
Paper, Slides
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Composite Cores: Pushing Heterogeneity into a Core
Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Faissal M. Sleiman, Ronald Dreslinski, Thomas F. Wenisch, and Scott Mahlke
The International Symposium on Microarchitecture (MICRO-45), Dec. 2012
Paper, Slides
Journals
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Exploring Fine-Grained Heterogeneity with Composite Cores
Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Faissal M. Sleiman, Ronald Dreslinski, Thomas F. Wenisch, and Scott Mahlke
IEEE Transactions on Computers (To Appear. 2015)
Workshops
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Performance Prediction Models
Shruti Padmanabha, Andrew Lukefahr, Reetuparna Das, and Scott Mahlke
Gem5 user workshop at The International Symposium on Microarchitecture (MICRO-45), Dec. 2012
Slides
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Adaptive Cache Partitioning on a Composite Core
Jiecao Yu, Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, and Scott Mahlke
The PRISM-3 Workshop at The International Symposium on Computer Architecture (ISCA-45), June, 2015
Slides
Patents
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Control of Switching Between Executed Mechanisms
Shruti Padmanabha, Andrew Lukefahr, Reetuparna Das, and Scott Mahlke
US 14/323,040, Filed July 3, 2014
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Trace Based Phase Prediction for Tightly-Coupled Heterogeneous Cores
Shruti Padmanabha, Andrew Lukefahr, Reetuparna Das, and Scott Mahlke
US/093,042, Filed November 29, 2013
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Heterogeneity Within A Processor Core
Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, and Scott Mahlke
US 14/093,090, Filed November 29, 2013