EECS 373 -- HW1: Debugging Schedule

Instructions:

• Put Your Name In the Box --->

==================================================================

   STATUS

==================================================================

• Group 1 is done

• Group 2 is done

• Group 3 is done

• Group 4 is done

• Group 5 is currently working

• Group 6 is currently working

31 enrolled students, 10 groups of 3 + 1 group of 4

• (Now) - Monday, Sep 26 at Midnight

• Assignment 1

• (don't forget to "svn update" first!)

• Simulator must sucessfully run all of basic.s

• Group:

• Tyler Axdorff -- taxdorff@umich.edu

• Joseph Romeoo -- jromeoo@umich.edu

• Charles Irvin -- irvinc@umich.edu

• Midnight Mon Sep 26 -- Midnight Wed Sep 28

• Assignment 2

• All of the sample programs (blink.c, echo.c, echo_str.c, trivialC.c, trivialS.s, trivialPrintf.c) must run correctly on the reference simulator

• Note: You do not have to debug printf 100%, just enough to get trivialPrintf.c working correctly (aka, %s has to work - and from a quick look, I think it already does)

• Group

• Haishan Zhu -- francisz@umich.edu

• Yifei Huang -- yifhuang@umich.edu

• Adam Williams -- adamwill@umich.edu

• Midnight Wed Sep 28 -- Midnight Fri Sep 30

• Assignment 3

• Simulator must run blink.c correctly

• Group

• Jack Schultz -- schuljoh@umich.edu

• Sami Luber -- saluber@umich.edu

• Andrew Robinson - androbin@umich.edu

• Midnight Fri Sep 30 -- Midnight Sun Oct 2

• Assignment 4

• Simulator must run all sample programs (blink.c, echo.c, echo_str.c, trivialC.c trivialS.s trivialPrintf.c) correctly

• Group

• Constantine Ioannou -- ibooga@gmail.com

• Forest Darling -- fdarling@umich.edu

• Baishun Goldenears -- wubs@umich.edu

• Midnight Sun Oct 2 -- Midnight Tue Oct 4

• Assignment 5

• Branch, CB, CMP, and IT testbenches must be complete in coverage and run correctly on the simulator

• B,bl,blx,bx,cbz,cmn_imm,cmn_reg,cmp_imm,cmp_reg,it

• Your testbench sould thouroughly test all the possible conditions

• (That is, not just 'eq' and 'ne', bring in the others: cs/hs, cc/lo, mi, pl, etc)

• Group

• Noah Klugman

• Tarek El Shamy

• MJ Gellada - xirt@umich.edu

• Midnight Tue Oct 4 -- Midnight Thr Oct 6

• Assignment 6

• Add, Sub, and Mov testbenches must be complete in coverage and run correctly on the simulator

• adc_imm,adc_reg,add_imm,add_reg,add_sp_imm,add_sp_reg,rsb_imm,rsb_reg,sbc_imm,

• sbc_reg,sub_imm,sub_reg,sub_sp_imm,sub_sp_reg,mov_imm,mov_reg,movt,pkhbt

• Optional: the signed and unsigned add and sub instructions

• sadd16,sadd8,shadd16,shadd8,uadd16,uadd8,uhadd16,uhadd8,usad8,usada8,shsub16,shsub8,ssub16,ssub8,uhsub16,uhsub8,usub16,usub8

• Group

• Aryn Lipnicki - alipnick@umich.edu

• Joshua Stephenson - joshstep@umich.edu

• Lisa Herta - hertal@umich.edu

• Midnight Thr Oct 6 -- Midnight Sat Oct 8

• Assignment 7

• Logical, Extend, and Shift testbenches must be complete in coverage and run correctly on the simulator

• and_imm,and_reg,bic_imm,bic_reg,eor_imm,eor_reg,lsl_imm,lsl_reg,lsr_imm,lsr_reg,mvn_imm,mvn_reg,orn_imm,orn_reg,orr_imm,orr_reg,teq_imm,teq_reg,tst_imm,tst_reg,sxtb,sxtb16,sxth,uxtab,uxtab16,uxtah,uxtb,uxtb16,uxth,asr_imm,asr_reg,ror_imm,ror_reg,rrx

• Group

• Kevin Nasto - knasto@umich.edu

• Ian Burris - iburris@umich.edu

• Chris Dionysopoulos - cdiony@umich.edu

• Midnight Sat Oct 8 -- Midnight Mon Oct 10

• Assignment 8

• Push, Pop, Ld, and Str testbenches must be complete in coverage and run correctly on the simulator

• push,pop,ldr_imm,ldr_lit,ldr_reg,ldrb_imm,ldrb_lit,ldrb_reg,ldrd_imm,

• ldrd_lit,ldrh_imm,ldrh_lit,ldrh_reg,ldrsb_imm,ldrsb_lit,ldrsb_reg,ldrsh_imm,

• ldrsh_lit,ldrsh_reg,str_imm,str_reg,strb_imm,strb_reg,strd_imm,strh_imm,

• strh_reg

• Group

• Austen Campbell-Fox

• Robert Napier - rlnapier@umich.edu

• Lizzie Paris - elizpar@umich.edu

• Midnight Mon Oct 10 -- Midnight Wed Oct 12

• Assignment 9

• Mul and Div testbenches must be complete in coverage and run correctly on the simulator

• mla,mls,mul,smlabb,smlad,smlal,smlalbb,smlald,smlawb,smlsd,smlsld,smmla,smmls,smmul,smuad,smulbb,smull,smulwb,smusd,umaal,umlal,umull,sdiv,udiv

• Group

• Alan Duanmu - duanmua@umich.edu

• Sheikh Shafeen Mahmud - shafeen@umich.edu

• Fahd Ibn Muhib - fmuhib@umich.edu

• Midnight Wed Oct 12 -- Midnight Fri Oct 14

• Assignment 10

• Ldm and Strm testbenches must be complete in coverage and run correctly on the simulator

• ldm,ldmdb,stm,stmdb

• Develop a printf testbench and ensure that it outputs what is expected over the UART peripheral.  You should test all of our supported features of printf ( \n \t %% %{d,u,x,c,s} %{digit}+{d,u,x,c,s} %0{digit}+{d,u,x,c,s} ).  See trivalPrintf.c for an example. This portion does not have to be automated (e.g., you can verify the printf output by hand on a terminal)

• However, extra credit available if you write an expect script: http://www.tcl.tk/man/expect5.31/expect.1.html

• Group

• Haven Moore -havenm@umich.edu

• Kyle Fassnacht - kfoznot@umich.edu

• Jerome Grunnale - tgrunn@umich.edu