#Build: Synplify Pro D-2009.12A, Build 040R, Jan 20 2010 #install: C:\Actel\Libero_v9.0\Synopsys\synplify_D200912A #OS: 6.1 #Hostname: WIN-K2PJVCLULR9 #Implementation: synthesis #Sat Aug 28 14:19:47 2010 $ Start of Compile #Sat Aug 28 14:19:47 2010 Synopsys Verilog Compiler, version comp475rc, Build 060R, built Jan 15 2010 Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved @I::"C:\Actel\Libero_v9.0\Synopsys\synplify_D200912A\lib\proasic\smartfusion.v" @I::"Z:\Documents\projects\teaching\eecs373-f10\labs\lab4\files\lab4fpga\component\Actel\SmartFusionMSS\MSS\2.2.101\mss_comps.v" @I::"Z:\Documents\projects\teaching\eecs373-f10\labs\lab4\files\lab4fpga\component\work\lab4_mss\MSS_CCC_0\lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v" @I::"Z:\Documents\projects\teaching\eecs373-f10\labs\lab4\files\lab4fpga\component\work\lab4_mss\lab4_mss.v" @I::"Z:\Documents\projects\teaching\eecs373-f10\labs\lab4\files\lab4fpga\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3_muxptob3.v" @I::"Z:\Documents\projects\teaching\eecs373-f10\labs\lab4\files\lab4fpga\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v" @I::"Z:\Documents\projects\teaching\eecs373-f10\labs\lab4\files\lab4fpga\hdl\enc3to8.v" @I::"Z:\Documents\projects\teaching\eecs373-f10\labs\lab4\files\lab4fpga\hdl\enc3to8wraper.v" @I::"Z:\Documents\projects\teaching\eecs373-f10\labs\lab4\files\lab4fpga\component\work\lab4_top\lab4_top.v" Verilog syntax check successful! Options changed - recompiling Selecting top level module lab4_top @W:CG775 : coreapb3.v(13) | Found Component CoreAPB3 in library COREAPB3_LIB @N:CG364 : coreapb3_muxptob3.v(13) | Synthesizing module CAPB3O @N:CG364 : coreapb3.v(13) | Synthesizing module CoreAPB3 APB_DWIDTH=6'b100000 RANGESIZE=21'b000000000000100000000 IADDR_ENABLE=1'b0 APBSLOT0ENABLE=1'b1 APBSLOT1ENABLE=1'b0 APBSLOT2ENABLE=1'b0 APBSLOT3ENABLE=1'b0 APBSLOT4ENABLE=1'b0 APBSLOT5ENABLE=1'b0 APBSLOT6ENABLE=1'b0 APBSLOT7ENABLE=1'b0 APBSLOT8ENABLE=1'b0 APBSLOT9ENABLE=1'b0 APBSLOT10ENABLE=1'b0 APBSLOT11ENABLE=1'b0 APBSLOT12ENABLE=1'b0 APBSLOT13ENABLE=1'b0 APBSLOT14ENABLE=1'b0 APBSLOT15ENABLE=1'b0 CAPB3O1I=32'b00000000000000000000000000001000 CAPB3I1I=32'b00000000000000000000000000001000 CAPB3l1I=8'b00001100 CAPB3OOl=8'b00001000 CAPB3IOl=8'b00000100 CAPB3lOl=8'b00000000 CAPB3OIl=8'b00000100 CAPB3IIl=8'b00000000 CAPB3lIl=8'b00000000 CAPB3Oll=16'b0000000000000001 CAPB3Ill=16'b0000000000000000 CAPB3lll=16'b0000000000000000 CAPB3O0l=16'b0000000000000000 CAPB3I0l=16'b0000000000000000 CAPB3l0l=16'b0000000000000000 CAPB3O1l=16'b0000000000000000 CAPB3I1l=16'b0000000000000000 CAPB3l1l=16'b0000000000000000 CAPB3OO0=16'b0000000000000000 CAPB3IO0=16'b0000000000000000 CAPB3lO0=16'b0000000000000000 CAPB3OI0=16'b0000000000000000 CAPB3II0=16'b0000000000000000 CAPB3lI0=16'b0000000000000000 CAPB3Ol0=16'b0000000000000000 Generated name = CoreAPB3_Z1 @N:CG364 : smartfusion.v(1814) | Synthesizing module VCC @N:CG364 : mss_comps.v(23) | Synthesizing module INBUF_MSS @N:CG364 : mss_comps.v(151) | Synthesizing module MSS_CCC @N:CG364 : smartfusion.v(2566) | Synthesizing module RCOSC @N:CG364 : smartfusion.v(1133) | Synthesizing module GND @N:CG364 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(5) | Synthesizing module lab4_mss_tmp_MSS_CCC_0_MSS_CCC @N:CG364 : mss_comps.v(680) | Synthesizing module MSS_APB @N:CG364 : lab4_mss.v(5) | Synthesizing module lab4_mss @N:CG364 : enc3to8.v(3) | Synthesizing module enc3to8 @N:CG364 : enc3to8wraper.v(3) | Synthesizing module enc3to8wraper @W:CL113 : enc3to8wraper.v(41) | Feedback mux created for signal sw_reg[31:2]. @A: : enc3to8wraper.v(41) | Feedback mux created for signal PRDATA[31:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @W:CL251 : enc3to8wraper.v(41) | All reachable assignments to sw_reg[31:2] assign 0, register removed by optimization @N:CG364 : lab4_top.v(5) | Synthesizing module lab4_top @W:CL246 : enc3to8wraper.v(20) | Input port bits 1 to 0 of PADDR[3:0] are unused @W:CL157 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(62) | *Output RCOSC_CLKOUT has undriven bits - a simulation mismatch is possible @W:CL157 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(63) | *Output MAINXIN_CLKOUT has undriven bits - a simulation mismatch is possible @W:CL157 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(64) | *Output LPXIN_CLKOUT has undriven bits - a simulation mismatch is possible @W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(36) | Input CLKA is unused @W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(37) | Input CLKA_PAD is unused @W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(38) | Input CLKA_PADP is unused @W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(39) | Input CLKA_PADN is unused @W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(40) | Input CLKB is unused @W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(41) | Input CLKB_PAD is unused @W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(42) | Input CLKB_PADP is unused @W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(43) | Input CLKB_PADN is unused @W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(44) | Input CLKC is unused @W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(45) | Input CLKC_PAD is unused @W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(46) | Input CLKC_PADP is unused @W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(47) | Input CLKC_PADN is unused @W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(48) | Input MAINXIN is unused @W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(49) | Input LPXIN is unused @W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(50) | Input MAC_CLK is unused @W:CL246 : coreapb3.v(217) | Input port bits 23 to 12 of PADDR[23:0] are unused @W:CL159 : coreapb3.v(208) | Input PRESETN is unused @W:CL159 : coreapb3.v(210) | Input PCLK is unused @W:CL159 : coreapb3.v(356) | Input PRDATAS1 is unused @W:CL159 : coreapb3.v(363) | Input PRDATAS2 is unused @W:CL159 : coreapb3.v(370) | Input PRDATAS3 is unused @W:CL159 : coreapb3.v(377) | Input PRDATAS4 is unused @W:CL159 : coreapb3.v(384) | Input PRDATAS5 is unused @W:CL159 : coreapb3.v(391) | Input PRDATAS6 is unused @W:CL159 : coreapb3.v(398) | Input PRDATAS7 is unused @W:CL159 : coreapb3.v(405) | Input PRDATAS8 is unused @W:CL159 : coreapb3.v(412) | Input PRDATAS9 is unused @W:CL159 : coreapb3.v(419) | Input PRDATAS10 is unused @W:CL159 : coreapb3.v(426) | Input PRDATAS11 is unused @W:CL159 : coreapb3.v(433) | Input PRDATAS12 is unused @W:CL159 : coreapb3.v(440) | Input PRDATAS13 is unused @W:CL159 : coreapb3.v(447) | Input PRDATAS14 is unused @W:CL159 : coreapb3.v(454) | Input PRDATAS15 is unused @W:CL159 : coreapb3.v(458) | Input PREADYS1 is unused @W:CL159 : coreapb3.v(460) | Input PREADYS2 is unused @W:CL159 : coreapb3.v(462) | Input PREADYS3 is unused @W:CL159 : coreapb3.v(464) | Input PREADYS4 is unused @W:CL159 : coreapb3.v(466) | Input PREADYS5 is unused @W:CL159 : coreapb3.v(468) | Input PREADYS6 is unused @W:CL159 : coreapb3.v(470) | Input PREADYS7 is unused @W:CL159 : coreapb3.v(472) | Input PREADYS8 is unused @W:CL159 : coreapb3.v(474) | Input PREADYS9 is unused @W:CL159 : coreapb3.v(476) | Input PREADYS10 is unused @W:CL159 : coreapb3.v(478) | Input PREADYS11 is unused @W:CL159 : coreapb3.v(480) | Input PREADYS12 is unused @W:CL159 : coreapb3.v(482) | Input PREADYS13 is unused @W:CL159 : coreapb3.v(484) | Input PREADYS14 is unused @W:CL159 : coreapb3.v(486) | Input PREADYS15 is unused @W:CL159 : coreapb3.v(490) | Input PSLVERRS1 is unused @W:CL159 : coreapb3.v(492) | Input PSLVERRS2 is unused @W:CL159 : coreapb3.v(494) | Input PSLVERRS3 is unused @W:CL159 : coreapb3.v(496) | Input PSLVERRS4 is unused @W:CL159 : coreapb3.v(498) | Input PSLVERRS5 is unused @W:CL159 : coreapb3.v(500) | Input PSLVERRS6 is unused @W:CL159 : coreapb3.v(502) | Input PSLVERRS7 is unused @W:CL159 : coreapb3.v(504) | Input PSLVERRS8 is unused @W:CL159 : coreapb3.v(506) | Input PSLVERRS9 is unused @W:CL159 : coreapb3.v(508) | Input PSLVERRS10 is unused @W:CL159 : coreapb3.v(510) | Input PSLVERRS11 is unused @W:CL159 : coreapb3.v(512) | Input PSLVERRS12 is unused @W:CL159 : coreapb3.v(514) | Input PSLVERRS13 is unused @W:CL159 : coreapb3.v(516) | Input PSLVERRS14 is unused @W:CL159 : coreapb3.v(518) | Input PSLVERRS15 is unused @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Sat Aug 28 14:19:51 2010 ###########################################################] Synopsys Actel Technology Mapper, Version map500act, Build 058R, Built Jan 18 2010 09:16:23 Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved Product Version D-2009.12A @N:MF249 : | Running in 32-bit mode. @N:MF258 : | Gated clock conversion disabled @W:MO111 : lab4_mss_tmp_mss_ccc_0_mss_ccc.v(62) | tristate driver RCOSC_CLKOUT on net RCOSC_CLKOUT has its enable tied to GND (module lab4_mss_tmp_MSS_CCC_0_MSS_CCC) @W:MO111 : lab4_mss_tmp_mss_ccc_0_mss_ccc.v(63) | tristate driver MAINXIN_CLKOUT on net MAINXIN_CLKOUT has its enable tied to GND (module lab4_mss_tmp_MSS_CCC_0_MSS_CCC) @W:MO111 : lab4_mss_tmp_mss_ccc_0_mss_ccc.v(64) | tristate driver LPXIN_CLKOUT on net LPXIN_CLKOUT has its enable tied to GND (module lab4_mss_tmp_MSS_CCC_0_MSS_CCC) Automatic dissolve at startup in view:COREAPB3_LIB.CoreAPB3_Z1(verilog) of CAPB3llOI(CAPB3O) Automatic dissolve at startup in view:work.lab4_mss(verilog) of MSS_CCC_0(lab4_mss_tmp_MSS_CCC_0_MSS_CCC) Automatic dissolve at startup in view:work.lab4_top(verilog) of lab4_mss_0(lab4_mss) Automatic dissolve at startup in view:work.lab4_top(verilog) of CoreAPB3_0(CoreAPB3_Z1) Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB) Auto Dissolve of enc3to8wraper_0 (inst of view:work.enc3to8wraper(verilog)) Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 57MB) Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB) Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB) Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB) Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB) High Fanout Net Report ********************** Driver Instance / Pin Name Fanout, notes ---------------------------------------------------------------------------- lab4_mss_0.MSS_ADLIB_INST / M2FRESETn 33 : 32 asynchronous set/reset lab4_mss_0.MSS_ADLIB_INST / MSSPADDR[3] 33 enc3to8wraper_0.led_reg_0_sqmuxa_0_a3 / Y 32 enc3to8wraper_0.un2_rd_enable_i / Y 32 CoreAPB3_0.CAPB3O11_1[0] / Y 34 CoreAPB3_0.CAPB3O11_2[0] / Y 34 ============================================================================ Replicating Combinational Instance CoreAPB3_0.CAPB3O11_2[0], fanout 34 segments 2 Replicating Combinational Instance CoreAPB3_0.CAPB3O11_1[0], fanout 34 segments 2 Replicating Combinational Instance enc3to8wraper_0.un2_rd_enable_i, fanout 32 segments 2 Replicating Combinational Instance enc3to8wraper_0.led_reg_0_sqmuxa_0_a3, fanout 32 segments 2 Buffering lab4_mss_0_FAB_CLK, fanout 65 segments 3 Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) Added 2 Buffers Added 4 Cells via replication Added 0 Sequential Cells via replication Added 4 Combinational Cells via replication Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) Writing Analyst data base Z:\Documents\projects\teaching\eecs373-f10\labs\lab4\files\lab4fpga\synthesis\lab4_top_1.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) Writing EDIF Netlist and constraint files D-2009.12A Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) @W:MT420 : | Found inferred clock lab4_top|lab4_mss_0.MSS_CCC_0.lab4_mss_0_FAB_CLK_inferred_clock with period 1000.00ns. A user-defined clock should be declared on object "n:lab4_mss_0_FAB_CLK" @W:MT246 : lab4_mss.v(50) | Blackbox MSS_APB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) ##### START OF TIMING REPORT #####[ # Timing Report written on Sat Aug 28 14:19:57 2010 # Top view: lab4_top Library name: smartfusion Operating conditions: COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree ) Requested Frequency: 1.0 MHz Wire load mode: top Wire load model: smartfusion Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock.. Performance Summary ******************* Worst slack in design: 992.202 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------------------------------------------ lab4_top|lab4_mss_0.MSS_CCC_0.lab4_mss_0_FAB_CLK_inferred_clock 1.0 MHz 254.6 MHz 1000.000 3.928 996.072 inferred Inferred_clkgroup_0 System 1.0 MHz 181.5 MHz 1000.000 5.509 994.491 system default_clkgroup ======================================================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- lab4_top|lab4_mss_0.MSS_CCC_0.lab4_mss_0_FAB_CLK_inferred_clock lab4_top|lab4_mss_0.MSS_CCC_0.lab4_mss_0_FAB_CLK_inferred_clock | 1000.000 996.072 | No paths - | No paths - | No paths - ========================================================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: lab4_top|lab4_mss_0.MSS_CCC_0.lab4_mss_0_FAB_CLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------- enc3to8wraper_0.led_reg[2] lab4_top|lab4_mss_0.MSS_CCC_0.lab4_mss_0_FAB_CLK_inferred_clock DFN1E1P0 Q led_reg[2] 0.737 996.072 enc3to8wraper_0.led_reg[0] lab4_top|lab4_mss_0.MSS_CCC_0.lab4_mss_0_FAB_CLK_inferred_clock DFN1E1P0 Q led_reg[0] 0.737 996.128 enc3to8wraper_0.led_reg[1] lab4_top|lab4_mss_0.MSS_CCC_0.lab4_mss_0_FAB_CLK_inferred_clock DFN1E1P0 Q led_reg[1] 0.737 996.128 enc3to8wraper_0.led_reg[3] lab4_top|lab4_mss_0.MSS_CCC_0.lab4_mss_0_FAB_CLK_inferred_clock DFN1E1P0 Q led_reg[3] 0.737 997.419 enc3to8wraper_0.led_reg[4] lab4_top|lab4_mss_0.MSS_CCC_0.lab4_mss_0_FAB_CLK_inferred_clock DFN1E1P0 Q led_reg[4] 0.737 997.419 enc3to8wraper_0.led_reg[5] lab4_top|lab4_mss_0.MSS_CCC_0.lab4_mss_0_FAB_CLK_inferred_clock DFN1E1P0 Q led_reg[5] 0.737 997.419 enc3to8wraper_0.led_reg[6] lab4_top|lab4_mss_0.MSS_CCC_0.lab4_mss_0_FAB_CLK_inferred_clock DFN1E1P0 Q led_reg[6] 0.737 997.419 enc3to8wraper_0.led_reg[7] lab4_top|lab4_mss_0.MSS_CCC_0.lab4_mss_0_FAB_CLK_inferred_clock DFN1E1P0 Q led_reg[7] 0.737 997.419 enc3to8wraper_0.led_reg[8] lab4_top|lab4_mss_0.MSS_CCC_0.lab4_mss_0_FAB_CLK_inferred_clock DFN1E1P0 Q led_reg[8] 0.737 997.419 enc3to8wraper_0.led_reg[9] lab4_top|lab4_mss_0.MSS_CCC_0.lab4_mss_0_FAB_CLK_inferred_clock DFN1E1P0 Q led_reg[9] 0.737 997.419 ========================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------- enc3to8wraper_0.PRDATA[2] lab4_top|lab4_mss_0.MSS_CCC_0.lab4_mss_0_FAB_CLK_inferred_clock DFN1E0 D N_8 999.427 996.072 enc3to8wraper_0.PRDATA[0] lab4_top|lab4_mss_0.MSS_CCC_0.lab4_mss_0_FAB_CLK_inferred_clock DFN1E0 D PRDATA_RNO[0] 999.427 996.128 enc3to8wraper_0.PRDATA[1] lab4_top|lab4_mss_0.MSS_CCC_0.lab4_mss_0_FAB_CLK_inferred_clock DFN1E0 D PRDATA_RNO[1] 999.427 996.128 enc3to8wraper_0.PRDATA[3] lab4_top|lab4_mss_0.MSS_CCC_0.lab4_mss_0_FAB_CLK_inferred_clock DFN1E0 D N_10 999.427 997.419 enc3to8wraper_0.PRDATA[4] lab4_top|lab4_mss_0.MSS_CCC_0.lab4_mss_0_FAB_CLK_inferred_clock DFN1E0 D N_12 999.427 997.419 enc3to8wraper_0.PRDATA[5] lab4_top|lab4_mss_0.MSS_CCC_0.lab4_mss_0_FAB_CLK_inferred_clock DFN1E0 D N_14 999.427 997.419 enc3to8wraper_0.PRDATA[6] lab4_top|lab4_mss_0.MSS_CCC_0.lab4_mss_0_FAB_CLK_inferred_clock DFN1E0 D N_16 999.427 997.419 enc3to8wraper_0.PRDATA[7] lab4_top|lab4_mss_0.MSS_CCC_0.lab4_mss_0_FAB_CLK_inferred_clock DFN1E0 D N_18 999.427 997.419 enc3to8wraper_0.PRDATA[8] lab4_top|lab4_mss_0.MSS_CCC_0.lab4_mss_0_FAB_CLK_inferred_clock DFN1E0 D N_20 999.427 997.419 enc3to8wraper_0.PRDATA[9] lab4_top|lab4_mss_0.MSS_CCC_0.lab4_mss_0_FAB_CLK_inferred_clock DFN1E0 D N_22 999.427 997.419 =========================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 1000.000 - Setup time: 0.573 + Clock delay at ending point: 0.000 (ideal) = Required time: 999.427 - Propagation time: 3.354 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 996.072 Number of logic level(s): 1 Starting point: enc3to8wraper_0.led_reg[2] / Q Ending point: enc3to8wraper_0.PRDATA[2] / D The start point is clocked by lab4_top|lab4_mss_0.MSS_CCC_0.lab4_mss_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by lab4_top|lab4_mss_0.MSS_CCC_0.lab4_mss_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------ enc3to8wraper_0.led_reg[2] DFN1E1P0 Q Out 0.737 0.737 - led_reg[2] Net - - 1.669 - 9 enc3to8wraper_0.PRDATA_RNO[2] NOR2B B In - 2.405 - enc3to8wraper_0.PRDATA_RNO[2] NOR2B Y Out 0.627 3.033 - N_8 Net - - 0.322 - 1 enc3to8wraper_0.PRDATA[2] DFN1E0 D In - 3.354 - ================================================================================================ Total path delay (propagation time + setup) of 3.928 is 1.938(49.3%) logic and 1.990(50.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------- lab4_mss_0.MSS_ADLIB_INST System MSS_APB MSSPADDR[3] lab4_mss_0_MSS_MASTER_APB_PADDR_\[3\] 0.000 992.202 lab4_mss_0.MSS_ADLIB_INST System MSS_APB MSSPADDR[8] lab4_mss_0_MSS_MASTER_APB_PADDR_\[8\] 0.000 992.266 lab4_mss_0.MSS_ADLIB_INST System MSS_APB MSSPADDR[11] lab4_mss_0_MSS_MASTER_APB_PADDR_\[11\] 0.000 992.294 lab4_mss_0.MSS_ADLIB_INST System MSS_APB MSSPSEL lab4_mss_0_MSS_MASTER_APB_PSELx 0.000 992.318 lab4_mss_0.MSS_ADLIB_INST System MSS_APB MSSPADDR[10] lab4_mss_0_MSS_MASTER_APB_PADDR_\[10\] 0.000 992.433 lab4_mss_0.MSS_ADLIB_INST System MSS_APB MSSPADDR[9] lab4_mss_0_MSS_MASTER_APB_PADDR_\[9\] 0.000 992.494 lab4_mss_0.MSS_ADLIB_INST System MSS_APB M2FRESETn lab4_mss_0_M2F_RESET_N 0.000 993.947 lab4_mss_0.MSS_ADLIB_INST System MSS_APB MSSPADDR[2] lab4_mss_0_MSS_MASTER_APB_PADDR_\[2\] 0.000 994.449 lab4_mss_0.MSS_CCC_0.I_RCOSC System RCOSC CLKOUT N_CLKA_RCOSC 0.000 994.491 lab4_mss_0.MSS_ADLIB_INST System MSS_APB MSSPWRITE CoreAPB3_0_APBmslave0_PWRITE 0.000 994.915 ======================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------- enc3to8wraper_0.PRDATA[0] System DFN1E0 E N_6_0 999.392 992.202 enc3to8wraper_0.PRDATA[1] System DFN1E0 E N_6_0 999.392 992.202 enc3to8wraper_0.PRDATA[2] System DFN1E0 E N_6 999.392 992.202 enc3to8wraper_0.PRDATA[3] System DFN1E0 E N_6 999.392 992.202 enc3to8wraper_0.PRDATA[4] System DFN1E0 E N_6 999.392 992.202 enc3to8wraper_0.PRDATA[5] System DFN1E0 E N_6 999.392 992.202 enc3to8wraper_0.PRDATA[6] System DFN1E0 E N_6 999.392 992.202 enc3to8wraper_0.PRDATA[7] System DFN1E0 E N_6 999.392 992.202 enc3to8wraper_0.PRDATA[8] System DFN1E0 E N_6 999.392 992.202 enc3to8wraper_0.PRDATA[9] System DFN1E0 E N_6 999.392 992.202 ============================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 1000.000 - Setup time: 0.608 + Clock delay at ending point: 0.000 (ideal) = Required time: 999.392 - Propagation time: 7.190 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (critical) : 992.202 Number of logic level(s): 2 Starting point: lab4_mss_0.MSS_ADLIB_INST / MSSPADDR[3] Ending point: enc3to8wraper_0.PRDATA[2] / E The start point is clocked by System [rising] The end point is clocked by lab4_top|lab4_mss_0.MSS_CCC_0.lab4_mss_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------ lab4_mss_0.MSS_ADLIB_INST MSS_APB MSSPADDR[3] Out 0.000 0.000 - lab4_mss_0_MSS_MASTER_APB_PADDR_\[3\] Net - - 2.720 - 33 enc3to8wraper_0.un2_rd_enable_i_a2 NOR2 A In - 2.720 - enc3to8wraper_0.un2_rd_enable_i_a2 NOR2 Y Out 0.363 3.083 - N_139 Net - - 1.184 - 4 enc3to8wraper_0.un2_rd_enable_i OR3B C In - 4.267 - enc3to8wraper_0.un2_rd_enable_i OR3B Y Out 0.751 5.018 - N_6 Net - - 2.172 - 16 enc3to8wraper_0.PRDATA[2] DFN1E0 E In - 7.190 - ============================================================================================================ Total path delay (propagation time + setup) of 7.798 is 1.722(22.1%) logic and 6.076(77.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] -------------------------------------------------------------------------------- Target Part: A2F200M3F_FBGA256_Std Report for cell lab4_top.verilog Core Cell usage: cell count area count*area BUFF 2 1.0 2.0 GND 7 0.0 0.0 MSS_APB 1 0.0 0.0 MSS_CCC 1 0.0 0.0 MX2 2 1.0 2.0 NOR2 3 1.0 3.0 NOR2B 30 1.0 30.0 NOR3A 2 1.0 2.0 NOR3B 1 1.0 1.0 NOR3C 35 1.0 35.0 OR3 1 1.0 1.0 OR3A 3 1.0 3.0 OR3B 5 1.0 5.0 OR3C 1 1.0 1.0 RCOSC 1 0.0 0.0 VCC 7 0.0 0.0 DFN1E0 32 1.0 32.0 DFN1E1P0 32 1.0 32.0 ----- ---------- TOTAL 166 149.0 IO Cell usage: cell count INBUF 2 INBUF_MSS 1 OUTBUF 8 ----- TOTAL 11 Core Cells : 149 of 4608 (3%) IO Cells : 11 of 66 (17%) RAM/ROM Usage Summary Block Rams : 0 of 8 (0%) Mapper successful! Process took 0h:00m:02s realtime, 0h:00m:01s cputime # Sat Aug 28 14:19:57 2010 ###########################################################]