IEEE, AVS, and ECS
Fellow
University of Michigan
Department of Electrical Engineering and Computer Science
2304 EECS Building
1301 Beal Avenue
Ann Arbor, MI 48109-2122
Telephone: (734) 936-2962
Fax: (734) 763-9324
Email: pang@umich.edu
Associate Dean for Graduate Education
2105 LEC Building
1221 Beal Avenue
Ann Arbor, MI 48109-2102
Telephone: (734) 647-7090
Fax: (734) 647-7045
Education
Ph.D., Department of
Electrical Engineering and Computer Science (Electronic Materials
and Devices), Princeton University, Princeton, NJ 08544. (1981).
MSc., Electrical Engineering
and Computer Science, Princeton University, Princeton, NJ 08544.
(1978).
ScB., Electrical and
Computer Engineering, Brown University, Providence, RI. (1977).
Research Interest
Nanofabrication Technology, Dry Etching,
Dry Deposition, Microelectronic, Optical, and Microelectromechanical
Devices
Research Projects
Research areas include nanofabrication
technology, plasma etching and deposition technology, process
induced damage, micromachining technology and devices, field emission
devices, and quantum effect devices. High-resolution patterning
and plasma processing are used to generate devices with features
below 100 nm. Plasma process induced defects are identified and
techniques to minimize, remove, and passivate damage have been
developed. Novel techniques in micromachining are developed to
create high sensitivity and high frequency resonators and sensors
with merged circuits. Optical switching arrays in Si are formed
using vertical Si micromirrors and high aspect ratio resonators.
Uniform arrays of gated Si field emission devices are fabricated
with sharp emitters and close gate-tip spacing. These high efficiency
field emitters have low threshold voltage and high emission current,
especially after plasma passivation or HfC coating. Controllable
and low damage dry etching technology is applied to single electron
transistors, in-plane gated quantum wire transistors, heterojunction
bipolar transistors, optical waveguides and mirrors with high
performance.
- Identify process induced
defects and relate changes in electrical characteristics to optical
responses. Develop novel techniques to minimize or passivate
damage to provide substantial performance improvements. Model
and control defect generation and distribution in Si and III-V
devices.
- Develop and characterize
quantum effect devices including single electron transistors,
in-plane gated quantum wire transistors and quantum wires/dots
for lasers and waveguides. Patterning and etching technologies
are developed to fabricate high quality devices down to 20 nm.
- Develop direct nano-printing
technology in metal and polymer using SiC molds for high resolution
and high throughput patterning. This is the first demonstration
that nanostructures down to 20 nm can be printed in metal repeatedly
using a SiC mold.
- Develop novel micromachining
technology to fabricate thick resonators with higher sensitivity.
With this new technology, device thickness is no longer limited
and the process is simplified significantly since bonding to
glass is not needed and it requires only 1 mask level.
- Implementation of merged
MEMS devices with on-chip circuits using thick (>10 µm)
single crystal Si microstructures without bonding to glass or
another wafer. Without bonding, the process is simplified significantly.
The thick single crystal Si also provides higher sensitivity
and higher quality factor.
- Demonstration of vertical
mirrors and lenses in Si that can be controlled by integrated
electrostatic drivers. Optical switching arrays with Si vertical
mirrors were fabricated with large modulations of the optical
signals at low power.
- Develop new technology for
self-aligned field emitter arrays with sharp emitters and close
gate-tip spacings. Emitters with radius of 8 nm and density >107
tips/cm2 have been demonstrated. Low turn-on voltage (16 V),
high emission current (6 µA/tip), and good stability (±0.25%)
were obtained which are substantially better than previously
reported results.
- Develop low damage emitter
etch and precise end point techniques for self-aligned HBTs.
Emitter etching is stopped within 5 nm with low damage and high
device performance.