Mikhail Smelyanskiy's Home Page

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About Me

I am a Principal Engineer at Intel's Parallel Computing Lab, part of Intel Research Labs in Santa Clara, CA. My main focus is on application-driven parallel architecture research. Specifically, my work involves design, implementation and analysis (including competitive analysis) of parallel algorithms and workloads for the current and future generation parallel processor systems. In my work I take a top-down approach: (i) designing fastest algorithm, (ii) mapping this algorithm to the underlying hardware architecture, (iii) modeling and analyzing the performance (using cycle-accurate performance simulators if needed) to discover and explain performance bottlenecks. This results in architectural recommendations and proposals to drive the design of Intel future parallel architectures, as well as highly optimized (down to 'bare-metal ') workload implementations on existing systems. For the list of my publications, please see 'List of Publications' below.

I made significant contribution to the definition of Intel® Many-Integrated Core (MIC) architecture and the development of the Intel® Xeon Phi™ coprocessor. My research in the areas of medical imaging, computational finance and more recently in fundamental high performance compute kernels, such as DGEMM (double precision matrix-matrix multiplication), SpMVM (sparse matrix-vector multiplication) and QCD (quantum chromodynamics), helped improve MIC architecture, as well as demonstrate its full performance potential.

I was Intel technical lead behind top(#1)-ranked position in Green500, November 2012. The record was set by MIC-based Beacon system built at National Institute for Computational Sciences. Green500 provides a ranking of the 500 most energy-efficient supercomputers in the world. I was also Intel technical lead behind the very first MIC-based submission to the TOP500, which ranked number 150 in June 2012. TOP500 provides a ranking of the 500 fastest computers in the world. My highly optimized double-precision matrix-matrix multiplication (DGEMM) implementation running on single-chip Intel® Xeon Phi™ sustained performance of over 1 TeraFLOP/s (1012 floating-point computations per second) in November 2011 – at the time, the world's fastest DGEMM, and the first to go above one TeraFLOP/s.  I received Intel Achievement Award, Intel's highest honor, in 2012.

Prior to my work at Intel, I earned Ph.D. from the Department of Electrical Engineering and Computer Science at the University of Michigan, Ann Arbor in 2003. My academic advisors were Professor Edward Davidson and Professor Scott Mahlke. The focus of my thesis work was on hardware/software co-design and compiler optimizations for efficient resource utilization on VLIW architectures.

Contact Infromation

Mikhail Smelyanskiy, Ph.D.
Intel Corporation
2200 Mission College Blvd., SC-12
Santa Clara, CA 95054
Email:     mikhail.smelyanskiy@intel.com
Linkedin: View Misha Smelyanskiy's profile on LinkedIn
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List of Publications

2007 & Older