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Research Projects

Flynn Research Group projects.


Brain Prostheses
Deep brain stimulation (DBS) of the subthalamic nucleus is an effective therapy for numerous neurological disorders including Parkinson's disease, which affects more than 1.5m people in the US. However current treatment systems require monthly or weekly adjustment by trained clinicians. Despite more than a decade of research, effective closed-loop optimization of stimulation parameters, which would greatly improve the treatment of the neurological disorders, remains elusive. Recently several SoCs incorporating both neural recording and stimulation have been described. Spike sorting and principal component analysis (PCA) can disentangle spikes, this approach is not effective for closed-loop DBS. Moreover spike sorting with PCA requires significant computation making RF powered or even long-term battery powered operation difficult.
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A complete receiver demo based on Michigan's flexible receiver IC.
A complete wireless receiver system combines a custom multi-band, multi-standard 65nm CMOS receiver IC with a real-time baseband demodulator on an FPGA to create a full-functioning wireless demonstration system. The demonstration showcases a system built around a highly-integrated receiver IC that captures a RF input and outputs digital baseband bitstreams. The wideband front-end and SAR ADC with embedded configurable discrete-time (DT) filters ("SARfilter ADC") of the receiver IC allow it to adapt to its environment and to different communication standards. The performance of this receiver is verified with both the 915MHz and 2450MHz bands of IEEE 802.15.4 and IEEE 802.11. A custom digital baseband demodulator implemented on a FPGA performs real-time digital phase correction, symbol timing acquisition, and demodulation of 802.15.4 2450MHz band packets. Additional custom FPGA logic interfaces the demodulator to a video driver, in order to create a complete hardware demonstration system that receives, demodulates, and displays images.
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Noise Shaping SAR ADCs
In recent years, charge-redistribution SAR (Successive Approximation) ADCs have exhibited the highest conversion efficiencies for ADCs with moderate resolution and bandwidth. For effective resolutions beyond 10 bits or so, however, the accuracy of the SAR circuit blocks limits the overall energy efficiency of the converter. At high resolutions, for instance, the DAC voltages become small compared to the input-referred noise of a dynamic comparator, necessitating an additional power-hungry, low-noise pre-amplifier to drive the comparator. To improve the resolutions of SAR ADCs, this work introduces a technique to decouple the accuracy of the comparator from the resolution of the ADC.
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Hybrid SAR Pipeline ADC
SAR ADC architectures are popular for achieving high energy efficiency but they suffer from resolution and speed limitations. On the other hand pipeline ADC architectures can achieve high resolution and speed but have lower energy-efficiency and are more complex. We propose a two-stage pipeline ADC architecture with a large first-stage resolution, enabled with the help of a SAR-based sub-ADC. The prototype 12b 50MS/s ADC achieves an ENOB of 10.4b at Nyquist, and an FOM of 52fJ/conversion-step. The ADC achieves low-power, high-resolution and high-speed operation without calibration. The ADC is fabricated in 65nm and 90nm CMOS and occupies a core area of only 0.16mm2.
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Compressive Sensing
New theory and techniques for processing information received from wireless sensor networks are being investigated for the ultimate purpose of monitoring the nation's infrastructure, including bridges, buildings and related construction. Named, "Sensing Sensors: Compressed Sampling with Co-design of Hardware and Algorithms across Multiple Layers in Wireless Sensor Networks," this new five year, $3M multi-disciplinary research program funded by the National Science Foundation includes a diverse team of faculty in the areas of circuits (Prof. Michael Flynn, Principle Investigator, and Prof.David Wentzloff), systems (Profs. Mingyan Liu and Wayne Stark), mathematics (Prof. Anna Gilbert) and civil and environmental engineering (Prof. Jerry Lynch).
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Hybrid Sigma-Delta Pipeline ADCs
Hybrid Sigma-Delta Pipeline ADCs offer the accuracy of noise-shaping ADCs along with the speed and Nyquist sampling of pipeline ADCs. Current state-of-the-art CMOS integrated circuit (IC) processes are ideally suited to implementing digital circuits; but they do not deliver the precision and accuracy required for high-resolution analog design. This is because the transistors have poor analog properties (such as linearity and gain) and the shrinking of the supply voltage makes the matter worse. The Analog-to-Digital Converter (ADC) is a key analog component in most applications. Thus, new techniques need to be developed to design ADCs in these new IC processes. Furthermore, the performance requirements (in terms of resolution, speed, and power) of such ADCs also increase with newer applications. This work involves the use of oversampling techniques to trade speed for accuracy. Sigma-delta (or oversampling) ADCs have been used traditionally for low-bandwidth, high-accuracy applications, and trading speed for accuracy.
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End of the CMOS Scaling Roadmap ADCs
Our goal is to investigate new approaches to analog-to-digital conversion that are suited for end-of-the-roadmap CMOS, and which also deliver orders-of-magnitude improvements in speed and energy efficiency. We break analog-to-digital conversion down to its essence and simplify the process of analog-to-digital conversion to its most basic form. This allows us to take advantage of the tremendous digital capability of nanometer processes and then implement the analog circuitry in the simplest way. We propose an ADC structure that is comprised of low-precision comparators aided by digital processing. The architecture incorporates redundancy to cancel mismatch and offset. This project is supported by Intel Corporation.
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Low-Power Mostly-Digital Transmitters for Sensor Networks
The aim of this research is to develop a new architecture for a wireless transmitter with an emphasis on performing much of the analog functions in the digital domain. The proposed transmitter architecture performs direct modulation by varying a phase-locked loop (PLL) divide ratio.
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Bandpass Sigma-Delta ADCs
A continuous-time bandpass ∑∆ modulator (CTBPSDM) is a good solution for software-defined-radio (SDR) since it allows much flexibility in digital backend and also decreases the complexity of the receiver chain by combining several analog blocks into a single ADC. However, conventional CTBPSDMs suffer from large power consumption and occupy large area. CTBPSDMs based on LC are large, while biquad-based resonators are also large and suffer from high power consumption because two amplifiers are usually required in each resonator. The fact that there are typically twice as many feedback paths compared to a lowpass ∑∆ modulator with the same bandwidth and performance also increases power consumption, area and complexity. This paper presents a novel power-efficient resonator with a single amplifier and also introduces a simplified architecture utilizing return-to-zero (RZ) and half-clock-delayed return-to-zero (HZ) pulses to solve the power and complexity problems.
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Very Low Power Pulse Position Modulation (PPM) ADC in 90nm CMOS Technology
Reducing the power consumption and chip area of analog-to-digital converters is a big challenge in todays research since analog-to-digital converters are key building blocks in all communication, sensing, and imaging systems.
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A Fully Integrated CMOS Receiver
The rapidly growing wireless communication market is creating a growing demand for radio frequency (RF) transceivers. To minimize size and cost, more and more RF bands and standards have been integrated onto a single chip. This project focuses on developing a wireless solution, which is highly integrated, that is small in size, and that requires very low power. This research targets applications such as implantable neuroprosthetic devices, and environmental wireless sensors, which require short range, low data-rate, but long lifetime wireless connectivity.
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Fully Integrated CMOS Super-Regenerative Radios
A multi-channel 2.4-GHz ISM band super-regenerative receiver implemented in 130 nm CMOS.
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Remotely Powered Wireless Telemetry
We present a transponder architecture for long range, remotely powered, sensor telemetry applications. Power and a reference clock are recovered from a 450 MHz incident RF signal, and data is modulated on a 900 MHz carrier.
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20Gbps+ on Chip Data Links
This project proposes new scheme for long-range (~10 mm) on-chip, digital signaling in a conventional digital CMOS process. Unlike other schemes, there is no requirement for up-conversion, equalization, or special metal processing. Prototype links are faster and more energy efficient than conventional parallel busses.
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Digitally Calibrated Moderate Resolution ADCs
This work involves developing digital calibration techniques for folding analog-to-digital converters. According to the 2001 International Technology Roadmap for Semiconductors, improved ADC technology is a key factor in developing present and future applications.
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Electrical Engineering and Computer Science
2417F EECS
1301 Beal Avenue
Ann Arbor, MI 48109-2122
Phone: 734-936-2966
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