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Journal Publications

  1. H. Chae and M.P. Flynn, "A 69dB SNDR, 25MHz BW, 800MS/s Continuous-time Bandpass ΔΣ Modulator Using a Duty-cycle-controlled DAC for Low Power and Re- configurability," IEEE Journal of Solid-State Circuits, In Press, 2016.

  2. A. E. Mendrela, J. Cho, J. A. Fredenburg, M. P. Flynn, and E. Yoon, "A Bidirectional Neural Interface Circuit With Active Stimulation Artifact Cancellation and Cross-Channel Common-Mode Noise Suppression," IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol.PP, no.99, pp.1-11 January, 2016.

  3. J. Jeong, N. Collins, and M. P. Flynn, "”A 260 MHz IF Sampling Bit-Stream Processing Digital Beamformer with an Integrated Array of Continuous-Time Band-Pass ΔΣ Modulators," IEEE Journal of Solid-State Circuits, May, 2016.

  4. Yong Lim; M. P. Flynn, " A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring Amplifiers," IEEE Journal of Solid State Circuits, Volume: 50, Issue: 10 Pages: 2331 - 2341, DOI:10.1109/JSSC.2015.2453332, 2015.

  5. Yong Lim , Flynn, M.P., "A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC," IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 50, No. 12, December, 2015.

  6. Hyungil Chae, Jaehun Jeong, Manganaro, G. Flynn, M.P., "A 12 mW Low Power Continuous-Time Bandpass ΔΣ Modulator With 58 dB SNDR and 24 MHz Bandwidth at 200 MHz IF," IEEE Journal of Solid-State Circuits, (Volume:49 , Issue: 2), pp. 405-415, December 11, 2014.

  7. Hyo-Gyuem Rhew, Jaehun Jeong, Jeffrey A. Fredenburg, Student Member, IEEE, Sunjay Dodani, Parag G. Patil, and Michael P. Flynn, Senior Member, IEEE , "A Fully Self-Contained Logarithmic Closed-Loop Deep Brain Stimulation SoC With Wireless Telemetry and Wireless Power Management," IEEE Journal of Solid-State Circuits, (Volume:PP , Issue: 99 ), pp. 1-15, August 28, 2014.

  8. D.T. Lin, H. Chae, L. Li and M.P. Flynn, "A Low-Power Adaptive Receiver Utilizing Discrete-Time Spectrum-Sensing," IEEE Transactions on Microwave Theory and Techniques, vol.47, no.12, pp.2898-2904, December, 2013.

  9. Hyungil Chae, Li Li, Flynn, M.P., "A Low-Power Adaptive Receiver Utilizing Discrete-Time Spectrum-Sensing," IEEE Transactions on Microwave Theory and Techniques, (Volume:61 Issue: 3), pp. 1338-1346 February 12, 2013.

  10. J. A. Fredenburg and M. P. Flynn, "A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC," IEEE Journal of Solid-State Circuits, vol.47, no.12, pp.2898-2904, December, 2012.

  11. D. Lin, L. Li, S. Farahani, and M.P. Flynn , "A Flexible 500 MHz to 3.6 GHz Wireless Receiver with Configurable DT FIR and IIR Filter Embedded in a 7b 21 MS/s SAR ADC," IEEE Transactions on Circuits and Systems I, December, 2012.

  12. P. K. Yenduri, A. Z. Rocca, A. S. Rao, S. Naraghi, M. P. Flynn and A. C. Gilbert, "A Low-Power Compressive Sampling Time-Based Analog-to-Digital Converter," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol.2, no.3, pp.502-515, September, 2012.

  13. J. A. Fredenburg and M. P. Flynn, "Statistical Analysis of ENOB and Yield in Binary Weighted ADCs and DACS with Random Element Mismatch," IEEE Transactions on Circuits and Systems I, pp.1-13, December , 2012.

  14. J. Pernillo and M. P. Flynn, "A 1.5GS/s Flash ADC with 57.7dB SFDR & 6.4b ENOB in 90nm Digital CMOS," IEEE Transactions on Circuits and Systems II, pp.837-841, December , 2011.

  15. C. C. Lee and M. P. Flynn, "A 14b 23MS/s 48mW Resetting SD ADC with 87db SFDR 11.7b ENOB & 0.5mm2 Area," (TCAS1) IEEE Transactions on Circuits and Systems I, Vol. 58, (6), pp. 1167-1177, June , 2011.

  16. Fredenburg, J.A. ; Flynn, M.P., "Statistical Analysis of ENOB and Yield in Binary Weighted ADCs and DACS With Random Element Mismatch," IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, Vol. 59, No. 7, pp. 1396-1408, July, 2011.

  17. S. Naraghi, M. Courcy, and M. P. Flynn, "A 9-bit, 14μW and 0.06 mm2 Pulse Position Modulation ADC in 90nm digital CMOS," IEEE Journal of Solid-State Circuits, September , 2010.

  18. J. Lee, J. Kang, S. Park, J. Seo, J. Anders, J. Guilhereme and M. P. Flynn, "A 2.5mW 80dB DR 36dB SNDR 22MS/s Logarithmic Pipeline ADC," IEEE Journal of Solid State Circuits, October , 2009.

  19. S. Park, Y. Palaskas and M. P. Flynn, "A 4 GS/s 4 bit Flash ADC in 0.18 μm CMOS," IEEE Journal of Solid-State Circuits, Vol. 42, No. 9, pp. 1865-1872, September , 2009.

  20. J. Park, J. Kang, S. Park, and M. P. Flynn, "A 9Gbit/s Serial Transceiver for On-chip Global Signaling over Lossy Transmission Lines," IEEE Transactions on Circuits and Systems I, October , 2009.

  21. M. Ferriss and M. P. Flynn, "A 14mW Fractional-N PLL modulator with a digital phase detector and frequency switching scheme," IEEE Journal of Solid-State Circuits, Vol. 43, No. 11, pp. 2464-2471, November , 2008.

  22. S. Park, Y. Palaskas and M. P. Flynn, "A 4 GS/s 4 bit Flash ADC in 0.18 μm CMOS," IEEE Journal of Solid-State Circuits, Vol. 42, No. 9, pp. 1865-1872, September , 2007.

  23. J. Chen, M. P. Flynn, and J. Hayes, "A Fully Integrated Auto-Calibrated Super-Regenerative Receiver in 0.13μm CMOS," IEEE Journal of Solid-State Circuits, Vol. 42, No. 9, pp. 1976-1985, September , 2007.

  24. J. Chen, M. P. Flynn, and J. Hayes, "A Fully Integrated Auto-Calibrated Super-Regenerative Receiver in 0.13μm CMOS," IEEE Journal of Solid-State Circuits, Vol. 42, No. 9, pp. 1976-1985, September , 2007.

  25. F. Kocer and M. P. Flynn, "A New Transponder Architecture with On-Chip ADC for Long-Range Telemetry Applications," IEEE Journal of Solid-State Circuits, vol. 41, no. 5, pp. 1142-1148, May , 2006.

  26. S. Park and M. P. Flynn, "A Regenerative Comparator Structure with Integrated Inductors," IEEE Transactions on Circuits and Systems I, vol. 53 no. 8, pp. 1704-1711, August , 2006.

  27. F. Kocer and M. P. Flynn, "An RF Powered, Wireless CMOS Temperature Sensor," IEEE Sensors Journal, vol. 6, no. 3, June 2006, pp. 557-64, June, 2006.

  28. M. P. Flynn, S. Park, and C. C. Lee, "Achieving Analog Accuracy in nanometer CMOS," International Journal of High Speed Electronics and Systems, vol. 5, no. 2, pp. 255-275, 2005.

  29. M. P. Flynn, C. Donovan, and L. Sattler, "Digital Calibration Incorporating Redundancy of Flash ADCs," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 50, no. 5, pp. 205-214, May , 2003.

  30. C. Donovan and M. P. Flynn, "A ‘Digital’ 6-bit ADC in 0.25m CMOS," IEEE Journal of Solid-State Circuits, pp. 432-437, March , 2002.

  31. D. J. Foley and M. P. Flynn, "A Low-power 8-PAM Serial Transceiver in 0.5m digital CMOS," IEEE Journal of Solid-State Circuits, pp. 310-316, March , 2002.

  32. D. J. Foley and M. P. Flynn, "CMOS DLL Based 2V, 3.2ps Jitter, 1GHz Clock Synthesizer and Temperature-Compensated Tunable Oscillator," IEEE Journal of Solid-State Circuits, pp. 417-423, March , 2001.

  33. M. P. Flynn and S. Lidholm, "A 1.2 um CMOS current controlled oscillator," IEEE Journal of Solid-State Circuits, Vol. 27, No. 7, pp. 982-987, July, 1992, .

  34. M. P. Flynn and B. Sheahan, "A 400MSample/s 6b CMOS Folding and interpolating ADC," IEEE Journal of Solid-State Circuits, Vol. 33, no. 12, pp. 1932-1938, December 1998, .

  35. M.P. Flynn and D.J. Allstot, "CMOS folding ADCs with Current-mode Interpolation," IEEE Journal of Solid-State Circuits, Vol. 31, no. 9, pp. 1248-1257, September 1996, .

Conference Proceedings

  1. M. Batuhan Dayanik, N. Collins and M. P. Flynn, "A 28.5 – 33.5GHz Fractional-N PLL Using a 3rd Order Noise Shaping Time-to-Digital Converter with 176fs Resolution," European Solid-State Circuits Conference (ESSCIRC), September, 2016.

  2. K. D. Choo, J. Bell, M. P. Flynn, "Area-Efficient 1GS/s 6b SAR ADC with Charge-Injection-Cell-Based DAC," IEEE International Solid State Circuits Conf. (ISSCC), February, 2016.

  3. A. Tanner, T. Gaier, B. Lambrigtsen, P. Kangaslahti, I. Ramos-Perez, M. P. Flynn, Z.Zhang, D. Austerberry, C. Ruf, D. McKague, "GeoSTAR System design and Development Update," MicroRad, April, 2016.

  4. M. M, Ghahramani, Y. Rajavi, A. Khalili, A. Kavousian,B. Kim, and M. P. Flynn, "A 192MHz Differential XO Based Frequency Quadrupler with Sub-Picosecond Jitter in 28nm CMOS," IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June, 2015.

  5. Yong Lim, M. P. Flynn, "A 1mW 71.5dB SNDR 50MS/S 13b fully differential ring-amplifier-based SAR-assisted pipeline ADC," Solid- State Circuits Conference - (ISSCC), IEEE International, 2015.

  6. J. Fredenburg and M. P. Flynn, "ADC Trends and Impact on SAR ADC Architecture and Analysis," Custom Integrated Circuits Conference , September, (Invited), 2015.

  7. Jaehun Jeong, Collins, N. , Flynn, M.P., "An IF 8-element 2-beam bit-stream band-pass beamformer," Radio Frequency Integrated Circuits Symposium (RFIC), May, 2015.

  8. Mendrela, A.E. ; Jihyun Cho ; Fredenburg, J.A. ; Chestek, C.A. ; M.P. Flynn; Euisik Yoon, "Enabling closed-loop neural interface: A bi-directional interface circuit with stimulation artifact cancellation and cross-channel CM noise suppression," , Symposium on VLSI Circuits (VLSI Circuits), 2015.

  9. Yong Lim, Michael P. Flynn, "A 100MS/s 10.5b 2.46mW comparator-less pipeline ADC using self-biased ring amplifiers," Solid-State Circuits Conference Digest of Technical Papers, 2014 IEEE International Solid State Circuits Conf.(ISSCC), February, 2014.

  10. Chunyang Zhai, Jeffrey Fredenburg, John Bell, and Michael P. Flynn, "An N-path filter enhanced low phase noise ring VCO," 2014 Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, HW, June, 2014.

  11. Hyungil Chae, Flynn, M.P., "A 69dB SNDR, 25MHz BW, 800MS/s continuous-time bandpass ΔΣ ADC using DAC duty cycle control for low power and reconfigurability," 2013 Symposium on VLSI Circuits (VLSIC), IEEE Journal of Solid-State Circuits, (Volume:49 , Issue: 2), pp. 405-415, December 11, 2013.

  12. Jorge Pernillo and Michael P. Flynn, "A 9b 2GS/s 45mW 2X-interleaved ADC," 2013 Proceedings of the ESSCIRC (ESSCIRC) , pp. 125-128, 16-20 Sept. , 2013.

  13. H. Chae, J. Jeong, G. Manganaro and M. P. Flynn, "A 12mW Low Power Continuous-time Bandpass ∑∆ Modulator with 58dB SNDR and 24MHz Bandwidth at 200MHz IF," IEEE International Solid State Circuits Conf.(ISSCC), February, 2012.

  14. H. Rhew, J. Park and M.P. Flynn, "A 22Gb/s, 10mm On-Chip Serial Link over Lossy Transmission Line with Resistive Termination," European Solid-State Circuits Conference (ESSCIRC), September , 2012.

  15. L. Li, M. A. Ferriss, and M. P. Flynn, "A 5.8GHz Digital Arbitrary Phase-Setting Type II PLL in 65nm CMOS with 2.25deg Resolution," Asia Solid-State Circuits Conference (ASSCC), November, 2012.

  16. J. Fredenburg, and M. P. Flynn, "A 90MS/s 11MHz Bandwidth 62dB SNDR Noise-shaping SAR ADC," (ISSCC) IEEE International Solid-State Circuits Conference, San Francisco, CA, pp. 468-469, February, 2012.

  17. J. Pernillo and M. P. Flynn, "A 9b 1GS/S 27mW Two-Stage Pipeline ADC in 45nm SOI-CMOS," Asia Solid-State Circuits Conference (ASSCC), November , 2012.

  18. M. Ghahramani, M. Taghivand and M. P. Flynn, "A Low Voltage Sub 300uW 2.5GHz Current Reuse VCO," Asia Solid-State Circuits Conference (ASSCC), November, 2012.

  19. 5. H. Rhew, J. Jeong, J.A. Fredenburg, S. Dodani, P. Patil, M.P. Flynn, "A Wirelessly Powered Log-based Closed-loop Deep Brain Stimulation SoC with RF telemetry for Treatment of Neurological Disorders," IEEE Symposium on VLSI Circuits, June, 2012.

  20. H. G. Rhew, J. Jeong, J. A. Fredenburg, S. Dodani, P. Patil, and M. P. Flynn, "A Wirelessly Powered Log-based Closed-loop Deep Brain Stimulation SoC with Two-way Wireless Telemetry for Treatment of Neurological Disorders," VLSI Symposium on VLSI Circuits, Honolulu, HI, June, 2012.

  21. M. H. Ghaed, M. M. Ghahramani, G. Chen, M. Fojtik, D. Blaauw, M. P. Flynn, and D. Sylvester, "Low Power Wireless Sensor Networks for Infrastructure Monitoring," SPIE, San Diego, CA, vol. 8347, pp. 83470U, March (Invited), 2012.

  22. M. Ghahramani, M. Ferriss, and M. P. Flynn, "A 2.4GHz 2Mb/s digital PLL-based transmitter for 802.15.4 in 130nm CMOS," Radio Frequency Integrated Circuits Symposium (RFIC), 2011 IEEE, June , 2011.

  23. D. Lin, L. Li, S. Farahani, and M.P. Flynn, "A 600MHz to 3.4GHz flexible spectrum-sensing receiver with spectrum-adaptive reconfigurable DT filtering," RFIC, June, 2011.

  24. 10. T. Gaier, B. Lambrigtsen, P. Kangaslahti, B. Lim, A. Tanner, D. Harding, H. Owen, M. Soria, I. O'Dwyer, C. Ruf, R. Miller, B. Block, M. Flynn, S. Whitaker , "Geostar-II: A Prototype water vapor imager/sounder for the path mission," IEEE International Geoscience and Remote Sensing Symposium, August, 2011.

  25. D. Lin, M. Ghahramani, and L. Li, and M. P. Flynn, "New Techniques for Efficient Flexible Wireless Transceivers in Nanometer CMOS," SPIE Annual Meeting, Orlando, FL, April , 2011.

  26. P. K. Yenduri, A, C. Gilbert, M. P. Flynn and S. Naraghi, "Rand PPM : A low power compressive sampling analog to digital converter," IEEE International
Conference on Acoustics, Speech, and Signal Processing, May , 2011.

  27. B. Rhew, J. Jeong, J. Fredenburg, and M. P. Flynn, "Ultra Low Power Microsystems Using RF Energy Scavenging," (IEDM) IEEE International Electron Devices Meeting, Washington, DC, December (Invited), 2011.

  28. C. Lee and M. P. Flynn, "A 12b 50MS/s 3.5mW SAR Assisted 2-Stage Pipeline ADC," IEEE Symposium on VLSI Circuits, June , 2010.

  29. Lin, D.T. ; Li Li ; Farahani, S. ; Flynn, M.P., "A flexible 500MHz to 3.6GHz wireless receiver with configurable DT FIR and IIR filter embedded in a 7b 21MS/s SAR ADC," Custom Integrated Circuits Conference (CICC), September, 2010.

  30. M. Kurata, J. Lynch, T.,Galchev, M. P. Flynn, et al, "A two-tiered self-powered wireless monitoring system architecture for bridge health management," Proceedings of SPIE , Vol. 7649, 76490K (Invited), 2010.

  31. A. Tamez, J. A. Fredenburg, and Michael P. Flynn, "An Integrated 120 VAC Line Voltage Interface in Standard 0.13μm CMOS," IEEE European Solid-State Circuits Conference, September, 2010.

  32. D. T. Lin, L. Li, S. Farahani and M. P. Flynn, "Flexible Wireless Receiver with Software-Configurable DT FIR and IIR Filtering Embedded in a 7b 21MS/s SAR ADC," IEEE Custom Integrated Circuits Conference, September, 2010.

  33. J. Kang, and M. P. Flynn, "A 12b 11MS/s Successive Approximation ADC with two comparators in 0.13µm CMOS," IEEE Symposium on VLSI Circuits, June , 2009.

  34. S. Naraghi, M. Courcy, and M. P. Flynn, "A 9bit 14µW 0.06mm2 Pulse Position Modulation ADC in 90nm Digital CMOS," IEEE International Solid State Circuits Conf. (ISSCC), February, 2009.

  35. M. Ferriss, D. Lin, and M. P. Flynn, "A Fractional-N PLL modulator with flexible direct digital phase modulation," IEEE Custom Integrated Circuits Conference (CICC), September, 2009.

  36. J. P. Lynch, K. Kamat, V. Li, M. P. Flynn, D. Sylvester, K. Najafi, T. Gordon, M. Lepech, A. Emami-Naeini, A. Krimotat, M. Ettouney, S.Alampalli, and T. Ozdemir, "Overview of a Cyber-enabled Wireless Monitoring System for the Protection and Management of Critical Infrastructure Systems," SPIE Smart Structures and Materials, San Diego, CA, (Invited Paper), 2009.

  37. C. C. Lee and M. P. Flynn, "A 14b 23MS/s 48mW Resetting SD ADC with 87dB SFDR 11.7b ENOB & 0.5mm2 area," IEEE Symposium on VLSI Circuits, June , 2008.

  38. D. Shi, N. Behdad, J. Chen, and M. P. Flynn, "A 5GHz Fully Integrated Super-regenerative Receiver with On-chip Slot Antenna in 0.13µm CMOS," IEEE Symposium on VLSI Circuits, June, 2008.

  39. J. Park, J. Kang, S. Park, and M. P. Flynn, "A 9Gbit/s Serial Transceiver for On-chip Global Signaling over Lossy Transmission Lines," IEEE Custom Integrated Circuits Conference (CICC), September, 2008.

  40. J. Kang, D. Lin, L. Li, and M. P. Flynn, "A Reconfigurable FIR Filter Embedded in a 9b Successive Approximation ADC," IEEE Custom Integrated Circuits Conference (CICC), September, 2008.

  41. N. Behdad, D. Shi, W. Hong, K. Sarabandi and M. P. Flynn, "A 0.3mm2 Miniaturized X-Band On-Chip Slot Antenna in 0.13m CMOS," IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June , 2007.

  42. M. Ferriss and M. P. Flynn, "A 14mW Fractional-N PLL modulator with a novel digital phase detector and frequency switching scheme," IEEE International Solid State Circuits Conference (ISSCC), February , 2007.

  43. J. Lee, S. Park, J. Kang, J. Seo, J. Anders and M. P. Flynn , "A 2.5mW 80dB DR 36dB SNDR 22MS/s Logarithmic Pipeline ADC," J. Lee, S. Park, J. Kang, J. Seo, J. Anders and M. P. Flynn , June , 2007.

  44. J. Lee, S. Park, J. Kang, J. Seo, J. Anders and M. P. Flynn , "A 2.5mW 80dB DR 36dB SNDR 22MS/s Logarithmic Pipeline ADC," IEEE Symposium on VLSI Circuits, June , 2007.

  45. I. Bogue and M. P. Flynn, "A 57dB SFDR Digitally Calibrated 500MS/s Folding ADC in 0.18µm," IEEE Custom Integrated Circuits Conference (CICC), September, 2007.

  46. D. Shi, and M. P. Flynn , "A Compact 5GHz Q-enhanced Standing-Wave Resonator-based Filter in 0.13μm CMOS," IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June, 2007.

  47. D. Shi, J East and M. P. Flynn, "A Compact 5GHz Standing-Wave Resonator-based VCO in 0.13µm CMOS," IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June, 2007.

  48. S. Park, Palaskas, A. Ravi, R. Bishop and M. Flynn, "A 3.5 GS/s 5-b Flash ADC in 90 nm CMOS," Custom Integrated Circuits Conference (CICC), September , 2006.

  49. S. Park, Y. Palaskas and M. P. Flynn, "A 4GS/s 4bit Flash ADC in 0.18m CMOS," IEEE International Solid State Circuits Conference (ISSCC), February , 2006.

  50. J. Chen, M. P. Flynn, and J. Hayes, "A Fully Integrated Auto-Calibrated Super-Regenerative Receiver," IEEE International Solid State Circuits Conference (ISSCC), February, 2006.

  51. J.Y. Park and M. P. Flynn, "A Low Jitter Multi-Phase PLL with Capacitive Coupling," Custom Integrated Circuits Conference (CICC), September, 2006.

  52. J. Chen, M. P. Flynn and J. Hayes, "A 3.6mW 2.4-GHz Multi-Channel Super-Regenerative Receiver in 130nm CMOS," Custom Integrated Circuits Conference (CICC), September, 2005.

  53. J. Chen, M. P. Flynn and J. Hayes, "A 3.6mW 2.4-GHz Multi-Channel Super-Regenerative Receiver in 130nm CMOS," Custom Integrated Circuits Conference (CICC), September, 2005.

  54. Kocer, F.; Flynn, M.P., "A long-range RFID IC with on-chip ADC in 0.25 μm CMOS," Radio Frequency integrated Circuits (RFIC) Symposium , Digest of Papers, IEEE, 2005.

  55. F. Kocer and M. P. Flynn, "A New Transponder Architecture for Long-Range Telemetry Applications," European Conference on Circuit Theory and Design, August , 2005.

  56. J. Park and M. P. Flynn, "Capacitively Averaged Multi-Phase LC Oscillators," International Conference on Circuits and Systems (ISCAS), , 2005.

  57. J. Kang, J. Park and M. P. Flynn, "Global High-Speed Signaling in Nanometer CMOS," Asia Solid State Circuits Conference (ASSCC), November, 2005.

  58. M. P. Flynn and J. Kang, "Global Signaling over Lossy Transmission Lines," International Conference on Computer Aided Design (ICCAD), November(Invited), 2005.

  59. F. Kocer and M. P. Flynn, "An Injection Locked, RF Powered, Telemetry IC in 0.25µm CMOS," IEEE Symposium on VLSI Circuits, June, 2004.

  60. F. Kocer and M. P. Flynn, "An RF powered, wireless temperature sensor in 0.25µm CMOS," International Symposium on Circuits and Systems, May, 2004.

  61. R. B. Brown, D. Sylvester, D. Blaauw, M. P. Flynn, and G. Carichner, "VLSI Design Curriculum," 2004 ASEE Annual Conference & Exposition, June, 2004.

  62. F. Kocer and M. P. Flynn, "Wireless, remotely powered telemetry in 0.25µm CMOS," IEEE Radio Frequency Integrated Circuits Conference (RFIC 2004), pp. 339-342, 2004.

  63. M. P. Flynn and I. Bogue, "Using redundancy to break the link between accuracy and speed in an ADC," Instrumentation and Measurement Technology Conference (IMTC '03), Proceedings of the 20th IEEE, Vol: 1, 2003.

  64. E. T. Zellers, K. D. Wise, K. Najafi, D. Aslam, R. B. Brown, Q. Y. Cai, J. Driscoll, M. P. Flynn, J. Giachino, et al., "Determinations of Complex Vapor Mixtures in Ambient Air with a Wireless Microanalytical System: Vision, Progress, and Homeland Security Applications," Technical Digest of the IEEE Conference on Technologies for Homeland Security, Waltham, MA, IEEE, Boston, pp. 92-95, November 13-14, 2002.

  65. C. Donovan and M. P. Flynn, "A ‘Digital’ 6-bit ADC in 0.25m CMOS," Custom Integrated Circuits Conference, pp. 145-148, May , 2001.

  66. D.J. Foley and M. P. Flynn, "A Low-power 8-PAM Serial Transceiver in 0.5m digital CMOS," Custom Integrated Circuits Conference, San Diego, pp. 123-126, 2001.

  67. D. Foley and M. P. Flynn, "A 3.3V 1.6GHz Low Jitter Self Correcting DLL Based Clock Synthesizer in 0.5m CMOS," International Symposium on Circuits and Systems, Vol. 2, pp. 249-252, May, 2000.

  68. D. Foley and M. P. Flynn, "A 3.3V 1.6GHz Low Jitter Self Correcting DLL Based Clock Synthesizer in 0.5m CMOS," International Symposium on Circuits and Systems, Vol. 2, pp. 249-252, May , 2000.

  69. D. Foley and M. P. Flynn, "CMOS DLL Based 2V, 3.2ps Jitter, 1-GHz Clock Synthesizer and Temperature Compensated Tunable Oscillator," Custom Integrated Circuits Conference, pp. 371-374, May , 2000.

  70. M. P. Flynn and B. Sheahan, "A 400MSample/s 6b CMOS Folding and interpolating ADC," International Solid-State Circuits Conference, February 1998, .

  71. M. P. Flynn, M. Twohig, R. Byrne, H. Reyhani and J. Ryan, "A BiCMOS Preamplifier IC for Tape Drive," Custom Integrated Circuits Conference, pp. 329-332, May 1999, .

  72. M. P. Flynn and S. Lidholm, "A High-Performance 1m CMOS Current Controlled Oscillator," European Solid-State Circuits Conference, September 1991, .

  73. J. G. Ryan, J. Doyle, M. Buckley and M. Flynn, "A Magnetic Field Sensitive Amplifier with Temperature Compensation," International Solid-State Circuits Conference, February 1992, .

  74. M. Buckley, J Doyle, M. Flynn and J. Ryan, "An investigation of split-drain MAGFET and signal conditioning circuitry," Proceedings of Sensors and Their Applications V, 1991, .

  75. M. P. Flynn and D. J. Allstot, "CMOS folding ADCs with Current-mode Interpolation," International Solid-State Circuits Conference, February 1995, .

  76. P.C. Maulik, M. P. Flynn, D.J. Allstot and L.R. Carley, "Rapid Redesign of Analog Cells using Constrained Optimization Techniques," Custom Integrated Circuits Conference, May 1992, .

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