Introduction

Lecture - 1 & 2
• Handout for Course Organization and Evaluation Criteria
• Handout for Custom vs. Semicustom Layout Techniques
• Sait and Youssef, Physical Design Automation - Theory and Practice, IEEE Press, 1995 (Chapter 1).
• K. Shahookar and P. Mazumder, "VLSI Cell Placement Techniques," ACM Computing Surveys, vol. 23, no. 2, pp. 143-220, June 1991 (Introduction section only).

Lecture - 3 & 4
• B. W. Kernighan and S. Lin, "An Efficient Heuristic Procedure for Partitioning Graphs," The Bell System Technical Journal, pp. 291-307, February 1970. K-L Paper
  Lecture - 5 & 6
• C. M. Fiduccia and R. M. Mattheyses, "A Linear-Time Heuristic for Improving Network Partitions," in Proc. 19th Design Automation Conference, pp. 175-181, 1982. F-M Paper
• B. Krishnamurthy, "An Improved Min-Cut Algorithm for Partitioning VLSI Networks," IEEE Transactions on Computers, vol. C-33, no. 5, pp. 438-446, May 1984.
• S. Dutt and W. Deng, "A Probability-Based Approach to VLSI Circuit Partitioning," in Proc 33rd Design Automation Conference, pp. 100-105, 1996.
  Self-Study
• W.-K. Mak and D. F. Wong, "Minimum Replication Min-Cut Partitioning," in Proc. of the International Conference on Computer-Aided Design, pp. 205-210, 1996.
• S. Dutt and W. Deng, "VLSI Circuit Partitioning by Cluster-Removal Using Iterative Improvement Techniques," in Proc. International Conference on Computer-Aided Design, pp. 194-200, 1996.
• C.-K. Cheng and Y.-C. A. Wei, "An Improved Two-Way Partitioning Algorithm with Stable Performance," IEEE Transactions on Computer-Aided Design, vol. 10, no. 12, pp. 1502-1511, December 1991.
• J. Yih and P. Mazumder, "A Neural Network Design for Circuit Partitioning," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 9, no. 12, pp. 1265-1271, December 1990.
• K. Shahookar and P. Mazumder, "Genetic Min-cut Partitioning," in Proc. Eight International VLSI Design Conference, 1995.
• C. J. Alpert and S.-Z. Yao, "Spectral Partitioning: The More Eigenvectors, The Better," in Proc. 32nd Design Automation Conference, pp. 195-200, 1995.
• C. J. Alpert and A. B. Kahng, "Multiway Partitioning Via Geometric Embeddings, Orderings, and Dynamic Programming," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no. 11, November 1995.
• M. Shih, E. S. Kuh, and R.-S. Tsay, "Performance-Driven System Partitioning on Multi-Chip Modules," in Proc. 29th ACM/IEEE Design Automation Conference, pp. 53-56, 1992.

• K. Shahookar and P. Mazumder, "VLSI Cell Placement Techniques," ACM Computing Surveys, vol. 23, no. 2, pp. 143-220, June 1991.
• M. Breuer, "Min-cut Placement," Journal of Design Automation and Fault Tolerant Computing, vol. 1, no. 4, pp. 343-382, October 1977.
• H. M. Chan, P. Mazumder, and K. Shahookar, "Macro-cell and Module Placement by Genetic Optimization with Bit-map Represented Crossover Operators," Integration: An International VLSI Journal, pp. 49-77, December 1991.
• C. Cheng and E. Kuh, "Module Placement based on Resistive Network Optimization," IEEE transactions on Computer-Aided Design, vol. 3, no. 7, pp. 218-225, July 1984.
• K. Hall, "An r-dimensional Quadratic Placement Algorithm," Management Science, vol. 17, no. 3, pp. 219-229, November 1970.
• M. Huang, F. Romeo, and A. Sangiovanni-Vincentelli, "An Efficient General Cooling Schedule for Simulated Annealing," in Proc. IEEE International Conference on Computer-Aided Design, pp. 381-384, 1986.
• C. Sechen and K. Lee, "An Improved Simlated Annealing Algorithm for Row-based Placement," in Proc. IEEE International Conference on Computer-Aided Design, pp. 478-481, 1987.
• C. Sechen, "Chip Planning, Placement, and Global Routing of Macro/custom Cell Integrated Circuits using Simulated Annealing," in Proc. Design Automation Conference, pp. 73-80, 1988.
• K. Shahoookar and P. Mazumder, "A Genetic Approach to Standard Cell Placement using Meta-genetic Parameter Optimization," IEEE Transactions on Computer-Aided Design, vol. 9, no. 5, pp. 500-511, May 1990.
• R. Tsay, E. Kuh, and T. Sudo, "Layout Strategy, Standardization, and CAD Tools," in Layout Design and Automation, T. Ohtsuki, Ed., Elsevier Science Pub. Co., New York, Chapter 1, 1986.

• K. Shahookar and P. Mazumder, "VLSI Cell Placement Techniques," ACM Computing Surveys, vol. 23, no. 2, pp. 143-220, June 1991.
• M. Breuer, "Min-cut Placement," Journal of Design Automation and Fault Tolerant Computing, vol. 1, no. 4, pp. 343-382, October 1977.
• H. M. Chan, P. Mazumder, and K. Shahookar, "Macro-cell and Module Placement by Genetic Optimization with Bit-map Represented Crossover Operators," Integration: An International VLSI Journal, pp. 49-77, December 1991.
• C. Cheng and E. Kuh, "Module Placement based on Resistive Network Optimization," IEEE transactions on Computer-Aided Design, vol. 3, no. 7, pp. 218-225, July 1984.
• K. Hall, "An r-dimensional Quadratic Placement Algorithm," Management Science, vol. 17, no. 3, pp. 219-229, November 1970.
• M. Huang, F. Romeo, and A. Sangiovanni-Vincentelli, "An Efficient General Cooling Schedule for Simulated Annealing," in Proc. IEEE International Conference on Computer-Aided Design, pp. 381-384, 1986.
• C. Sechen and K. Lee, "An Improved Simlated Annealing Algorithm for Row-based Placement," in Proc. IEEE International Conference on Computer-Aided Design, pp. 478-481, 1987.
• C. Sechen, "Chip Planning, Placement, and Global Routing of Macro/custom Cell Integrated Circuits using Simulated Annealing," in Proc. Design Automation Conference, pp. 73-80, 1988.
• K. Shahoookar and P. Mazumder, "A Genetic Approach to Standard Cell Placement using Meta-genetic Parameter Optimization," IEEE Transactions on Computer-Aided Design, vol. 9, no. 5, pp. 500-511, May 1990.
• R. Tsay, E. Kuh, and T. Sudo, "Layout Strategy, Standardization, and CAD Tools," in Layout Design and Automation, T. Ohtsuki, Ed., Elsevier Science Pub. Co., New York, Chapter 1, 1986.