EECS 579: Digital System Testing

Fall 2002

Instructor: Prof. Pinaki Mazumder

General Information

 
Lectures T & Th 9:00-10:30 p.m., 153 EWRE/th>
Office hours T & Th 10:45-12:15 p.m.
Office 2215 EECS
Office phone 763-2107
Email address mazum@eecs.umich.edu
Prerequisite: EECS 478 or Instructor's consent.
Text Book: M. Bushnell, and V. D. Agarwal, Essential of Electronic Testing for Digital, Memory and Mixed Signal VLSI Circuits ,
Kluwer Aacdemic Press,, Boston , 2000, 690 pages
Supplementary Text Book: 1. P. Mazumder and K.Chakraborty, Testing and Testable Design of Random-Access Memories,
Kluwer Academic Publishers, New York, 1996, 430 pages.
: 2. M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital System Testing and Testable Design,
IEEE Press, New York, 1990, 652 pages
(an early version of the same book was published by Computer Science Press).
Evaluation: 1. Homework Assignments(6): 30%
2. Project: 30%
3. Midterm(2): 20%
4. Final Exam: 20%.
Class Handouts

Course Announcement
Detailed Course Outline
List of Projects
Schedule
Lecture Materials

Lectures #1&2: Preliminary issues of VLSI chip testing


Lectures #2&3:Test economics, test quality and yield analysis


Lectures #4&5:Fault models, fault collapsing and logic simulation


Lectures #6:Testing of basic gates and parity tree based gated networks


Lectures #7 & 8:Combinational circuit testing

Lectures #9 & 10:Algorithms for combinational circuit testing


Lectures #11 & 12:PODEM and FAN


Lectures #13 & 14:Testability and SCOAP


Lectures #15 & 16:Fault Simulation


Lectures #17 & 18:Memory testing


Lectures #19 & 20:Built-in Self-Testing and LFSR Theory
Homework Assignments

Homework assignment #1: Chapters 1, 2 and 3. (Textbook)
Goal: To evaluate your knowledge in Test Economics and Test Quality
Distribution date: Sept 17, 2002
Due date: Sept 24, 2002
Homework assignment #2: Chapter 4: Fault Modeling
Goal: To evaluate your knowledge in Fault Modeling
Distribution date: Sept 24, 2002
Due date: October 3, 2002
Other Links and Resources

EECS 427: VLSI Design I
: Mask level integrated circuit design. Mentor Graphics IC Station, Design Archtect, Quicksim, Accusim, etc.
EECS 470: Computer Architecture
: Concepts of computer architecture and organization. Verilog Hardware Description Language.
EECS 627: VLSI Design II
: Advanced VLSI circuit design.
The University of California, Berkeley, SPICE3
Electrical engineering Virtual Library.
UNIX Reference Desk.