Marios C. Papaefthymiou - Select Publications

• Energy-efficient design
• Power macromodeling
• Timing analysis and optimization
• Clock tree synthesis
• Embedded systems
• Parallel and distributed computing
• Pot pourri

Energy-efficient design

• J. Kao, W. H. Ma, V. S. Sathe, and M. C. Papaefthymiou. Energy-efficient low-latency 600MHz FIR with high-overdrive charge-recovery logic. IEEE Transactions on VLSI Systems , to appear.

• J. Kao, W.-H. Ma, S. Kim, and M. C. Papaefthymiou. 2.07GHz floating-point unit with resonant-clock precharge logic. In IEEE Asian Solid-State Circuits Conference, November 2010.

• W. H. Ma, J. Kao, V. S. Sathe, and M. C. Papaefthymiou. A 187MHz subthreshold supply charge-recovery FIR. IEEE Journal of Solid State Circuits , Vol. 45, No. 4, April 2010.

• J. Kao, W.-H. Ma, V. Sathe, and M. C. Papaefthymiou. A charge-recovery 600MHz FIR filter with 1.5-cycle latency overhead. In European Solid-State Circuits Conference , September 2009.

• A. Ishii, J. Kao, V. Sathe, and M. C. Papaefthymiou. A resonant-clock 200MHz ARM926EJ-S^{TM} microcontroller. In European Solid-State Circuits Conference, September 2009.

• W. H. Ma, J. Kao, V. Sathe, and M. C. Papaefthymiou. A 187MHz subthreshold-supply robust FIR filter with charge-recovery logic. In IEEE Symposium on VLSI Circuits, June 2009.

• V. S. Sathe, J. Kao, and M. C. Papaefthymiou. Resonant-clock latch-based design. IEEE Journal of Solid State Circuits, Vol. 43, No. 4, April 2008.

• V. Sathe, J. Kao, and M. C. Papaefthymiou. A 0.8-1.2GHz frequency tunable single-phase resonant-clocked FIR filter. In IEEE 2007 Custom Integrated Circuits Conference, September 2007.

• S. Kim, S. V. Kosonocky, D. R. Knebel, K. Stawiasz, and M. C. Papaefthymiou. A multi-mode power gating structure for low-voltage deep-submicron CMOS ICs. IEEE Transactions on Circuits and Systems II, Vol. 54, No. 7, July 2007.

• V. Sathe, J. Kao, and M. C. Papaefthymiou. RF2: A 1GHz filter with distributed resonant clock generator. In IEEE Symposium on VLSI Circuits, June 2007.

• V. S. Sathe, J.-Y. Chueh, and M. C. Papaefthymiou. Energy-efficient GHz-class charge-recovery logic. IEEE Journal of Solid State Circuits, Vol. 42, No. 1, January 2007.

• J.-Y. Chueh, V. Sathe, and M. C. Papaefthymiou. 900MHz to 1.2GHz two-phase resonant clock network with programmable driver and loading. In IEEE 2006 Custom Integrated Circuits Conference, September 2006.

• X. Liu, Y. Peng, and M. C. Papaefthymiou. Practical repeater insertion for low power: What repeater library do we need? IEEE Transactions on Computer-Aided Design of Integrated Circuits, Vol. 25, No. 5, pp. 917-924, May 2006.

• V. Sathe, J.-Y. Chueh, and M. C. Papaefthymiou. A 1.1GHz charge recovery logic. In International Solid-State Circuits Conference, February 2006.

• V. Sathe, C. Ziesler, and M. C. Papaefthymiou. GHz-class charge recovery logic. In International Symposium on Low-Power Electronics and Design, August 2005.

• S. Kim, C. Ziesler, and M. C. Papaefthymiou. Charge-recovery computing on silicon. IEEE Transactions on Computers, Vol. 54, No. 6, June 2005.

• V. Sathe, J.-Y. Chueh, J. Kim, C. Ziesler, S. Kim, and M. C. Papaefthymiou. Fast, efficient, recovering, and irreversible. In 1st Workshop on Reversible Computing of the 2005 ACM Computing Frontiers Conference , May 2005.

• J.-Y. Chueh, V. Sathe, and M. C. Papaefthymiou. Two-phase resonant clock distribution. In Proceedings of the 2005 IEEE International Symposium on VLSI, May 2005.

• V. Sathe, M. C. Papaefthymiou, and C. Ziesler. Boost Logic: A high-speed energy recovery circuit family. In Proceedings of the 2005 IEEE International Symposium on VLSI, May 2005.

• X. Liu, Y. Peng, and M. C. Papaefthymiou. RIP: An efficient hybrid repater insertion scheme for low power. In Proceedings of the 2005 Conference on Design, Automation, and Test in Europe, March 2005.

• J. Kim and M. C. Papaefthymiou. Constant-load energy recovery memory for efficient high-speed operation. In International Symposium on Low-Power Electronics and Design, August 2004.

• X. Liu, Y. Peng, and M. C. Papaefthymiou. Practical repeater insertion for low power: What repeater library do we need? In Proceedings of the 41st ACM/IEEE Design Automation Conference , June 2004.

• J.-Y. Chueh, C. Ziesler, and M. C. Papaefthymiou. Empirical evaluation of timing and power in resonant clock distribution. In 2004 IEEE International Symposium on Circuits and Systems, May 2004.

• J.-Y. Chueh, C. Ziesler, and M. C. Papaefthymiou. Experimental evaluation of resonant clock distribution. In Proceedings of the 2004 IEEE International Symposium on VLSI, February 2004.

• J. Kim and M. C. Papaefthymiou. Block-based multi-period refresh for energy efficient dynamic memory. IEEE Transactions on VLSI Systems, Vol. 11, No. 6, pp. 1006--1018, December 2003.

• X. Liu and M. C. Papaefthymiou. Design of a 20 Mb/s 256-state Viterbi decoder. IEEE Transactions on VLSI Systems, Vol. 11, No. 6, pp. 965--975, December 2003.

• S. Kim, C. Ziesler, and M. C. Papaefthymiou. Fine-grain real-time reconfigurable pipelining. IBM Journal of Research and Development, Vol. 47, No. 5/6, pp. 599--609, September/November 2003.

• C. Ziesler, J. Kim, V. Sathe, and M. C. Papaefthymiou. A 225MHz resonant clocked ASIC chip. In International Symposium on Low Power Electronics and Design, August 2003.

• S. Kim, C. Ziesler, and M. C. Papaefthymiou. A true single-phase energy-recovery multiplier. IEEE Transactions on VLSI Systems, Vol. 11, No. 2, pp. 194--207, April 2003.

• C. Ziesler, J. Kim, and M. C. Papaefthymiou. Energy recovering ASIC design. In Proceedings of the 2003 IEEE International Symposium on VLSI, February 2003.

• J. Kim, C. Ziesler, and M. C. Papaefthymiou. Energy recovering static memory. In International Symposium on Low Power Electronics and Design, August 2002.

• X. Liu and M. C. Papaefthymiou. Design of a high-throughput low-power IS95 Viterbi decoder. In Proceedings of the 39th ACM/IEEE Design Automation Conference, June 2002.

• J. Kim and M. C. Papaefthymiou. Block-based multi-period refresh for energy efficient dynamic memory. In 14th IEEE International ASIC/SOC Conference, September 2001.

• C. Ziesler, S. Kim, and M. C. Papaefthymiou. A resonant clock generator for single-phase adiabatic systems. In International Symposium on Low Power Electronics and Design, August 2001.

• S. Kim, C. Ziesler, and M. C. Papaefthymiou. A true single-phase 8-bit adiabatic multiplier. In Proceedings of the 38th ACM/IEEE Design Automation Conference, June 2001. Received first prize in VLSI Design Contest (Operational Category).

• S. Kim, C. Ziesler, and M. C. Papaefthymiou. Design, verification, and test of a true single-phase 8-bit adiabatic multiplier. In Advanced Research in VLSI: Proceedings of the 2001 Conference, March 2001.

• S. Kim and M. C. Papaefthymiou. True single-phase adiabatic circuitry. IEEE Transactions on VLSI Systems, Vol. 9, No. 1, pp. 52--63, February 2001.

• J. Kim and M. C. Papaefthymiou. Dynamic memory design for low data-retention power. In 10th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS '00), September 2000.

• S. Kim, C. Ziesler, and M. C. Papaefthymiou. A reconfigurable pipelined IDCT for low-energy video processing. In 13th IEEE International ASIC/SOC Conference, September 2000.

• S. Kim and M. C. Papaefthymiou. Reconfigurable low energy multiplier for multimedia system design . In IEEE Annual Workshop on VLSI , April 2000.

• S. Kim and M. C. Papaefthymiou. Low-energy adder design with a single-phase source-coupled adiabatic logic . In PATMOS '99, 9th International Workshop on Power and Timing Modeling, Optimization and Simulation, October 1999.

• S. Hong, S. Kim, M. C. Papaefthymiou, and W.E. Stark. Low power parallel multiplier design for DSP applications through coefficient optimization . In 12th IEEE International ASIC/SOC Conference, September 1999.

• S. Kim and M. C. Papaefthymiou. Single-phase source-coupled adiabatic logic . In International Symposium on Low-Power Electronics and Design, August 1999.

• S. Hong, S. Kim, M. C. Papaefthymiou, and W.E. Stark. Power-complexity analysis of pipelined VLSI FFT architectures for low energy wireless communication applications . In 42nd Midwest Symposium on Circuits and Systems, August 1999.

• S. Kim and M. C. Papaefthymiou. Pipelined DSP design with a true single-phase energy-recovering logic style . In VOLTA'99 IEEE Alessandro Volta Memorial International Workshop on Low Power Design, March 1999.

• S. Kim and M. C. Papaefthymiou. True single-phase energy-recovering logic for low-power, high-speed VLSI. In 1998 International Symposium on Low-Power Electronics and Design, August 1998.

• K.N. Lalgudi and M. C. Papaefthymiou. Fixed-phase retiming for low power design . In 1996 International Symposium on Low Power Electronics and Design, August 1996.

• M. C. Knapp, P. J. Kindlmann, and M. C. Papaefthymiou. Design and evaluation of adiabatic arithmetic units. Analog Integrated Circuits and Signal Processing, Special Issue on Analog Design Issues in Digital VLSI Circuits and Systems, Vol. 14, pp. 71--79, 1997.

• M. C. Knapp, P. J. Kindlmann, and M. C. Papaefthymiou. Implementing and evaluating adiabatic arithmetic units . In Proceedings of the IEEE 1996 Custom Integrated Circuits Conference, May 1996.

• M. Alidina, J. Monteiro, S. Devadas, A. Ghosh, and M. C. Papaefthymiou. Precomputation-based sequential logic optimization for low power. IEEE Transactions on VLSI Systems, Special Issue on Low Power Design, December 1994. Earlier versions of this paper appeared in Technical Digest of Papers of the 1994 IEEE/ACM International Conference on Computer-Aided Design, November 1994, and in 1994 International Symposium on Low Power Design, April 1994.

Power macromodeling

• X. Liu and M. C. Papaefthymiou. HyPE: Hybrid power estimation for IP-based systems-on-chip. IEEE Transactions on Computer-Aided Design of Integrated Circuits, Vol. 24, No. 7, pp. 1089--1103, July 2005.

• X. Liu and M. C. Papaefthymiou. A Markov chain sequence generator for power macromodeling. IEEE Transactions on Computer-Aided Design of Integrated Circuits, Vol. 23, No. 7, pp. 1048--1062, July 2004.

• X. Liu and M. C. Papaefthymiou. HyPE: Hybrid Power Estimation for IP-Based Programmable Systems. In Proceedings of the 2003 IEEE/ACM Asia and South Pacific Design Automation Conference, January 2003.

• X. Liu and M. C. Papaefthymiou. A Markov chain sequence generator for power macromodeling. In Technical Digest of the 2002 IEEE/ACM International Conference on Computer-Aided Design, November 2002.

• X. Liu and M. C. Papaefthymiou. A statistical model of input glitch propagation and its application to power macromodeling. In 45th IEEE International Midwest Symposium on Circuits and Systems, August 2002.

• X. Liu and M. C. Papaefthymiou. Incorporation of input glitches into power macromodeling. In Proceedings of the 2002 International Symposium on Circuits and Systems, May 2002.

• X. Liu and M. C. Papaefthymiou. A static power estimation methodology for IP-based design. In Proceedings of the 2001 Conference on Design, Automation, and Test in Europe, March 2001.

• G. Bernacchia and M. C. Papaefthymiou. Analytical macromodeling for high-level power estimation . In Technical Digest of the 1999 IEEE/ACM International Conference on Computer-Aided Design, November 1999.

Timing analysis and optimization

• X. Liu, M. C. Papaefthymiou, and E. G. Friedman. Retiming and clock scheduling for digital circuit optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits, Vol. 21, No. 2, pp. 184--203, February 2002.

• X. Liu, M. C. Papaefthymiou, and E.G. Friedman. Maximizing performance by retiming and clock skew scheduling . In Proceedings of the 36th ACM/IEEE Design Automation Conference, June 1999.

• X. Liu, M. C. Papaefthymiou, and E.G. Friedman. Minimizing sensitivity to delay variations in high-performance synchronous circuits . In Proceedings of the 1999 IEEE Conference on Design, Automation, and Test in Europe , March 1999.

• M. C. Papaefthymiou. Asymptotically efficient retiming under setup and hold constraints . In Technical Digest of Papers of the 1998 IEEE/ACM International Conference on Computer-Aided Design, November 1998.

• M. C. Papaefthymiou, E. G. Friedman, and X. Liu. Retiming and clock scheduling for high-performance synchronous circuits. In PATMOS '98, Eighth International Workshop on Power and Timing Modeling, Optimization and Simulation, October 1998.

• K. N. Lalgudi and M. C. Papaefthymiou. Retiming edge-triggered circuits under general delay models. IEEE Transactions on Computer-Aided Design of Integrated Circuits, Vol. 16, No. 12, pp. 1393--1408, December 1997.

• A. T. Ishii and M. C. Papaefthymiou. Efficient pipelining of level-clocked circuits with min-max propagation delays. In TAU'95 ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, November 1995.

• K. N. Lalgudi and M. C. Papaefthymiou. Delay: An efficient tool for retiming with realistic delay modeling. In Proceedings of the 32nd ACM/IEEE Design Automation Conference, June 1995. Received Best Paper Award.

• K. N. Lalgudi and M. C. Papaefthymiou. Efficient retiming under a general delay model. In Advanced Research in VLSI: Proceedings of the 1995 Chapel Hill Conference, March 1995.

• M. C. Papaefthymiou and K.H. Randall. TIM: A Timing package for two-phase, level-clocked circuitry. In Proceedings of the 30th ACM/IEEE Design Automation Conference, June 1993.

• M. C. Papaefthymiou and K. H. Randall. Edge-triggering vs. two-phase level-clocking. In Research on Integrated Systems: Proceedings of the 1993 Symposium, March 1993.

• A. T. Ishii, C. E. Leiserson, and M. C. Papaefthymiou. Optimizing two-phase, level-clocked circuitry. Journal of the ACM, Vol. 44, No. 1, pp. 148--199, January 1997. An extended abstract appeared in Advanced Research in VLSI and Parallel Systems: Proceedings of the 1992 Brown/MIT Conference, March 1992.

• M. Alidina, J. Monteiro, S. Devadas, A. Ghosh, and M. C. Papaefthymiou. Precomputation-based sequential logic optimization for low power. IEEE Transactions on VLSI Systems, Special Issue on Low Power Design, Vol. 2, No. 4, pp. 426--436, December 1994.

• M. C. Papaefthymiou. Understanding retiming through maximum average-delay cycles. Mathematical Systems Theory, No. 27, pp. 65--84, 1994. An early version of this paper appeared in Proceedings of the 3rd ACM Symposium on Parallel Algorithms and Architectures, July 1991.

Clock tree synthesis

• D. Velenis, E. G. Friedman, and M. C. Papaefthymiou. Clock tree layout design for reduced delay uncertainty. In 17th IEEE International SOC Conference, September 2004.

• D. Velenis, E. G. Friedman, and M. C. Papaefthymiou. Reduced delay uncertainty in high performance clock distribution networks. In Proceedings of the 2003 Conference on Design, Automation, and Test in Europe, March 2003.

• D. Velenis, E. G. Friedman, and M. C. Papaefthymiou. Clock tree topology extraction algorithm to improve the tolerance of data paths to process and environmental variations. In Proceedings of the 2001 International Symposium on Circuits and Systems, May 2001.

Embedded systems

• F. Koushanfar, D. Kirovski, I. Hong, M. Potkonjak, and M. C. Papaefthymiou. Symbolic debugging of embedded hardware and software. IEEE Transactions on Computer-Aided Design of Integrated Circuits, Vol. 20, No. 3, pp. 392--401, March 2001.

• K. N. Lalgudi, M. C. Papaefthymiou, and M. Potkonjak. Optimizing computations for effective block-processing. ACM Transactions on Design Automation of Electronic Systems, Vol. 5, No. 3, pp. 604--630, July 2000.

• D. Kirovski, I. Hong, M. Potkonjak, and M. C. Papaefthymiou. Symbolic debugging of globally optimized behavioral specifications. In Asia South-Pacific Design Automation Conference, January 2000.

• I. Hong, M. Potkonjak, and M. C. Papaefthymiou. Efficient block scheduling to minimize context switching time for programmable embedded processors. Design Automation for Embedded Systems, Vol. 4, No. 4, pp. 311--327, October 1999.

• K. N. Lalgudi, M. C. Papaefthymiou, and M. Potkonjak. Optimizing computations for effective block-processing. In Proceedings of the 33rd ACM/IEEE Design Automation Conference, June 1996. An extended version of this paper appeared as Technical Report YALEU/DCS/RR-1102, April 1996.

Parallel and distributed computing

• J. Kim, M. C. Papaefthymiou, and J. L. Neves. Parallelizing post-placement timing optimization. In Proceedings of the 18th International Parallel and Distributed Processing Symposium, April 2006.

• J. Kim, M. C. Papaefthymiou, and A. Tayyab. An algorithm for geometric load balancing with two constraints. In Proceedings of the 18th International Parallel and Distributed Processing Symposium, April 2004.

• F. Wang, M. C. Papaefthymiou, and M. S. Squillante. Performance evaluation of gang scheduling for parallel and distributed multiprogramming. In Workshop on Job Scheduling Strategies for Parallel Processing of the 1997 International Parallel Processing Symposium, April 1997.

• M. S. Squillante, F. Wang, and M. C. Papaefthymiou. Stochastic analysis of gang scheduling in parallel and distributed systems. Performance Evaluation, 27 & 28:273--296, 1996.

• M. S. Squillante, F. Wang, and M. C. Papaefthymiou. Stochastic analysis of gang scheduling in parallel and distributed systems. In Performance '96, October 1996.

• M. S. Squillante, F. Wang, and M. C. Papaefthymiou. An analysis of gang scheduling for multiprogrammed parallel computing environments. In Proceedings of the 8th ACM Symposium on Parallel Algorithms and Architectures, June 1996.

• F. Wang, H. Franke, M. C. Papaefthymiou, P. Pattnaik, L. Rudolph, and M. S. Squillante. A gang scheduling design for multiprogrammed parallel computing environments. In Workshop on Job Scheduling Strategies for Parallel Processing of the 1996 International Parallel Processing Symposium, April 1996.

• M. C. Papaefthymiou and J. Rodrigue. Implementing parallel shortest-paths algorithms. In The Third DIMACS International Algorithm Implementation Challenge on Parallel Algorithms , October 1994. Journal version appeared in Parallel Algorithms, S.N. Bhatt (ed.), DIMACS Series in Discrete Mathematics and Theoretical Computer Science, Vol. 30, 1997.

• A. Agarwal, J. Guttag, C. Hadjicostis, and M. C. Papaefthymiou. Memory assignment for multiprocessor caches through grey coloring. In Parallel Architectures and Languages Europe, July 1994.

Pot pourri

• V. S. Sathe, M. C. Papaefthymiou, S. V. Kosonocky, and S. Kim. On-chip synchronous communication between clock domains with quotient frequencies. Electronics Letters, Vol. 43, No. 9, April 2007.

• V. S. Sathe, C. H. Ziesler, M. C. Papaefthymiou, S. Kim, and S. Kosonocky. A synchronous interface for SoCs with multiple voltage and clock domains. In 17th IEEE International SOC Conference, September 2004.

• K. G. Oweiss, D. J. Anderson, and M. C. Papaefthymiou. Optimizing signal coding in neural interface System-on-a-Chip modules. In Proceedings of the 25th IEEE International Conference on Engineering in Medicine and Biology, September 2003

• K. N. Lalgudi and M. C. Papaefthymiou. Computing strictly-second shortest paths. Information Processing Letters, Vol. 63, pp. 177--181, 1997.

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