Prof. Papaefthymiou investigates design technologies for energy-efficient high-performance computer systems. Currently, the main thrust of his research group is on charge-recovery (a.k.a. energy-recovery or adiabatic) circuits and VLSI architectures for high-performance servers, mobile devices, and bio-embedded networks. Together with his students, Prof. Papaefthymiou has pioneered the exploration of practical charge-recovery technologies that can be used with mainstream design flows. Several advances have been demonstrated via working silicon prototypes, including the first-ever GHz-class charge-recovery ASICs and circuit families, a resonant clocking technology that is compatible with standard ASIC design flows, and the first charge-recovery circuit family that operates using a single-phase power-clock waveform.
Prof. Papaefthymiou is also interested in algorithms for the timing analysis and optimization of high-performance digital circuitry. His investigation of the retiming transformation has resulted in several asymptotically efficient retiming algorithms for edge-triggered and level-clocked circuits under general delay models that account for setup times, hold times, register delays, and clock skew. Other areas of active research are parallel and distributed computing, as well as design automation algorithms and tools for managing design complexity, with a focus on fast power estimators and geometric partitioners.
Support for Prof. Papaefthymiou's research group is provided by the National Science Foundation, ARO, DARPA, SRC, IBM Corporation, and equipment grants from Intel Corporation.