Marios C. Papaefthymiou - Research Summary


Papaefthymiou is interested in design technologies for energy-efficient high-performance computer systems. Over the past several years, his reesarch has focused on so-called charge-recovery (a.k.a. adiabatic or energy recycling) architectures. These architectures have the theoretical potential to decrease energy consumption by orders of magnitude. In practice, however, their potential has remained unrealized, due to the high overheads and relatively slow operation of early implementations. Together with his students, Papaefthymiou has pioneered the exploration of practical charge-recovery technologies, providing silicon demonstration of the first-ever charge-recovery circuits and architectures that operate at GHz clock speeds and are compatible with standard design flows. His work on charge-recovery clocking (a.k.a. resonant clocking) has been commercialized through Cyclos Semiconductor and represents the first-ever deployment of charge-recovery technologies in practice. Resonant clocking is now used in multi-GHz microprocessor chips from AMD and IBM.

Papaefthymiou is also interested in algorithms for the timing analysis and optimization of high-performance digital circuitry. His investigation of the retiming transformation has resulted in several asymptotically efficient retiming algorithms for edge-triggered and level-clocked circuits under general delay models that account for setup times, hold times, register delays, and clock skew. Other areas of active research are parallel and distributed computing, as well as design automation algorithms and tools for managing design complexity, with a focus on fast power estimators and geometric partitioners.

Over the years Prof. Papaefthymiou's research has been supported by NSF, ARO, DARPA, SRC, IBM Corporation, Broadcom Foundation, and equipment grants from Intel Corporation.