Hi, I'm Ziyun Li

I am a fourth year Ph.D. student and a member of the VLSI Digital Design Group co-advised by Prof. Hun-Seok Kim and Prof. Blaauw David at the Electrical Engineering & Computer Science (EECS) Department at the University of Michigan, Ann Arbor.
My research interest is the realization of modern computer vision, machine learning and deep learning based navigation systems on mobile platforms, specifically, Micro Aerial vechicles(MAVs), with a focus on joint optimizations of algorithm, architecture and circuit. My aspiration is to develop high-performance and energy-efficient SoCs and application-specific computing systems for next-generation energy efficient mobile intelligent machines.
I am interested in research opportunities (e.g., internships) related to acceleration and energy efficient design of 3D vision, Optical flow, SLAM and machine learning. My CV is available here

Education

Phd Candidate, Electrical and Computer Engineering, Sep 2014 - Now

Advisors: Prof. Hun-Seok Kim, Prof. David Blaauw
Univerisity of Michigan, Ann Arbor

B.S. Electrical Engineering, Sep 2012 - May 2014

Cumulative GPA: 3.85/4.00
University of Michigan, Ann Arbor

Undergraduate in EECS, Sep 2010 - July 2012

Cumulative GPA: 3.85/4.00
Honor class with major in EECS, Chien-Shiung We College, Southeast University, Nanjing

Research

High performance, Energy-efficient 6D vision processor

Designing a reconfigurable algorithm for unified real-time optical flow & stereo vision.
Co-optimizing hardware & algorithm to achieve 30 HD fps throughput with ~500mW.
Custom designing "coalescing-resolving" crossbar for high-bandwidth random memory access.
Taping out a reconfigurable 6D vision processer in July 2016 with TSMC 28nm HPC technology.
Integrating the processing into real-time demo platform.

Ultra-low power DNN for mobile intelligent system

Collabrating in designing an ultra-low power programmable DNN accelerator for intelligent sensor nodes.
Custom designing low-power memory & processing to achieve 288uW active power.
Exploiting multi-power domain, multi-clock with power gating and clock gating for power saving.
Integrating ARM M0 & MBus protocol on the SoC for sensor node integrating.
Taping out chip in 40nm LP and testing the system with MNIST and key word spotting dataset.

High performance, Energy-efficient stereo vision processor

Designing a low-power stereo vision processor based on SGM algorithm.
Co-optimizing hardware & algorithm to achieve 30 HD fps throughput with 811mW.
Custom designing ultra-wide memory buffer to achieve 1.6Tbs memory bandwidth.
Taping out chip in 40nm, developing software, and integrating system on a drone with USB3.0 interface.
Performing real-time demo in ISSCC and delivering ~20 systems to ARL, JPL for collaboration.

Experience

Nvidia Research, Oct 2016 - Dec 2016

Research Intern, Manager: Brucek Khailany

Publications

Z. Li, Q. Dong, M. Saligane, B. Kempke, S. Yang, Z. Zhang, R. Dreslinski, D. Sylvester, D. Blaauw, H. Kim; “A 1920×1080 30fps 2.3TOPS/W Stereo-Depth Processor for Robust Autonomous Navigation”, IEEE International Solid-State Circuits Conference (ISSCC 2017), Invited to JSSC .

Z. Li, Q. Dong, M. Saligane, B. Kempke, L. Gong, Z. Zhang, R. Dreslinski, D. Sylvester, D. Blaauw, Hun Seok Kim; “A 1920×1080 30fps 2.3TOPS/W Stereo Depth Processor for Energy-Efficient Autonomous Navigation of Micro Aerial Vehicles”, IEEE Journal of Solid-State Circuits (JSSC).

Z. Li, X. Jiang, L. Gong, D. Blaauw, C. Chakrabarti, H. Kim; “Low Complexity, Hardware-Efficient Neighbor-Guided SGM Optical Flow for Low Power Mobile Vision Applications”, IEEE Transcations on Circuits and Systems I (TCAS-I), under review.

S. Jeloka, J. Lee, Z. Li, J. Shah, Q. Dong, K. Yang, D. Sylvester, D. Blaauw “An Ultra-Wide Program, 122pJ/Bit Flash Memory Using Charge Recycling”, Symposia on VLSI Circuits (VLSIC 2017)

S. Bang, J. Wang, Z. Li, C. Gao, Y. Kim, Q. Dong, Y. Chen, L. Fick, X. Sun, R. Dreslinski, T. Mudge, H. Kim, D. Blaauw and D. Sylvester; “A 288μW Programmable Deep Learning Processor with 270kB On-chip Weight Storage Using Non-Uniform Memory Hierarchy for Mobile Intelligence”; IEEE International Solid-State Circuits Conference (ISSCC 2017)

Q. Dong, Y. Kim, I. Lee, M. Choi, Z. Li, J. Wang, K. Yang, Y. Chen, J. Dong, M. Cho, G. Kim, W. Chang, Y. Chen, Y. Chih, D. Blaauw, D. Sylvester; “A 1Mb Embedded NOR Flash Memory with 39μW Program Power for mm-Scale High-Temperature Sensor Nodes”; IEEE International Solid-State Circuits Conference (ISSCC 2017)

J. Xiang, Z. Li, H. Kim and C. Chakrabarti; “Hardware-Efficient Neighbor-Guided SGM Optical Flow for Low Power Vision Applications”, IEEE International Workshop on Signal Processing Systems (SiPS), Oct 2016, Presenter, First Place in Bob Owens Best Student Paper Award

i J. Xiang, Z. Li, D. Blaauw, H. Kim and C. Chakrabarti; “Low complexity optical flow using neighbor-guided semi-global matching”, IEEE International Conference on Image Processing (ICIP), Sep 2016

Y. Shi, M. Choi, Z. Li, G. Kim, Z. Foo, H. Kim, D. Wentzloff, D. Blaauw, “Inductive-Coupling Near-Field Radio for Syringe-Implantable Smart Sensor Nodes”, IEEE Journal of Solid-State Circuits (JSSC), Apr 2016

Y. Shi, M. Choi, Z. Li, G. Kim, Z. Foo, H. Kim, D. Wentzloff, D. Blaauw, “A 10mm3 Syringe-Implantable Near-Field Radio System on Glass Substrate”, IEEE International Solid-State Circuits Conference (ISSCC), Feb 2016

S. Oh, Y. Lee, Y. Kim, J. Wang, Z. Foo, W. Jung, Z. Li, D. Blaauw, D. Sylvester, A Dual-Slope Capacitance-to-Digital Converter Integrated in an Implantable Pressure-Sensing System, IEEE Journal of Solid-State Circuits (JSSC), Invited Paper to the Special issue on ESSCIRC, Vol. 50, No. 7, pgs., Jul 2015

External Links

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