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Summary
The purpose of this project is to demonstrate why
traditional methods of logic design ( truth tables + minimization) are no
longer used when designing even the simplest logic design components. In
this project, four components are profiled as two-level implementations
using ESPRESSO for logic minimization and other helpful details.
After the appropriate components are evaluated by ESPRESSO, the resulting
information is analyzed and then put into a table format.
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Using ESPRESSO
- If you are trying to get started using ESPRESSO, you may
want to try these links:
- Creating ESPRESSO inputs can become tedious. It
may be best to find a good program to create your ESPRESSO inputs like "eqntott".
Another alternative is for one to create their own program to create the
ESPRESSO inputs.
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Analyzing ESPRESSO Results
Basic Interpretation of ESPRESSO can be found in the ESPRESSO
tutorial (use link above). The following contains the descriptions of how
to get the results illustrated in the results tables to follow.
-
Inputs: # of Inputs to Component
-
Truth-Table Rows: 2 * Inputs
-
Gate Count: # of Logic Gates Needed for the
Circuit (AND + OR + INV). In most cases the # of outputs equals the # of
OR gates since their is only one OR gate per output in this PLA
Implementation. The # of INVERTERS equals the the number of inputs because
in every circuit there needs to be an inverter to an initial input. The
Number of AND gates is equal to the number of equations that the ESPRESSO
output file has.This can be found by either counting the # of equations
manually or locating the line starting with ".p" before the output
equations are listed (the number after the .p is the number of equations)
-
Transistor Count: # of Transistors for
circuit. This implementation assumes 5 transistors for an AND & OR gates
and 2 for each INV gate.
-
Total # of AND Gate Inputs: This is the
total amount of inputs to all of the AND gates in the circuit. This can be
found either by counting the number of binary digits (do not count don't
cares) in the left hand side of the ESPRESSO output equations or by
looking on the last line of the ESPRESSO output file which starts with a
"#" in front of it. The line contains an expression such as "in=
(number)". That number is the total number of AND gate inputs.
-
Total # of OR Gate Inputs: This is the total
amount of inputs to all of the OR gates in the circuit. This can be found
either by counting the ones on the right hand side of the ESPRESSO output
equations or by looking on the last line of the ESPRESSO output file which
starts with a "#" in front of it. The line contains an expression such as
"out= (number)". That number is the total number of OR gate inputs.
-
Total # of INV Gate Inputs: Equal to the
amount of inputs for a component.
-
Total # of Gate Inputs: Total AND inputs +
Total OR inputs. (Not counting INV gates)
-
Delay: Critical Path of Circuit. To do this
one must get the # of AND gate inputs & OR gate inputs for an individual
output and then technology map the respective AND & OR gates for that
output to get the "levels" of 2-input AND gates & 2-input OR gates used.
To get the levels of inputs you must take the log (base 2) of the # of
inputs. For example, an output having 8 AND gate inputs would technology
map down to 3 levels of 2-input AND gates. Once you have figured out
the technology-mapping "levels" for both the AND gate and the OR gate,
multiply those by the delay for a 2-input AND/OR gate (.12ns & .14ns) This
gives the critical path delay from the and gate level to the or gate
level. Lastly add the delay of an inverter gate to your previous solution
to get the total delay.
-
Logic Synthesis Time: Time taken for
ESPRESSO to minimize equations and create output. The last line of the
ESPRESSO output file which starts with a "#" in front of it contains
the time taken to minimize it. (can be varied by servers)
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N-bit Adder espresso
input files (1bit -> 8bit): a_1
a_2 a_3
a_4 a_5
a_6 a_7
a_8 -generated
by program: espresso.cpp espresso
output files (1bit -> 8bit): 1bit
2bit 3bit
4bit 5bit
6bit 7bit
8bit -obtained
after running ESPRESSO
|
Size
(bits) |
Inputs |
Truth-Table Rows |
Gate
Count |
Transistor Count |
Total # of
AND Gate Inputs |
Total # of
OR Gate Inputs |
Total # of
Gate Inputs
|
Delay (ns) |
Logic Synthesis Time
(seconds) |
| 1 |
2 |
4 |
7 |
29 |
6 |
3 |
9 |
0.29 |
0.01 |
| 2 |
4 |
16 |
18 |
78 |
32 |
11 |
43 |
0.69 |
0.01 |
| 3 |
6 |
64 |
41 |
187 |
115 |
31 |
147 |
0.95 |
0.01 |
| 4 |
8 |
256 |
88 |
408 |
340 |
75 |
415 |
1.23 |
0.04 |
| 5 |
10 |
1028 |
183 |
880 |
892 |
167 |
1059 |
1.37 |
0.33 |
| 6 |
12 |
4096 |
374 |
1834 |
2196 |
355 |
2551 |
1.51 |
3.27 |
| 7 |
14 |
16384 |
757 |
3743 |
5196 |
735 |
5931 |
1.77 |
42.09 |
| 8 |
16 |
65536 |
1539 |
7647 |
11972 |
1499 |
13271 |
1.91 |
1798.60 |
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N-bit Comparator espresso
input files (1bit -> 8bit): ci_1
ci_2 ci_3 ci_4
ci_5 ci_6
ci_7 ci_8 -generated
by program: espresso.cpp espresso
output files (1bit -> 8bit): co_1 co_2
co_3 co_4 co_5
co_6 co_7 co_8 -obtained
after running ESPRESSO
|
Size
(bits) |
Inputs |
Truth-Table Rows |
Gate
Count |
Transistor Count |
Total # of
AND Gate Inputs |
Total # of
OR Gate Inputs |
Total # of
Gate Inputs
|
Delay (ns) |
Logic Synthesis Time
(seconds) |
| 1 |
2 |
4 |
9 |
39 |
8 |
4 |
12 |
0.29 |
0.01 |
| 2 |
4 |
16 |
17 |
73 |
32 |
10 |
42 |
0.55 |
0.01 |
| 3 |
6 |
64 |
31 |
137 |
96 |
22 |
118 |
0.81 |
0.01 |
| 4 |
8 |
256 |
57 |
261 |
256 |
46 |
302 |
0.95 |
0.01 |
| 5 |
10 |
1028 |
107 |
505 |
640 |
94 |
734 |
1.21 |
0.07 |
| 6 |
12 |
4096 |
205 |
989 |
1536 |
190 |
1726 |
1.35 |
0.42 |
| 7 |
14 |
16384 |
389 |
1953 |
3584 |
382 |
366 |
1.49 |
2.43 |
| 8 |
16 |
65536 |
785 |
3877 |
8192 |
766 |
8958 |
1.63 |
25.93 |
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N-bit Multiplier espresso
input files (1bit -> 8bit): m_1
m_2 m_3
m_4 m_5
m_6 m_7
m_8 -generated
by program: espresso.cpp espresso
output files (1bit -> 8bit): o_m1 o_m2
o_m3 o_m4 o_m5
o_m6 o_m7 -obtained
after running ESPRESSO
|
Size
(bits) |
Inputs |
Truth-Table Rows |
Gate
Count |
Transistor Count |
Total # of
AND Gate Inputs |
Total # of
OR Gate Inputs |
Total # of
Gate Inputs
|
Delay (ns) |
Logic Synthesis Time
(seconds) |
| 1 |
2 |
4 |
5 |
19 |
2 |
1 |
3 |
0.29 |
0.00 |
| 2 |
4 |
16 |
15 |
63 |
22 |
8 |
30 |
0.55 |
0.00 |
| 3 |
6 |
64 |
44 |
202 |
136 |
38 |
174 |
0.83 |
0.01 |
| 4 |
8 |
256 |
144 |
696 |
735 |
156 |
891 |
1.23 |
0.21 |
| 5 |
10 |
1028 |
507 |
2505 |
3555 |
613 |
4168 |
1.51 |
3.27 |
| 6 |
12 |
4096 |
1973 |
9829 |
17657 |
2591 |
20248 |
1.79 |
163.52 |
| 7 |
14 |
16384 |
7538 |
37648 |
81575 |
10317 |
91892 |
2.07 |
4765.41 |
| 8 |
16 |
65536 |
N/A - Logic Synthesis Time over 24 hours |
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N-bit Carry-Look Ahead Adder espresso
input files (1bit -> 8bit): cl_1
cl_2 cl_3
cl_4 cl_5
cl_6 cl_7
cl_8 -generated
by program: espresso.cpp espresso
output files (1bit -> 8bit): clo_1
clo_2 clo_3 clo_4
clo_5 clo_6 clo_7
clo_8 -obtained
after running ESPRESSO
|
Size
(bits) |
Inputs |
Truth-Table Rows |
Gate
Count |
Transistor Count |
Total # of
AND Gate Inputs |
Total # of
OR Gate Inputs |
Total # of
Gate Inputs
|
Delay (ns) |
Logic Synthesis Time
(seconds) |
| 1 |
2 |
4 |
9 |
39 |
12 |
3 |
15 |
0.55 |
0.00 |
| 2 |
4 |
16 |
26 |
118 |
120 |
22 |
142 |
0.95 |
0.00 |
| 3 |
6 |
64 |
79 |
377 |
756 |
124 |
880 |
1.23 |
0.01 |
| 4 |
8 |
256 |
276 |
1356 |
4080 |
632 |
4712 |
1.63 |
0.10 |
| 5 |
10 |
1028 |
1049 |
5215 |
20460 |
3056 |
23516 |
1.91 |
1.38 |
| 6 |
12 |
4096 |
4126 |
20594 |
98280 |
14304 |
112584 |
2.19 |
12.86 |
| 7 |
14 |
16384 |
16419 |
82053 |
458724 |
65472 |
524196 |
2.47 |
224.79 |
| 8 |
16 |
65536 |
65576 |
327832 |
2097120 |
294784 |
2391904 |
2.87 |
6989.00 |
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© 2003 University of California, Riverside, Department of Computer Science and
Engineering, Riverside, CA
92521
Questions/Concerns/Corrections? - ksewell@cs.ucr.edu |
