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2005

Dynamic Symmetry-Breaking for Improved Boolean Optimization

Arathi Ramani,, Fadi A. Aloul, Igor L. Markov, and Karem A. Sakallah, in Asia and South Pacific Design Automation Conference (ASP-DAC), Januray 2005, Shanghai, China, 2005.

2004

Exploiting Structure in Symmetry Detection for CNF

P. T. Darga, M. H. Liffiton, K. A. Sakallah, and I. L. Markov, in Proc. 41st IEEE/ACM Design Automation Conference (DAC), pp. 530-534, San Diego, California, 2004.

 
AMUSE: A Minimally-Unsatisfiable Subformula Extractor

Y. Oh, M. N. Mneimneh, Z. S. Andraus, K. A. Sakallah, and I. L. Markov, in Proc. 41st IEEE/ACM Design Automation Conference (DAC), pp. 518-523, San Diego, California, 2004.

 
Automatic Abstraction and Verification of Verilog Models

Z. S. Andraus and K. A. Sakallah, in Proc. 41st IEEE/ACM Design Automation Conference (DAC), pp. 218-223, San Diego, California, 2004.

 
A Comparative Study of Two Boolean Formulations of FPGA Detailed Routing Constraints

G.-J. Nam, F. Aloul, K. A. Sakallah, and R. A. Rutenbar, IEEE Transactions on Computers, vol. 53, no. 6, pp. 688-696, June 2004

 
Breaking Instance-Independent Symmetries in Exact Graph Coloring

A. Ramani, F. A. Aloul, I. L. Markov, and K. A. Sakallah, in Proc. of the Design, Automation and Test in Europe Conference (DATE 2004), pp. 324-329,Paris, France, 2004.

 
ShatterPB: Symmetry-Breaking for Pseudo-Boolean Formulas

F. A. Aloul, A. Ramani, I. L. Markov, and K. A. Sakallah, in Asia and South Pacific Design Automation Conference (ASP-DAC 2004), pp. 884-887,Yokohama, Japan, 2004.

 
Preserving Synchronizing Sequences of Sequential Circuits After Retiming

M. N. Mneimneh, K. A. Sakallah, and J. Moondanos, in Asia and South Pacific Design Automation Conference (ASP-DAC 2004), pp. 579-584,Yokohama, Japan, 2004. (Best Paper Award)

2003

Solving Difficult Instances of Boolean Satisfiability in the Presence of Symmetry

F. A. Aloul, A. Ramani, I. L. Markov, and K. A. Sakallah, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 9, pp. 1117-1137, September 2003.

 
REVERSE: Efficient Sequential Verification for Retiming

M. N. Mneimneh and K. A. Sakallah, in TECHCON, August 2003, Dallas, Texas.

 
Symmetry-Breaking for Pseudo-Boolean Formulas

F. A. Aloul, A. Ramani, I. L. Markov, and K. A. Sakallah, in Third International Workshop on Symmetry in Constraint Satisfaction Problems, Held in conjunction with Ninth International Conference on Principles and Practice of Constraint Programming, CP'03, pp. 1-12, County Cork, Ireland, September 29 2003.

 
Efficient Symmetry Breaking for Boolean Satisfiability

F. A. Aloul, K. A. Sakallah, and I. L. Markov, in Proc. 18th International Joint Conference on Artificial Intelligence (IJCAI-03), pp. 271-282, August 2003, Acapulco, Mexico.

 
Satometer: How Much Have We Searched?

F. A. Aloul, B. Sierawski, and K. A. Sakallah, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 8, pp. 995-1004, August 2003.

 
sub-SAT: A Formulation for Relaxed Boolean Satisfiability with Applications in Routing

H. Xu, R. A. Rutenbar, and K. A. Sakallah, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 6, pp. 814-820, June 2003.

 
Shatter: Efficient Symmetry-Breaking for Boolean Satisfiability

F. A. Aloul, I. L. Markov, and K. A. Sakallah, in Proc. 40th IEEE/ACM Design Automation Conference (DAC), pp. 836-839, June 2003, Anaheim, California.

 
REVERSE: Efficient Sequential Verification for Retiming

M. Mneimneh and K. Sakallah, in Twelfth International Workshop on Logic and Synthesis, pp. 133-139, May 2003, Laguna Beach, California.

 
Computing Vertex Eccentricity in Exponentially Large Graphs: QBF Formulation and Solution

M. Mneimneh and K. Sakallah, in Sixth International Conference on Theory and Applications of Satisfiability Testing, pp. 356-369, May 2003, Portofino, Italy.

 
FORCE: A Fast and Easy-to-Implement Variable-Ordering Heuristic

F. A. Aloul, I. L. Markov, and K. A. Sakallah, in Great Lakes Symposium on VLSI (GLSVLSI 2003), pp. 116-119, April 2003, Washington, D.C.

 
Timing, Test and Manufacturing Overview

K. A. Sakallah, D. M. H. Walker, and S. R. Nassif, in The Best of ICCAD: 20 Years of Excellence in Computer-Aided Design, A. Kuehlmann, Ed.: Kluwer Academic Publishers, 2003, pp. 551-562. Commentary article about the significant developments in timing, test, and manufacturing over the 20-year history of ICCAD.

 
GRASP—A New Search Algorithm for Satisfiability

J. P. Marques Silva and K. A. Sakallah, in The Best of ICCAD: 20 Years of Excellence in Computer-Aided Design, A. Kuehlmann, Ed.: Kluwer Academic Publishers, 2003, pp. 73-89. Reprint of ICCAD 96 article.

 
SAT-based Sequential Depth Computation

M. Mneimneh and K. Sakallah, in Asia and South Pacific Design Automation Conference (ASP-DAC 2003), pp. 87-92, January 2003, Kitakyushu, Japan.

 
Transistor Placement for Noncomplementary Digital VLSI Cell Synthesis

M. A. Riepe and K. A. Sakallah, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 8, no. 1, pp. 81-107, January 2003.

2002

Resynthesis of Multi-level Circuits Under Tight Constraints Using Symbolic Optimization

V. N. Kravets and K. A. Sakallah, in Digest of IEEE International Conference on Computer-Aided Design (ICCAD), pp. 687-693, November 2002, San Jose, California.

 
Generic ILP versus Specialized 0-1 ILP: an Update

F. A. Aloul, A. Ramani, I. L. Markov, and K. A. Sakallah, in Digest of IEEE International Conference on Computer-Aided Design (ICCAD), pp. 450-457, November 2002, San Jose, California.

 
Improving the Efficiency of Circuit-to-BDD Conversion by Gate and Input Ordering

F. A. Aloul, I. L. Markov, and K. A. Sakallah, in International Conference on Computer Design (ICCD), pp. 64-69, September 2002, Freiburg, Germany.

 
Robust SAT-Based Search Algorithm for Leakage Power Reduction

F. A. Aloul, S. Hassoun, K. A. Sakallah, and D. Blaauw, in 12th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS '02), pp. 167-177, September 2002, Sevilla, Spain.

 
SAT-based Sequential Depth Computation

M. Mneimneh and K. Sakallah, in First International Workshop on Constraints in Formal Verification, Held in conjunction with Eight International Conference on Principles and Practice of Constraint Programming, CP2002, September 8 2002, Ithaca, New York.

 
Symmetry Breaking for Boolean Satisfiability: The Mysteries of Logic Minimization

F. A. Aloul, I. L. Markov, and K. A. Sakallah, in Second International Workshop on Symmetry in Constraint Satisfaction Problems, Held in conjunction with Eighth International Conference on Principles and Practice of Constraint Programming, CP2002, pp. 37-46, September 8 2002, Ithaca, New York.

 
Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search

G.-J. Nam, K. Sakallah, and R. Rutenbar, in 12th International Conference on Field Programmable Logic and Application (FPL 2002), Springer-Verlag LNCS 2438, pp. 360-369, September 2002, Montpellier, France.

 
Satometer: How Much Have We Searched?

F. A. Aloul, B. Sierawski, and K. A. Sakallah, in Proc. 39th IEEE/ACM Design Automation Conference (DAC), pp. 737-742, June 2002, New Orlean, Louisiana.

 
Solving Difficult SAT Instances in the Presence of Symmetry

F. A. Aloul, R. Arathi, I. Markov, and K. A. Sakallah, in Proc. 39th IEEE/ACM Design Automation Conference (DAC), pp. 731-736, June 2002, New Orlean, Louisiana.

 
Majority-Based Decomposition of Carry Logic in Binary Adders

L. Nazhandali and K. A. Sakallah, in International Workshop on Logic & Synthesis (IWLS), pp. 179-184, June 2002, New Orleans, Louisiana.

 
Efficient Gate and Input Ordering for Circuit-to-BDD Conversion

F. A. Aloul, I. L. Markov, and K. A. Sakallah, in International Workshop on Logic & Synthesis (IWLS), pp. 137-142, June 2002, New Orleans, Louisiana.

 
ZBDD-Based Backtrack Search SAT Solver

F. A. Aloul, M. N. Mneimneh, and K. A. Sakallah, in International Workshop on Logic & Synthesis (IWLS), pp. 131-136, June 2002, New Orleans, Louisiana.

 
A New FPGA Detailed Routing Approach via Search-Based Boolean Satisfiability

G.-J. Nam, K. A. Sakallah, and R. Rutenbar, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 6, pp. 674-684, June 2002.

 
PBS: A Backtrack-Search Pseudo-Boolean Solver and Optimizer

F. A. Aloul, A. Ramani, I. L. Markov, and K. A. Sakallah, in Fifth International Symposium on Theory and Applications of Satisfiability Testing, pp. 346-353, May 2002, Cincinnati, Ohio.

 
Solving Difficult SAT Instances in the Presence of Symmetry

F. A. Aloul, A. Ramani, I. L. Markov, and K. A. Sakallah, in Fifth International Symposium on Theory and Applications of Satisfiability Testing, pp. 338-345, May 2002, Cincinnati, Ohio.

 
A Tool for Measuring Progress of Backtrack-Search Solvers

F. A. Aloul, B. D. Sierawski, and K. A. Sakallah, in Fifth International Symposium on Theory and Applications of Satisfiability Testing, pp. 98-105, May 2002, Cincinnati, Ohio.

 
sub-SAT: A Formulation for Relaxed Boolean Satisfiability with Applications in Routing

H. Xu, R. A. Rutenbar, and K. A. Sakallah, in Proc. of 2002 International Symposium on Physical Design, pp. 182-187, April 2002, Del Mar, California.

 
Search-Based SAT Using Zero-Suppressed BDDs

F. Aloul and K. Sakallah, in Proceedings of the Design, Automation and Test in Europe Conference (DATE 2002), March 2002, p. 1082, Paris, France.

 
Satisfiability Models and Algorithms for Circuit Delay Computation

L. G. e Silva, J. Marques-Silva, L. M. Silveira, and K. A. Sakallah, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 7, no. 1, pp. 137-158, January 2002.

2001

Static Timing Analysis

Y. Kukimoto, M. Berkelaar, and K. Sakallah, in Logic Synthesis and Verification, S. Hassoun and T. Sasao, Eds., Kluwer Academic Publishers, 2001, pp. 373-401.

 
Faster SAT and Smaller BDDs via Common Function Structure

F. Aloul, I. Markov, and K. A. Sakallah, in Digest of IEEE International Conference on Computer-Aided Design (ICCAD), pp. 443-448, November 2001, San Jose, California.

 
An Advanced Timing Characterization Method Using Mode Dependency

H. Yalcin, R. Palermo, M. S. Mortazavi, C. Bamji, K. A. Sakallah, and J. P. Hayes, in Proc. 38th IEEE/ACM Design Automation Conference (DAC), pp. 657-660, June 2001, Las Vegas, Nevada.

 
SATIRE: A New Incremental Satisfiability Engine

J. Whittemore, J. Kim, and K. A. Sakallah, in Proc. 38th IEEE/ACM Design Automation Conference (DAC), pp. 542-545, June 2001, Las Vegas, Nevada.

 
Scalable Hybrid Verification of Complex Microprocessors

M. Mneimneh, F. Aloul, C. Weaver, S. Chatterjee, K. Sakallah, and T. Austin, in Proc. 38th IEEE/ACM Design Automation Conference (DAC), pp. 41-46, June 2001, Las Vegas, Nevada.

 
Backtrack Search Using ZBDDs

F. A. Aloul, M. N. Mneimneh, and K. A. Sakallah, in International Workshop on Logic Synthesis (IWLS), pp. 293-297, June 2001, Granlibakken, California.

 
MINCE: A Static Global Variable-Ordering for SAT and BDD

F. A. Aloul, I. L. Markov, and K. A. Sakallah, in International Workshop on Logic Synthesis (IWLS), pp. 281-286, June 2001, Granlibakken, California.

 
A Comparative Study of Two Boolean Formulations of FPGA Detailed Routing Constraints

G.-J. Nam, F. Aloul, K. A. Sakallah, and R. Rutenbar, in International Sympoisum on Physical Design (ISPD '01), pp. 222-227, April 2001, Sonoma, California.

 
A Boolean Satisfiability-Based Incremental Rerouting Approach with Application to FPGAs

G.-J. Nam, K. Sakallah, and R. Rutenbar, in Proceedings of the Design, Automation and Test in Europe Conference (DATE 2001), pp. 560-564, March 2001, Munich, Germany.

 
Fast and Accurate Timing Characterization Using Functional Information

H. Yalcin, M. Mortazavi, R. Palermo, C. Bamji, K. A. Sakallah, and J. P. Hayes, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 2, pp. 315-331, February 2001.

2000

Functional Timing Analysis—False Path elimination in Timing Verification

K. A. Sakallah, in TAU '00—ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp. 82-83, December 2000, Austin, Texas. (invited)

 
Generalized Symmetries in Boolean Functions

V. N. Kravets and K. A. Sakallah, in Digest of IEEE International Conference on Computer-Aided Design (ICCAD), pp. 526-532, November 2000, San Jose, California.

 
Structure-Aware Functional Decomposition in Logic Synthesis

V. N. Kravets and K. A. Sakallah, in TECHCON, September 2000, Phoenix, Arizona.

 
On Solving Stack-Based Incremental Satisfiability Problems

J. Kim, J. P. Whittemore, J. P. Marques-Silva, and K. A. Sakallah, in Proc. of IEEE International Conference on Computer Design (ICCD), pp. 379-382, September 2000, Austin, Texas.

 
Boolean Satisfiability in Electronic Design Automation

J. P. Marques-Silva and K. A. Sakallah, in Proc. 37th IEEE/ACM Design Automation Conference (DAC), pp. 675-680, June 2000, Los Angeles, California.

 
Efficient Verification of the PCI Local Bus using Boolean Satisfiability

F. A. Aloul and K. A. Sakallah, in International Workshop on Logic Synthesis (IWLS), pp. 131-135, June 2000, Dana Point, California.

 
An Experimental Evaluation of Conflict Diagnosis and Recursive Learning in Boolean Satisfiability

F. A. Aloul and K. A. Sakallah, in International Workshop on Logic Synthesis (IWLS), pp. 117-121, June 2000, Dana Point, California.

 
Improving SAT: Stack-based Incremental Satisfiability

J. Kim, J. Whittemore, J. P. Marques-Silva, and K. A. Sakallah, in International Workshop on Logic Synthesis (IWLS), pp. 181-184, June 2000, Dana Point, California.

 
Structure-Aware Functional Decomposition in Logic Synthesis

V. N. Kravets and K. A. Sakallah, in International Workshop on Logic Synthesis (IWLS), pp. 81-90, June 2000, Dana Point, California.

 
An Experimental Study of Satisfiability Search Heuristics

F. Aloul, J. P. Marques-Silva, and K. A. Sakallah, in Proceedings of the Design, Automation and Test in Europe Conference (DATE 2000), p. 745, Paris, France, 2000.

 
On Applying Incremental Satisfiability to Delay Fault Testing

J. Kim, J. P. Whittemore, J. P. Marques-Silva, and K. A. Sakallah, in Proceedings of the Design, Automation and Test in Europe Conference (DATE 2000), pp. 380-384, Paris, France, 2000.

 
Constructive Library-Aware Synthesis Using Symmetries

V. N. Kravets and K. A. Sakallah, in Proceedings of the Design, Automation and Test in Europe Conference (DATE 2000), pp. 208-213, Paris, France, 2000.

1999

Satisfiability-Based Functional Delay Fault Testing

J. Kim, J. P. Marques-Silva, and K. A. Sakallah, in Proc. IFIP TC10 WG10.5 Tenth International Conference on Very Large Scale Integration (VLSI '99), pp. 362-372, Lisbon, Portugal, 1999.

 
Incremental Satisfiability and Its Application to Delay Fault Testing

J. Kim, J. Whittemore, J. P. Marques-Silva, and K. A. Sakallah, International Workshop on Logic Synthesis (IWLS), pp. 242-245, June 1999, Lake Tahoe, California.

 
Functional Timing Analysis for IP Characterization

H. Yalcin, M. Mortazavi, R. Palermo, C. Bamji, and K. Sakallah, IEEE/ACM Design Automation Conference, June 21-25, 1999, New Orleans, Louisiana.

 
GRASP: A Search Algorithm for Propositional Satisfiability

J. P. Marques-Silva, and K. A. Sakallah, IEEE Transactions on Computers, vol. 48, no. 5, pp. 506-521, May 1999.

 
Timing Verification of Sequential Dynamic Circuits

D. Van Campenhout, T. Mudge, and K. A. Sakallah, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 5, pp. 645-658, May 1999.

 
Transistor Level Micro-Placement and Routing for Two-Dimensional Digital VLSI Cell Synthesis

M. A. Riepe, and K. A. Sakallah, International Symposium on Physical Design (ISPD-99), April 12-14, 1999, Monterey, California.

 
Satisfiability-Based Layout Revisited: Detailed Routing of Complex FPGAs Via Search-Based Boolean SAT

G.-J. Nam, K. A. Sakallah, and R. A. Rutenbar, ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA'99), pp. 167-175, February 21-23, 1999, Monterey, California.

 
Functional Timing Analysis for IP Characterization

H. Yalcin, M. Mortazavi, R. Palermo, C. Bamji, and K. Sakallah, in TAU99—ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp. 59-64, March 1999, Monterey, California.

 
Satisfiability-Based Detailed FPGA Routing

G.-J. Nam, K. A. Sakallah, and R. A. Rutenbar, in Twelfth International Conference on VLSI Design, January 7-10 1999, pp. 574-577, Goa, India.

1998

False Path Analysis in Sequential Circuits

J. L. Bell, J. P. Whittemore and K. A. Sakallah, in 8th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS98), pp. 245-254, October 1998, Lyngby, Denmark.

 
Timing Analysis Using Propositional Satisfiability

L. G. e Silva, J. P. M. Silva, L. M. Silveira and K. A. Sakallah, in 5th International Conference on Electronics, Circuits, and Systems (ICECS98), pp. 95-98, September 1998, Lisbon, Portugal.

 
The Edge-Based Design Rule Model Revisited

M. A. Riepe and K. A. Sakallah, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 3, no. 3, pp. 463-486, July 1998.

 
M32: A Constructive Multilevel Logic Synthesis System

V. N. Kravets and K. A. Sakallah, in Proc. 35th IEEE/ACM Design Automation Conference (DAC), pp. 336-341, June 1998, San Francisco, California.

 
Congestion Driven Quadratic Placement

P. N. Parakh, R. B. Brown and K. A. Sakallah, in Proc. 35th IEEE/ACM Design Automation Conference (DAC), pp. 275-278, June 1998, San Francisco, California.

 
Satisfiability-Based Algorithms for 0-1 Integer Programming

V. Manquinho, J. M. Silva, A. Oliveira, and K. A. Sakallah, International Workshop on Logic Synthesis (IWLS), pp. 25-34, June 1998, Lake Tahoe, California.

 
Realistic Delay Modeling in Satisfiability-Based Timing Analysis

L. G. e Silva, J. P. M. Silva, L. M. Silveira and K. A. Sakallah, in International Symposium on Circuits and Systems (ISCAS98), June 1998, Monterey, California.

 
Functional Timing Analysis for IP Characterization

H. Yalcin, M. Mortazavi, R. Palermo, C. Bamji, and K. Sakallah, in Proc. Cadence Technical Conference, pp. 544-549, May 1998, San Antonio, Texas. (Received Best Paper Award)

 
Overview of Complementary GaAs Technology for High-Speed VLSI Circuits

R. B. Brown, B. Bernhardt, M. LaMacchia, J. Abrokwah, P. N. Parakh, T. D. Basso, S. M. Gold, S. Stetson, C. R. Gauthier, D. Foster, B. Crawforth, T. McQuire, K. A. Sakallah, R. J. Lomax, and T. N. Mudge, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 6, no. 1, pp. 47-51, March 1998.

 
AFTA: An Automaton for Functional Timing Analysis

V. Chandramouli, J. P. Whittemore and K. A. Sakallah, in Proc. Design, Automation and Test in Europe Conference (DATE98), pp. 350-355, February 1998, Paris, France. (Nominated for Best Paper Award)

1997

Satisfiability Models and Algorithms for Circuit Delay Computation

L. G. e Silva, J. P. M. Silva, L. M. Silveira, and K. A. Sakallah, TAU97: 1997 ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp. 57-62, December 1997, Austin, Texas.

 
AFTA: A Delay Model for Functional Timing Analysis

V. Chandramouli, J. P. Whittemore, and K. A. Sakallah, TAU97: 1997 ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp. 5-14, December 1997, Austin, Texas.

 
Application of System-Level EM Modeling to High-Speed Digital IC Packages and PCB's

J.-G. Yook, L. P. B. Katehi, K. A. Sakallah, R. S. Martin, L. Huang, and T. A. Schreyer, IEEE Transactions on Microwave Theory and Techniques, vol. 45, no. 10, pp. 1847-1856, October 1997

 
Synchronizers and Clocking Schemes in Digital Systems

V. Chandramouli and K. A. Sakallah, IEEE International Workshop on Clock Distribution Networks, Design, Synthesis, and Analysis, October 1997, Atlanta, Georgia

 
Selection of Voltage Thresholds for Delay Measurement

V. Chandramouli and K. A. Sakallah, Special issue on Analog Design Issues in Digital VLSI Circuits and Systems, Journal of Analog Integrated Circuits and Signal Processing (AICSP), Vol. 14, No. 1/2, pp. 9-28, September 1997.

 
Signal delay in Coupled Distributed RC Lines in the presence of Temporal Proximity

V. Chandramouli, A. Kayssi and K. A. Sakallah, in Proc. Advanced Research in VLSI (ARVLSI), pp. 32-46, September 1997, Ann Arbor, Michigan.

 
Design Verification: How Do We Know That These 100-Million Transistor Chips Will Work?

K. A. Sakallah, in Proc. Second LAAS International Conference on Computer Simulation, pp. 1-3, September 1997, Beirut, Lebanon. (invited)

 
Waveform Calculus for Timing Analysis of Digital Circuits

J. P. Whittemore, and K. A. Sakallah, in Proc. Second LAAS International Conference on Computer Simulation, pp. 231-235, September 1997, Beirut, Lebanon.

 
Robust Search Algorithms for Test Pattern Generation

J. P. M. Silva, and K. A. Sakallah, in Proc. Fault-Tolerant Computing Symposium (FTCS), pp. 152-161, June 1997, Seattle, Washington.

 
Test Pattern Generation for Circuits Using Power Management Techniques

J. P. M. Silva, J. C. Monteiro, and K. A. Sakallah, in Proc. European Test Workshop (ETW). 1997, Cagliari, Italy.

 
RID-GRASP: Redundancy Identification and Removal Using GRASP

J. Kim, J. P. M. Silva, H. Savoj and K. A. Sakallah, in Proc. of the International Workshop on Logic Synthesis (IWLS), May 1997, Lake Tahoe, California.

 
RID-GRASP: Redundancy Identification and Removal Using GRASP

J. Kim, J. P. M. Silva, H. Savoj, and K. A. Sakallah, in Cadence Technical Conference, pp. 131-134, May 1997, Keystone, Colorado.

 
Timing Abstraction of Intellectual Property Blocks

S. V. Venkatesh, R. Palermo, M. Mortazavi and K. A. Sakallah, in Proc. Custom Integrated Circuits Conference (CICC), pp. 99-102, May 1997, Santa Clara, California.

 
Computation of Switching Noise in Printed Circuit Boards

J.-G. Yook, V. Chandramouli, L. P. B. Katehi, K. A. Sakallah, T. R. Arabi and T. A. Schreyer, IEEE Transactions on Components, Packaging, and Manufacturing Technology—Part A, vol. 20, no. 1, pp. 64-75, March 1997.

1996

Conflict Analysis in Search Algorithms for Propositional Satisfiability

J. P. M. Silva, and K. A. Sakallah, in Proc. 8th IEEE International Conference on Tools with Artificial Intelligence (ICTAI'96), pp. 467-469, November 1996, Toulouse, France.

 
GRASP—A New Search Algorithm for Satisfiability

J. P. M. Silva and K. A. Sakallah, in Digest of IEEE International Conference on Computer-Aided Design (ICCAD), pp. 220-227, November 1996, San Jose, California

 
Timing Verification of Sequential Domino Circuits

D. Van Campenhout, T. Mudge and K. A. Sakallah, in Digest of IEEE International Conference on Computer-Aided Design (ICCAD), pp. 127-132, November 1996, San Jose, California

 
An Approximate Timing Analysis Method for Datapath Circuits

H. Yalcin, J. P. Hayes and K. A. Sakallah, in Digest of IEEE International Conference on Computer-Aided Design (ICCAD), pp. 114-118, November 1996, San Jose, California.

 
System Level EM Modeling of Digital IC Packages and PC Board

J.-G. Yook, T. Arabi, T. Schreyer, L. P. Katehi and K. A. Sakallah, in Proc. 5th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP'96), pp. 238-240, October 1996, Napa, California

 
Static Timing Analysis of Sequential Domino Circuits

D. Van Campenhout, T. Mudge and K. A. Sakallah, in TECHCON, September 1996, Phoenix, Arizona.

 
A Symbolic Calculus for Timing Analysis of Digital Circuits

J. P. Whittemore and K. A. Sakallah, in TECHCON, September 1996, Phoenix, Arizona

 
Modeling the Effects of Temporal Proximity of Input Transitions on Output Delay and Transition Times

V. Chandramouli and K. A. Sakallah, in Proc. IEEE/ACM Design Automation Conference (DAC), pp. 617-622, June 1996, Las Vegas, Nevada

 
Block Characterization: Timing Abstraction of Megacells

S. V. Venkatesh, M. Mortazavi, R. Palermo, and K. Sakallah, in Cadence Technical Conference, pp. 184-191, May 1996, Napa, California

 
Ravel-XL: A Hardware Accelerator for Assigned-Delay Compiled-Code Logic Gate Simulation

M. A. Riepe, J. P. M. Silva, K. A. Sakallah and R. B. Brown, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 4, no. 1, pp. 113-129, March 1996

1995

Maximum Rate Single-Phase Clocking of a Closed Pipeline including Wave Pipelining, Stoppability, and Startability

C.-H. Chang, E. S. Davidson and K. A. Sakallah, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no. 12, pp. 1526-1545, December 1995

 
Dynamic Modeling of Logic Gate Circuits

K. A. Sakallah, TAU95: 1995 ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp. 103-120, November 1995, University of Washington, Seattle, WA.

 
Computation of Switching Noise in PCBs for Digital Packages

J.-G. Yook, V. Chandramouli, L. P. Katehi and K. A. Sakallah, in Proc. 4th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP'95), pp. 37-39, October 1995, Portland, Oregon

 
Macromodeling and Simulation of RC Interconnection Circuits

A. I. Kayssi and K. A. Sakallah, in Proc. First LAAS International Conference on Computer Simulation (ICCS'95), pp. 207-212, September 1995, American University of Beirut, Lebanon.

 
Computation of Switching Noise in Printed Circuit Boards

J. Yook, V. Chandramouli, L. Katehi and K. A. Sakallah, in Progress in Electromagnetics Research Symposium, July 1995, Seattle, Washington

 
Critical Paths in Circuits with Level-Sensitive Latches

T. M. Burks, K. A. Sakallah and T. N. Mudge, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 3, no. 2, pp. 273-291, June 1995

 
The Aurora RAM Compiler

A. Chandna, D. C. Kibler, R. B. Brown, M. Roberts, and K. A. Sakallah, in Proc. IEEE/ACM Design Automation Conference (DAC), pp. 261-266, June 1995, San Francisco, California.

 
Timing Models for Gallium Arsenide Direct-Coupled FET Logic Circuits

A. I. Kayssi and K. A. Sakallah, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no. 3, pp. 384-393, March 1995

1994

Optimization of Critical Paths in Circuits with Level-Sensitive Latches

T. M. Burks and K. A. Sakallah, in Digest of IEEE International Conference on Computer-Aided Design (ICCAD), pp. 468-473, November 1994, San Jose, California

 
Dynamic Search-Space Pruning Techniques in Path Sensitization

J. P. M. Silva and K. A. Sakallah, in Proc. IEEE/ACM Design Automation Conference (DAC), pp. 705-711, June 1994, San Diego, California (nominated for best paper award)

 
Macromodel Simplification Using Dimensional Analysis

A. I. Kayssi and K. A. Sakallah, in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), vol. 1, pp. 335-338, June 1994, London, England

 
Efficient and Robust Test Generation-Based Timing Analysis

J. P. M. Silva and K. A. Sakallah, in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), vol. 1, pp. 303-306, June 1994, London, England.

 
Delay Macromodels for Point-to-Point MCM Interconnections

A. I. Kayssi and K. A. Sakallah, IEEE Transactions on Components, Packaging and Manufacturing Technology—Part B, vol. 17, no. 2, pp. 147-152, May 1994

1993

Min-Max Linear Programming and the Timing Analysis of Synchronous Circuits

T. M. Burks and K. A. Sakallah, in Digest of IEEE International Conference on Computer-Aided Design (ICCAD), pp. 152-155, November 1993, Santa Clara, California

 
Delay Modeling for GaAs DCFL Circuits

A. I. Kayssi and K. A. Sakallah, in Proc. IEEE GaAs IC Symposium, pp. 67-70, October 1993, San Jose, California

 
Ravel-XL: A Hardware Accelerator for Assigned-Delay Compiled-Code Logic Gate Simulation

M. A. Riepe, J. M. Silva, K. A. Sakallah and R. B. Brown, in Proc. IEEE International Conference on Computer Design (ICCD), pp. 361-364, October 1993, Boston, Massachusetts.

 
An Analysis of Path Sensitization Criteria

J. M. Silva and K. A. Sakallah, in Proc. IEEE International Conference on Computer Design (ICCD), pp. 68-72, October 1993, Boston, Massachusetts.

 
Min-Max Linear Programming and the Timing Analysis of Digital Circuits

T. M. Burks and K. A. Sakallah, in TAU93—ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, September 1993, Malente, Germany

 
A Comparison of Path Sensitization Criteria for Timing Analysis

J. M. Silva and K. A. Sakallah, in TAU93—ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, September 1993, Malente, Germany

 
Sensitization Networks for Accurate Timing Analysis

J. M. Silva and K. A. Sakallah, in TAU93—ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, September 1993, Malente, Germany

 
Concurrent Path Sensitization in Timing Analysis

J. M. Silva and K. A. Sakallah, in European Design Automation Conference (EuroDAC), pp. 196-199, September 1993, Hamburg, Germany

 
Synchronization of Pipelines

K. A. Sakallah, T. N. Mudge, T. M. Burks and E. S. Davidson, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 8, pp. 1132-1146, August 1993.

 
The Impact of Signal Transition Time on Path Delay Computation

A. I. Kayssi, K. A. Sakallah and T. N. Mudge, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 40, no. 5, pp. 302-309, May 1993

 
A High Performance GaAs Microprocessor

T. R. Huff, M. Upton, P. Sherhart, P. Barker, R. McVay, T. Stanley, R. Brown, R. Lomax, T. Mudge and K. Sakallah, in Proc. IEEE Princeton Section Sarnoff Symposium, March 1993, Princeton, New Jersey.

 
Delay-Accurate Compiled-Code Synchronous Gate-Level Verilog Simulation

M. A. Riepe and K. A. Sakallah, in Proc. International Verilog HDL Conference, pp. 121-127, March 1993, Santa Clara, California

 
A 160,000 Transistor GaAs Microprocessor

M. Upton, T. Huff, P. Sherhart, P. Barker, R. Brown, R. Lomax, T. Mudge and K. Sakallah, in International Solid-State Circuits Conference (ISSCC), pp. 92-93, February 1993, San Francisco, California

1992

Identification of Critical Paths in Circuits with Level-Sensitive Latches

T. M. Burks, K. A. Sakallah and T. N. Mudge, in Digest of IEEE International Conference on Computer-Aided Design (ICCAD), pp. 137-141, November 1992, Santa Clara, California.

 
Using Constraint Geometry to Determine Maximum Rate Pipeline Clocking

C.-H. Chang, E. S. Davidson and K. A. Sakallah, in Digest of IEEE International Conference on Computer-Aided Design (ICCAD), pp. 142-148, November 1992, Santa Clara, California.

 
Ravel: Assigned-Delay Compiled-Code Logic Simulation

E. J. Shriver and K. A. Sakallah, in Digest of IEEE International Conference on Computer-Aided Design (ICCAD), pp. 364-368, November 1992, Santa Clara, California.

 
GaAs RISC Processors

R. B. Brown, P. Barker, A. Chandna, T. R. Huff, A. I. Kayssi, R. J. Lomax, T. N. Mudge, D. Nagle, K. A. Sakallah, P. J. Sherhart, R. Uhlig, and M. Upton, in Proc. IEEE GaAs IC Symposium, pp. 81-84, October 1992, Miami Beach, Florida

 
Delay Macromodels for the Timing Analysis of GaAs DCFL

A. I. Kayssi and K. A. Sakallah, in Proc. European Design Automation Conference (EuroDAC), pp. 142-145, September 1992, Hamburg, Germany.

 
Impact of MCMs on System Performance Optimization

A. I. Kayssi, K. A. Sakallah, R. B. Brown, R. J. Lomax, T. N. Mudge and T. R. Huff, in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 919-922, May 1992, San Diego, California

 
Synthesis and Verification of a GaAs Microprocessor from a Verilog Hardware Description

R. Brown, A. Chandna, T. Hoy, T. Huff, R. Lomax, T. Mudge, D. Nagle, K. Sakallah, R. Uhlig, M. Upton, O. Olukotun, and D. Johnson, in Proc. International Verilog HDL Conference, pp. 85-92, March 1992, Santa Clara, California.

 
Multiphase Retiming Using minTc

T. M. Burks, K. A. Sakallah and T. N. Mudge, in TAU92—ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, March 1992, Princeton University.

 
Delay Macromodels for Point-to-Point MCM Interconnections

A. I. Kayssi and K. A. Sakallah, in Proc. IEEE Multi-Chip Module Conference (MCMC), pp. 79-82, March 1992, Santa Cruz, California.

 
Analysis and Design of Latch-Controlled Synchronous Digital Circuits

K. A. Sakallah, T. N. Mudge and O. A. Olukotun, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 11, no. 3, pp. 322-333, March 1992

 
Analytical Transient Response of CMOS Inverters

A. I. Kayssi, K. A. Sakallah and T. M. Burks, IEEE Transactions on Circuits and Systems, vol. 39, no. 1, pp. 42-45, January 1992

1991

FPD—An Environment for Exact Timing Analysis

J. P. Silva, K. A. Sakallah and L. M. Vidigal, in Digest of IEEE International Conference on Computer-Aided Design (ICCAD), pp. 212-215, November 1991, Santa Clara, California

 
Optimal Clocking of Circular Pipelines

K. A. Sakallah, T. N. Mudge, T. M. Burks and E. S. Davidson, in Proc. IEEE International Conference on Computer Design (ICCD), pp. 642-646, October 1991, Boston, Massachusetts.

 
Performance Improvement through Optimal Clocking and Retiming

T. M. Burks, K. A. Sakallah, K. A. Bartlett and G. Borriello, in Proc. of the International Workshop on Logic Synthesis (IWLS), May 1991, Research Triangle Park, North Carolina

 
Multilevel Optimization in the Design of a High-Performance GaAs Microcomputer

O. A. Olukotun, R. B. Brown, R. J. Lomax, T. N. Mudge and K. A. Sakallah, IEEE Journal on Solid State Circuits, vol. 26, no. 5, pp. 763-767, May 1991.

 
Impact of MCM's on System Performance

A. I. Kayssi, K. A. Sakallah, R. B. Brown, R. J. Lomax, T. N. Mudge and T. R. Huff, in Proc. MCM Workshop, pp. 58-65, March 1991, University of California, Santa Cruz

 
The Design of a Microsupercomputer

T. N. Mudge, W. P. Birmingham, R. B. Brown, J. A. Dykstra, A. I. Kayssi, R. J. Lomax, O. A. Olukotun, K. A. Sakallah and R. A. Milano, IEEE Computer, vol. 24, no. 1, pp. 57-64, January 1991

 
The Design of a GaAs Micro-Supercomputer

T. N. Mudge, R. Brown, W. P. Birmingham, J. Dykstra, A. Kayssi, R. Lomax, O. A. Olukotun, K. A. Sakallah and R. Milano, in Proc. Hawaii International Conference on Systems Sciences (HICSS), pp. 421-432, January 1991, Honolulu, Hawaii.

1990

checkTc and minTc: Timing Verification and Optimal Clocking of Synchronous Digital Circuits

K. A. Sakallah, T. N. Mudge and O. A. Olukotun, in Digest of IEEE International Conference on Computer-Aided Design (ICCAD), pp. 552-555, November 1990, Santa Clara, California

 
Optimal Clocking of Synchronous Systems

K. A. Sakallah, T. N. Mudge and O. A. Olukotun, in TAU90—ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, August 1990, University of British Columbia, Vancouver.

 
Analysis and Design of Latch-Controlled Synchronous Digital Circuits

K. A. Sakallah, T. N. Mudge and O. A. Olukotun, in Proc. IEEE/ACM Design Automation Conference (DAC), pp. 111-117, June 1990, Orlando, Florida (nominated for best paper award).

 
Clock Qualification Algorithm for Timing Analysis of Custom CMOS VLSI Circuits with Overlapped Clocking Disciplines and On-Section Clock Derivation

S. C. Menon and K. A. Sakallah, in Proc. International Conference on Systems Integration, pp. 550-558, April 1990, Boston, Massachusetts.

 
A First-Order Charge-Conserving MOS Capacitance Model

K. A. Sakallah, Y.-T. Yen and S. S. Greenberg, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 9, no. 1, pp. 99-108, January 1990

1988

Mixed Analog-Digital Simulation

S. S. Greenberg, J. Grodstein and K. A. Sakallah, in Electro/88 Professional Program Session Record 43/2, pp. 1-8, May 1988, Boston, Massachusetts.

1987

The Meyer Model Revisited: Explaining and Correcting the Charge Non-Conservation Problem

K. A. Sakallah, Y.-T. Yen and S. S. Greenberg, in Digest of IEEE International Conference on Computer-Aided Design (ICCAD), pp. 204-207, November 1987, Santa Clara, California

 
SAM0: An Automatic MOS Circuit Partitioner

Y.-T. Yen and K. A. Sakallah, in Proc. IEEE Custom Integrated Circuits Conference (CICC), pp. 129-132, May 1987, Portland, Oregon.

1985

Polynomial Terminal Equivalent Circuits as Dormant Models in Event Driven Circuit Simulation,

K. A. Sakallah, in Digest of IEEE International Conference on Computer-Aided Design (ICCAD), pp. 179-181, November 1985, Santa Clara, California.

 
SAMSON2: An Event Driven VLSI Circuit Simulator

K. A. Sakallah and S. W. Director, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-4, no. 4, pp. 668-684, October 1985.

 
PRIMO: A VLSI Circuit Partitioner for Simulation Applications

A. V. Vasquez, S. W. Director and K. A. Sakallah, in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1075-1078, June 1985, Kyoto, Japan

 
SAMSON: A Mixed Circuit- Logic-Level Simulator

K. A. Sakallah and S. W. Director, vol. 1 of Computer-Aided Design of VLSI Circuits and Systems (Ed: A. Sangiovanni-Vincentelli), pp. 149-223, JAI Press Inc., 36 Sherwood Place, Greenwich, Connecticut 06830, 1985.

1984

SAMSON: An Event Driven VLSI Circuit Simulator

K. A. Sakallah and S. W. Director, in Proc. IEEE Custom Integrated Circuits Conference (CICC), pp. 226-231, May 1984, Rochester, New York.

1982

An Event Driven Approach for Mixed Gate and Circuit Level Simulation

K. A. Sakallah and S. W. Director, in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1194-1197, May 1982, Rome, Italy.

1981

Mixed Simulation of Electronic Integrated Circuits

Ph.D. Thesis, Carnegie Mellon University, November 1981

 
An Algorithm for Activity-Directed Mixed-Level Simulation of VLSI Circuits

K. A. Sakallah and S. W. Director, in Tenth Computer-Aided Network Design (CANDE) Workshop, September 1981, Gravenhurst, Ontario, Canada

1980

An Activity-Directed Circuit Simulation Algorithm

K. A. Sakallah and S. W. Director, in Proc. IEEE International Conference on Circuits and Computers (ICCC), pp. 1032-1035, October 1980, Rye, New York

1977

The Simulation of Class I Traffic in an Integrated Communications Network

K. A. Sakallah, Master's Thesis, Carnegie Mellon University, June 1977