My research spans low power digital and mixed-signal circuit designs for hardware security and IoT systems. I also enjoy doing collaborative works on inter-disciplinary research, such as secure system design, hardware trojan attack and protection, circuit/system design in emerging devices. Some of my works during Ph.D. are shown below. For full list of the projects I worked on, please refer to my publications.Please click figures to enlarge.
Welcome to my website! Starting from Fall 17, I will be an assistant professor at Rice University. Please check out my new website! In 2017, I finished my PhD in the Michigan Integrated Circuits Lab at the University of Michigan-Ann Arbor. Before coming to Michigan, I received my Bachelor degree from Electronics Engineering (microelectronics) of Tsinghua University, Beijing, China in 2012.
My Ph.D. advisor is Prof. Dennis Sylvester and I'm also working closely with Prof. David Blaauw. During undergraduate, I worked with Prof. Zhiping Yu in Tsinghua University and with Prof. Sung Kyu Lim as a research intern in Georgia Tech, GA, in the summer of 2011. I also held an research internship with ARM Research in summer of 2015.
My research interests include digital and mixed-signal integrated circuit design for low power and secure IoT systems, hardware security, energy efficient and error resilient VLSI design, circuit/system design with emerging devices.
- Starting from Fall 17, I will be an assistant professor at Rice University. Please check out my new website at http://vlsi.rice.edu!
- 12/2016: I am awarded the IEEE Solid-State Circuits Society 2016-2017 Predoctoral Achievement Award! The prestigious awards for Ph.D. students in the area of solid-state circuits are made on the basis of academic record and promise, quality of publications, and a graduate study program well matched to the charter of SSCS.
- 9/2016: My paper "A2: Analog Malicious Hardware" is invited to Communications of ACM (CACM) "Research Highlights". The CACM Research Highlights (CACM-RH) section is devoted to the most important recent research results published in CS.
- 7/2016: My research on analog malicious hardware is 1 of 5 works nominated for Pwnie Most Innovative Research Award. The Pwnie Awards is an annual awards ceremony celebrating the achievements and failures of security researchers and the security community, held at the BlackHat USA security conference.
- 6/2016: Our work on hardware trajon received press coverage by technology medias and security blogs, including WIRED, COMPUTERWORLD, itNews, BoingBoing.net, Security Affairs, Hacker News, Silicon.de[German], Xakep[Russian], Leiphone[Chinese], Gigazine[Japanese], etc..
- 5/2016: We win the Distinguished (Best) Paper Award at 37th IEEE Symposium on Security and Privacy! The IEEE Symposium on Security and Privacy has been the premier forum for computer security and electronic privacy since 1980. This year, 55 of 411 submissions are accepted with 13.4% acceptance rate.
- 2/2016: Our ISSCC 2016 paper on error detection and correction processor (iRazor) is highlighted in ISSCC 2016 press kit.
- 5/2015: We win the Best Student Paper Award (1st place) at 48th IEEE International Symposium on Circuits and Systems (ISCAS 2015)! Award Ceremony Video is here!
- 2/2015: Our ISSCC 2015 paper on highly stable strong physically unclonable function is highlighted in ISSCC 2015 press kit.
- 2/2014: Our ISSCC 2014 paper on fully synthesizable true random number generator is highlighted in ISSCC 2014 press kit.
A2: Analog Malicious Hardware
The rapidly increasing cost to design and fabricate cutting-edge semiconductors forces chip designers to trust a few third-party foundries and third-party IPs, which makes the security of hardware an open question. Trojans are found in commercial chips as reported by University of Cambridge [link].
My work collaborating with computer scientists showed that an attacker can leverage analog behaviors of processors (lowest abstraction level) to insert a Trojan, which evades most existing protections based on digital behavior. The analog Trojan is also extremely small and low power, so that it can be inserted after placement and routing and its side channel leakage is too small to be captured. The payload of the attack is privilege escalation, which is much stronger than most Trojans that cause errors or do certain fixed operations. The significance of the work is to inspire new thoughts on fabrication time attacks and new protections.
This work was the first to describe a possible analog Trojan and the first to verify it in a complete processor (open source OR1200) by silicon chips in 65nm.
Physically Unclonable Functions (PUF)
PUFs are among the most promising security primitives for low cost solutions of key storage, chip authentication, and supply chain protection. Key to all kinds of PUF is good reproducibility across voltage and temperature variations while having enough Hamming Distances between chips and challenges.
My ISSCC 2015 strong PUF paper proposed to replace delay line in conventional arbiter PUF with oscillator and combine the 2 oscillators into a single one with 2 edges chasing each other. Noise is averaged out to achieve much better stability. A dynamic filtering technique is proposed to filter out unstable bits during runtime.
My ISSCC 2017 weak PUF (chip ID) proposes a new PUF cell achieving state-of-the-art stability without sacrificing area and power as in previous works. More details will be disclosed in the published paper.
True Random Number Generator (TRNG)
Silicon TRNG harvesting entropy from physical sources are demanded for higher security level and system integration. All-digital TRNGs provide better performance, easier integration and better technology portability. Oscillator-based TRNG is simpler but suffers from less entropy and lower performance compared to metastability based approach. My research was to improve the usability and performance of oscillator based TRNG by designing new entropy extraction concepts and circuits.
My ISSCC 2014 TRNG harvests entropy from the time it takes for an oscillator initialized to 3rd order harmonics to resume the fundamental frequency. It is theoretically proven that device mismatch doesn’t affect the randomness and therefore no calibration or tuning is required and the TRNG can be synthesized with standard cells. This paper was the first fully synthesizable TRNG to pass all NIST random tests and also the first to evaluate supply injection attack.
My VLSI 2015 TRNG is based on the chasing time of 2 edges propagating in an even-stage RO. This work requires tuning of oscillator but provides an easy-to-use indicator (average time to collapse) of the randomness of current configuration, enabling simple automatic run-time calibration, making it robust against widest reported temperature and voltage ranges. The mismatch of delay cells are used for fine grained tuning, which is much simpler than fine-grained driving strength and cap tuning in metastability based TRNGs.
- K. Yang, Q. Dong, W. Jung, Y. Zhang, M. Choi, D. Blaauw, and D. Sylvester “A 0.6nJ -0.22/0.19ºC inaccuracy temperature sensor using exponential sub-threshold oscillation dependence” 2017 IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2017
- K. Yang, Q. Dong, D. Blaauw, and D. Sylvester “A 553F2 2-Transistor amplifier based Physically Unclonable Function (PUF) with 1.67% native instability” 2017 IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2017
- Q. Dong, Y. Kim, I. Lee, M. Choi, Z. Li, J. Wang, K. Yang, Y-P. Chen, J. Dong, M. Cho, G. Kim, Y-S. Chen, Y-D. Chih, D. Blaauw, and D. Sylvester “A 1Mb Embedded NOR Flash Memory with 39uW Program Power for mm-Scale High-Temperature Sensor Nodes” 2017 IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2017
- Y. Zhang, K. Yang, M. Saligane, D. Blaauw, and D. Sylvester “A compact 446 Gbps/W AES accelerator for mobile SoC and IoT in 40nm” 2016 Symposium on VLSI Circuits Digest of Technical Papers (Symp. VLSI), Jun. 2016
- Q. Dong, K. Yang, D. Blaauw, and D. Sylvester “A 114-pw PMOS-only, trim-free voltage reference with 0.26% within-wafer inaccuracy for nW systems” 2016 Symposium on VLSI Circuits Digest of Technical Papers (Symp. VLSI), Jun. 2016
- X. Wu, Y. Shi, S. Jeloka, K. Yang, I. Lee, D. Sylvester, and D. Blaauw “A 66pW discontinuous switch-capacitor energy harvester for self-sustaining sensor application” 2016 Symposium on VLSI Circuits Digest of Technical Papers (Symp. VLSI), Jun. 2016 - Invited to JSSC
- K. Yang, M. Hicks, Q. Dong, T. Austin, and D. Sylvester “A2: Analog malicious hardware” 2016 IEEE International Symposium on Security and Privacy (Oakland), May 2016 - Distinguished Paper Award, 1 out of 55 accepted papers and 411 submissions, 13.4% acceptance rate - Invited to Communications of ACM (CACM) Research Highlights
- Y. Zhang, M. Khayatzadeh, K. Yang, M. Saligane, N. Pinckney, M. Alioto, D. Blaauw, and D. Sylvester “iRazor: 3-transistor current-based error detection and correction in an ARM Cortex-R4 processor” 2016 IEEE International Solid-State Circuits Conference (ISSCC), Jan. 2016 - ISSCC 2016 Technical Highlight
- W. Jung, J. Gu, P. D. Myers, M. Shim, S. Jeong, K. Yang, M. Choi, Z. Foo, S. Bang, S. Oh, D. Sylvester, and D. Blaauw “A 60%-efficiency 20nW-500µW tri-output fully integrated power management unit with environmental adaptation and load-proportional biasing for IoT systems” 2016 IEEE International Solid-State Circuits Conference (ISSCC), Jan. 2016
- K. Yang, D. Blaauw, and D. Sylvester “A Robust -40 to 120ºC All-Digital True Random Number Generator in 40nm CMOS” 2015 Symposium on VLSI Circuits Digest of Technical Papers (Symp. VLSI), Jun. 2015 - Invited to JSSC
- Q. Dong, K. Yang, L. Fick, D. Fick, D. Blaauw, and D. Sylvester “Racetrack converter: A low power and compact data converter using racetrack spintronic devices” 2015 IEEE International Symposium on Circuits and Systems (ISCAS), May 2015 - Best Student Paper Award
- K. Yang, Q. Dong, D. Blaauw, and D. Sylvester “A physically unclonable function with BER<10-8 for robust chip authentication using oscillator collapse in 40nm CMOS” 2015 IEEE International Solid- State Circuits Conference (ISSCC), Feb. 2015 - ISSCC 2015 Technical Highlight
- S. Oh, W. Jung, K. Yang, D. Blaauw, and D. Sylvester “15.4b incremental sigma-delta capacitance-to-digital converter with zoom-in 9b asynchronous SAR” 2014 Symposium on VLSI Circuits Digest of Technical Papers (Symp. VLSI), Jun. 2014
- K. Yang, D. Fick, M. Henry, Y. Lee, D. Blaauw, and D. Sylvester “A 23Mb/s 23pJ/b fully synthesized true-random-number generator in 28nm and 65nm CMOS” 2014 IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2014 - ISSCC 2014 Technical Highlight
- Q. Jin, K. Yang, C. Zhou, D. Yang, L. Zhang, Y. Wang, Z. Yu, and W. Geng “A transformer-based filtering technique to lower LC-oscillator phase noise” 2012 IEEE International Symposium on Circuits and Systems (ISCAS), May 2012
- K. Yang, D. H. Kim, and S. K. Lim “Design quality tradeoff studies for 3D ICs built with nano-scale TSVs and devices” 2012 13th International Symposium on Quality Electronic Design (ISQED), Mar. 2012
- X. Wu, Y. Shi, S. Jeloka, K. Yang, I. Lee, Y. Lee, D. Sylvester, D. Blaauw "A 20-pW Discontinuous Switched-Capacitor Energy Harvester for Smart Sensor Applications" IEEE Journal of Solid-State Circuits (JSSC), in press
- Q. Dong, K. Yang, L. Fick, D. Fick, D. Blaauw, and D. Sylvester "Low Power and Compact Analog-to-Digital Converter Using Spintronic Racetrack Memory Devices" IEEE Transactions on Very Large Scale Integration Systems (TVLSI), in press
- K. Yang, D. Blaauw, and D. Sylvester "An All-Digital Edge Racing True Random Number Generator Robust Against PVT Variations" IEEE Journal of Solid-State Circuits (JSSC), vol. 51, no. 4, pp. 1022-1031, Apr. 2016
1301 Beal Ave.
Department of Electrical Engineering and Computer Science
University of Michigan
Ann Arbor, MI, 48109, USA