This benchmark consists of an ALU with a comparator, an equality checker, and several parity trees.
The comparator has two 12-bit inputs X and Y, and computes Y>X using
a carry-lookahead adder (CLA) that performs the addition !X+Y.
It can be programmed to do a 4, 6, 8 or 12-bit comparison
of its inputs.
An interesting feature of the comparator is that it uses two identical
CLAs that have identical inputs, a redundancy technique commonly used in
fault-tolerant systems. The CLAs have a fairly standard structure with 3, 4 and 5-bit blocks.
The carry output signal of each CLA gives the result of (Y>X).
The output labeled OutYgreaterX_Equal
(line number 231) is constant 1 if the outputs of the two CLAs are identical,
as would normally be the case.
If, however, the CLAs produced different results, the OutYgreaterX_Equal
output would be logic 0, implying an error in the circuit.
This would happen, for example, if there were manufacturing defects in one of the CLAs.
Module M7 (EqualZ_W) performs an equality check on two 17-bit buses.
The ParityChecker module (M8) contains five 10-input parity trees,
whose outputs are all ANDed.
This module seems to perform a sanity check on the input buses of c2670.
There are also several small pieces of logic which are mostly random.