Vertically-Consistent Spatial Embedding of Integrated Circuits and Systems

Prof. Igor Markov, the University of Michigan

Current students: Jarrod Roy, Aaron Ng, David Papa, Kai-hui Chang, Steve Plaza
Former students: Dr. Saurabh Adya, Shubhyant Chaturvedi, James Lu

Collaborators at Michigan: Mike Moffitt, Prof. Martha Pollack, Prof. Valeria Bertacco
Collaborators at UCSD: Qinke Wang, Sherief Reda, Prof. Andrew Kahng

A large fraction of delay and considerable power in modern electronic systems are due to interconnect, including signal and clock wires, as well as various repeaters. This necessitates greater attention to spatial embedding at the system level and below. Traditional Verilog-based logic design, RTL design and system design at large scale often run into surprising performance losses at the first spatial embedding. This typically happens in floorplanning or gate-level placement, where timing and power constraints become violated and need to be repaired. Such complications are exacerbated by large transistor counts, by the embedding of memories and analog components with random logic, and by the poor scaling of interconnect at deep submicron technology nodes.

To improve the capacity and the overall success of modern electronic system design, distances, sizes and shapes must be accounted for and optimized at multiple layers of abstraction, with smooth transitions between design steps and support for other design optimizations. We pursue this notion of vertically consistent spatial embedding in our research.

A necessary ingredient (and also an enabler of further research) is a series of new spatial embedding algorithms and methodologies applicable at different design steps and used in different scenarios, as folllows.

1. Early, pre-RTL spatial embedding with hard, soft or free-shape modules.
2. Maintaining a consistent embedding through multiple layers of abstraction and transformations between them.
3. Physically safe logic and RTL optimizations.
4. Vertically-consistent repeater/buffer insertion.
5. Consistency between the spatial embedding of gates and wires, e.g., in placement and routing.

To this end, we have developped high-capacity interconnect-driven floorplanning with hard, soft and free-shape modules. We introduced techniques for incremental embedding (or adjustment) relevant to floorplanning, standard-cell placement, mixed-size placement, with respect to module-sizing, buffer insertion and logic restructuring. Such adjustments correct various design violations as well as optimize interconnect.

Our work in physical synthesis shows how to make physically safe simultaneous changes to the netlist and its embedding to significantly improve critical path delay. We are allocating area for buffers earlier than usual, during placement, because without this, the growing number of buffers can make it impossible (at future technology nodes) to meet timing constraints after place-and-route.

In the Place & Route domain, we have shown that Steiner wirelength, a more accurate measure of routed net length than the traditional half-perimeter wire length (HPWL) metric, can be directly optimized in top-down congestion-driven placement, which significantly improves routability and routed wire length.

Many of these techniques are implemented in our tools Capo and Parquet which are available in source code and binaries on Linux, Windows and Solaris platforms. Newer tools under development include a constraint-driven floorplan repair assistant (Floorist) and a counterexample-guided physical synthesis tool (GPSy). Also see our publications.