Welcome to BACPAC, a system-level performance model for the next decade. BACPAC is comprised of a large set of analytical models that have been newly developed and/or compiled to collectively form a new system performance model. Earlier system-level estimators such as Bakoglu's SUSPENS  and Sai-Halasz's cycle-time model  neglect important deep submicron effects such as noise considerations, the rising significance of power dissipation, on-chip memory, process variation, and other effects. BACPAC takes these issues, and many others, into account in order to determine the performance of future high-performance designs. BACPAC is also flexible in that it is geared towards both ASIC's and microprocessors. Motivation for BACPAC was provided by work performed in .
At this website, we have implemented BACPAC so that users can explore the capabilities of future VLSI systems given certain expected input conditions. Also, trends can be determined with respect to various input parameters, whether they are device, interconnect, or system-level properties. In the near future, a variety of different viewpoints will be provided to suit each user. For instance, process engineers who are interested in seeing the impact of varying gate oxide thickness or the dielectric constant of back-end dielectric materials will be able to do this very easily, without the need to consider higher-level architecture issues. On the other hand, system-level designers could examine the impact of varying design hierarchy (designing with 100,000 gate blocks of logic vs. 50,000 for example) without worrying about contacted metal pitches. Full functionality of BACPAC is currently available and we employ a bottom-up approach to "creating" your design. Inputs start at the process level and move up to the system-level parameters.
here to continue and examine a flow-chart describing BACPAC's operation
at this website.
If you have comments or questions on BACPAC, please contact Dennis Sylvester by email at email@example.com
Perl programming for this web-based tool was done by William
 H.B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI,
Addison-Wesley, Chapter 9, 1990.
 G.A. Sai-Halasz, “Performance trends in high-performance processors,” Proc. of the IEEE, pp. 20-36, Jan. 1995.
 D. Sylvester and K. Keutzer, “Getting to the bottom of deep submicron,” Proc. of International Conference on CAD, pp. 203-211, 1998.