Edward S. Davidson - Publications

Books or Monographs

D. L. Weller and E. S. Davidson, "Optimal Searching Algorithms for Parallel-Pipelined Computers," in Lecture Notes in Computer Science #24: Parallel Processing, Springer-Verlag, pp. 291-305, 1974.

D. J. Kuck, E. S. Davidson, D. H. Lawrie, and A. H. Sameh, "Parallel Supercomputing Today and the Cedar Approach," in Experimental Parallel Computing Architectures, (J. J. Dongarra, ed.), Elsevier Science Publishers B. V. (North-Holland), pp. 1-23, 1987.

J.K. Chaar, R.A. Volz and E.S. Davidson, "Developing Control Software for Efficient and Dependable Manufacturing Systems," Intelligent Manufacturing: Programming Environments for Computer Integrated Manufacturing," W.A. Gruver and J. Boudreaux (editors), pp. 2-45, Springer Verlag, October 1993.

J.K. Chaar, R.A. Volz, and E.S. Davidson, "Efficient and Dependable Manufacturing--A Software Perspective" in Computer Control of Manufacturing Systems, Sanjay B. Joshi and Jeffrey S. Smith (editors), Chapman & Hall, 1994.

S.-H. Hung, E. S. Davidson, “System Support for Dynamic Optimization of Application Performance,” in Innovative Architecture for Future Generation High-Performance Processors and Systems (A. Veidenbaum and H. Joe eds.), IEEE Computer Society Press, pp. 7-20, 1999.

S.-H. Hung, E. S. Davidson, “A Framework for Performance Evaluation and Optimization of Parallel Applications,” in Performance Evaluation and Benchmarking with Realistic Applications, (R. Eigenmann ed.), MIT Press, pp. 129-160, 2001.

Papers in Journals and Conferences

E. S. Davidson and G. Metze, "On the Relationship Between Flow-Graphs and the Traveling Salesman Problem," Proc. Fifth Ann. Allerton Conf. on Circuit and System Theory, pp. 683-691, October 1967.

E. S. Davidson and G. Metze, "Module Complexity and NAND Network Design Algorithms,"
Proc. Sixth Ann. Allerton Conf. on Circuit and System Theory, pp. 538-548, October 1968.

E. S. Davidson and G. Metze, "Comments on 'An Algorithm for Synthesis of Multiple-Output Combinational Logic'," IEEE TC, pp. 1091-1092, November 1968.

E. S. Davidson, "An Algorithm for NAND Decomposition under Network Constraints," IEEE-TC, pp. 1098-1109, December 1969.

H. P. Lee and E. S. Davidson, "A Transform for NAND Network Design," IEEE-TC, pp. 12-20, January 1972.

E. S. Davidson, "Scheduling for Pipelined Processors," Proc. Seventh Hawaii Conf. on System Sciences, pp. 58-60, January 1974.

L. E. Shar and E. S. Davidson, "A Multiminiprocessor System Implemented Through Pipelining," IEEE Computer Society, Lake Arrowhead Workshop on Minicomputers, published as a Special Feature in Computer, pp. 42-51, February 1974.

H. P. Lee and E. S. Davidson, "Redundancy Testing in Combinational Logic Networks," IEEE-TC, pp. 1029-1047, October 1974.

E. S. Davidson, "The University of Illinois Microcomputer Laboratory," Proc. Compcon Spring 1975, pp. 123-126.

E. S. Davidson and F. A. Briggs, "Organization of Semiconductor Memories for Parallel-Pipelined Processors," 1975 Sagamore Computer Conf. on Parallel Processing, pp. 155-158, August 1975.

J. H. Patel and E. S. Davidson, "Improving the Throughput of a Pipeline by Insertion of Delays," ACM, IEEE Third Ann. Symp. on Computer Architecture, pp. 159-164, January 1976.

F. A. Briggs and E. S. Davidson, "Organization of Semiconductor Memories for Parallel-Pipelined Processors," IEEE-TC, pp. 162-169, February 1977.

D. Hammerstrom and E. S. Davidson, "Information Content of CPU Memory Referencing Behavior," ACM, IEEE Fourth Ann. Symp . on Computer Architecture, pp. 184-192, March 1977.

J. Emer and E. S. Davidson, "Control Store Organization for Multiple Stream Pipelined Processors," 1978 Int’l. Conf. on Parallel Processing, pp. 43-48, August 1978.

B. Kumar and E. S. Davidson, "Performance Evaluation of Highly Concurrent Computers by Deterministic Simulation," CACM, pp. 904-913, November 1978.

W. Kaminsky and E. S. Davidson, "Developing a Multiple Instruction Stream Single Chip Processor," Computer, pp. 66-76, December 1979.

E. S. Davidson, "A Multiple Stream Processor Prototype System: AMP-1," Proc. 7th Int’l. Symp. on Computer Architecture, pp. 9-16, May 1980.

B. Kumar and E. S. Davidson, "Computer System Design Using a Hierarchical Approach to Performance Evaluation," CACM, pp. 511-521, September 1980.

R. Budzinski, E. S. Davidson, W. Mayeda and H. Stone, "DMIN: An Algorithm for Computing the Optimal Dynamic Allocation in a Virtual Memory Computer," IEEE-TSE, pp. 113-121, January 1981.

R. Budzinski and E. S. Davidson, "A Comparison of Dynamic and Static Virtual Memory Allocation Algorithms," IEEE-TSE, pp. 122-131, January 1981.

G. P. Mak, J. A. Abraham and E. S. Davidson, "The Design of PLAs with Concurrent Error Detection," Proc. 12th Int’l. Symp. on Fault-Tolerant Computing, pp. 303-310, June 1982.

D.W.L. Yen, J. H. Patel and E. S. Davidson, "Memory Interference in Synchronous Multiprocessor Systems," IEEE-TC, pp. 1116-1121, November 1982.

P.C.C. Yeh, J. H. Patel and E. S. Davidson, "Shared Cache for Multiple-Stream Computer Systems," IEEE-TC, pp. 38-47, January 1983.

P.C.C. Yeh, J. H. Patel and E. S. Davidson, "Performance of Shared Cache for Parallel-Pipelined Computer Systems," Proc. Int’l. Symp. on Computer Architecture, pp. 117-123, June 1983.

C. Y. Wong, W. K. Fuchs, J. A. Abraham and E. S. Davidson, "The Design of a Microprogram Control Unit with Concurrent Error Detection," Proc. 13th Int’l. Symp. on Fault-Tolerant Computing, pp. 476-483, June 1983.

A. R. Pleszkun and E. S. Davidson, "Structured Memory Access Architecture," Proc. 1983 Int’l. Conf. on Parallel Processing, pp. 461-471, August 1983.

J. A. Abraham, E. S. Davidson and J. H. Patel, "Memory-System Design for Tolerating Single Event Upsets," IEEE-Trans. on Nuclear Science, vol. NS-30, pp. 4339-4344, December 1983.

P. Bose and E. S. Davidson, "Design of Instruction Sets for Efficient Support of High-Level Languages," Proc. Int’l. Workshop on High-Level Architecture, Los Angeles, California, pp. 7.10-7.19, May 1984.

P. Bose and E. S. Davidson, "Design of Instruction Set Architectures for Support of High-Level Languages," Proc. 11th Symp. on Computer Architecture, Ann Arbor, Michigan, pp. 198-206, June 1984.

G. S. Sohi and E. S. Davidson, "Performance of the Structured Memory Access (SMA) Architecture," Proc. 1984 Int’l. Conf. on Parallel Processing, Bellaire, Michigan, pp. 506-513, August 1984.

D. F. Paul, W. K. Jenkins and E. S. Davidson, "Residue Arithmetic for Real-Time Applications: High Throughput and Reliability Using Customized Modules," Proc. IEEE Int’l. Conf. on Computer Design: VLSI in Computers, Chester, New York, pp. 689-694, October 1984.

W. K. Jenkins, E. S. Davidson and D. F. Paul, "A Custom-Designed Integrated Circuit for the Realization of Residue Number Digital Filters," Proc. 1985 Int’l. Conf. on Acoustics, Speech, and Signal Processing, Tampa, Florida, March 1985.

G. S. Sohi, E. S. Davidson and J. H. Patel, "An Efficient LISP-Execution Architecture with a New Representation for List Structures," Proc. 12th Int’l. Symp. Comp. Arch., Boston, Massachusetts, pp. 91-98, June 1985.

P.Y.-T. Hsu, J. T. Rahmeh, E. S. Davidson and J. A. Abraham, "TIDBITS: Speedup via Time-Delay Bit-Slicing in ALU Design for VLSI Technology," Proc. 12th Int’l. Symp. on Comp. Arch., Boston, Massachusetts, pp. 28-35, June 1985.

D. J. Kuck, E. S. Davidson, D. H. Lawrie and A. H. Sameh, "Parallel Supercomputing Today and the Cedar Approach," Science, pp. 967-974, February 1986.

A. R. Pleszkun, G. S. Sohi, B. Z. Kahhaleh and E. S. Davidson, "Features of the Structured Memory Access (SMA) Architecture," Compcon 86, San Francisco, California, pp. 259-263, March 1986.

P.Y.-T. Hsu and E. S. Davidson, "Highly Concurrent Scalar Processing," Proc. 13th Int’l. Symp. on Comp. Arch., Tokyo, Japan, pp. 386-395, June 1986.

S. G. Abraham and E. S. Davidson, "A Communication Model for Optimizing Hierarchical Multiprocessor Systems," Proc. 1986 Int’l. Conf. on Parallel Processing, St. Charles, Illinois, pp. 467-474, August 1986.

P. G. Emma and E. S. Davidson, "Characterization of Branch and Data Dependencies in Programs for Evaluating Pipeline Performance," IEEE-TC, pp. 859-875, July 1987.

T. Davis and E. S. Davidson, "PSolve: A Concurrent Algorithm for Solving Sparse Systems of Linear Equations," Proc. 1987 Int’l. Conf. on Parallel Processing, St. Charles, Illinois, pp. 483-490, August 1987.

G. McNiven and E. S. Davidson, "Analysis of Memory Referencing Behavior for Design of Local Memories," Proc. 15th Ann. Int’l. Symp. on Computer Architecture, Honolulu, Hawaii, pp. 56-63, May 1988.

J-H. Tang and E. S. Davidson, "An Evaluation of Cray-1 and Cray X-MP Performance on Vectorizable Livermore Fortran Kernels," Proc. 1988 Int’l. conf. on Supercomputing, St. Malo, France, pp. 510-518, July 1988.

J-H. Tang, E. S. Davidson and J. Tong, "Polycyclic Scheduling vs. Chaining on 1-Port Vector Supercomputers," Proc. Supercomputing '88 Conf., Orlando, Florida, pp. 122-129, November 1988.

T. A. Davis and E. S. Davidson, "Pairwise Reduction for the Direct, Parallel Solution of Sparse, Unsymmetric Sets of Linear Equations," IEEE-TC (Special Issue on Parallel and Distributed Algorithms), pp. 1648-1654, December 1988.

W. Mangione-Smith, S. G. Abraham and E. S. Davidson, "The Effects of Memory Latency and Fine-grain Parallelism on Astronautics ZS-1 Performance," Proc. 23rd Ann. Hawaii Int’l. Conf. on System Sciences, Kailua-Kona, Hawaii, vol. I, pp. 288-296, January 1990.

J. K. Chaar and E. S. Davidson, "Cyclic Job Shop Scheduling Using Reservation Tables," IEEE 1990 Int’l. Conf. on Robotics and Automation, Cincinnati, Ohio, pp. 2128-2135, May 1990.

W. Mangione-Smith, S.G. Abraham and E.S. Davidson, "Architectural vs. Delivered Performance of the IBM RS/6000 and the Astronautics ZS-1," 24th Annual HICSS, Kauai, HI, vol. 2, pp. 397-408, Jan. 1991. (Best Paper Award in the Architecture Track)

W. Mangione-Smith, S.G. Abraham and E.S. Davidson, "A Performance Comparison of the IBM RS/6000 and the Astronautics ZS-1," Computer, vol. 24, no. 1, pp. 39-46, Jan. 1991. (Special Issue on Research in Experimental Computer Architecture)

W. Mangione-Smith, S.G. Abraham and E.S. Davidson, "Vector Register Design for Polycyclic Vector Scheduling," 4th Intl. Conf. on Architectural Support for Programming Languages and Operating Systems, Santa Clara, CA, pp. 154-163, April 1991.

J. Konicek, T. Tilton, A. Veidenbaum, C.Q. Zhu, E.S. Davidson, R. Downing, M. Haney, M. Sharma, P.C. Yew, P.M. Farmwald, D. Kuck, D. Lavery, R. Lindsey, D. Pointer, J. Andrews, T. Beck, T. Murphy, S. Turner, and N. Warter, "The Organization of the Cedar System," Proc. 1991 Int’l. Conf. on Parallel Processing, St. Charles, IL, Vol. I, pp. 49-56, August 1991.

K. Sakallah, T. Mudge, T. Burks and E. S. Davidson, "Synchronization of Circular Pipelines," Proc. 1991 Int’l. Conf. on Computer Design, pp. 642-646, October 1991.

J.K. Chaar, R.A. Volz and E.S. Davidson, "An Integrated Approach to Developing Manufacturing Control Software," Proc. of the 1991 IEEE Int’l. Conf. on Robotics and Automation, pp. 1979-1984, April 1991.

W. Mangione-Smith, S.G. Abraham and E.S. Davidson, "Register Requirements of Pipelined Processors," Proc. Int'l Conf. on Supercomputing, pp. 260-271, July 1992.

C-H. Chang, E. S. Davidson and K. A. Sakallah, "Using Constraint Geometry to Determine Maximum Rate Pipeline Clocking," Proc. Int'l Conf. on Computer-Aided Design, pp. 142-148, November 1992.

D. Windheiser, E.L. Boyd, E. Hao, S.G. Abraham, and E.S. Davidson, "KSR1 Multiprocessor: Analysis of Latency Hiding Techniques in a Sparse Solver," Proc. 7th Int'l. Parallel Processing Symposium, pp. 454-461, April l993.

E.L. Boyd and E.S. Davidson, "Hierarchical Performance Modeling with MACS: A Case Study of the Convex C-240," Proc. Int'l Symp. on Computer Arch., pp. 203-2l2, May l993.

D. Kuck, E.S. Davidson, D. Lawrie, D. Padua, R. Downing, M. Haney, P.C. Yew, A. Veidenbaum, R. Eigenmann, P. Emrath, K. Gallivan, J. Konicek, and T. Murphy, "The Cedar System and the Initial Performance Study," Proc. Int'l Symp. on Computer Arch., pp. 2l3-223, May l993.

E.L. Boyd, J.D. Wellman, S. G. Abraham, and E.S. Davidson, "Evaluating the Communication Performance of MPPs Using Iterative Sparse Matrix Multiplications," International Conference on Supercomputing, pp. 240-250, July l993.

W. Mangione-Smith, T.P. Shih, S.G. Abraham and E.S. Davidson, "Approaching a Machine-Application Bound in Delivered Performance on Scientific Code," IEEE Proceedings, Special Issue on Performance Evaluation, pp. 1166-1178, August l993.

K. Sakallah, T. Mudge, T. Burks, and E. S. Davidson, "Synchronization of Pipelines," IEEE Transactions on Computer-Aided Design of Integrated Circtuits and Systems, pp. 1132-1146, August 1993.

E.L. Boyd and E.S. Davidson, "Communication in the KSR1 MPP: Performance Evaluation Using Synthetic Workload Experiments," Proceedings of the 1994 International Conference on Supercomputing, pp. 166-175, July 1994.

W.M. Meleis and E.S. Davidson, "Optimal Local Register Allocation for a Multiple-Issue Machine," Proceedings of the 1994 International Conference on Supercomputing, pp. 107-116, July 1994.

E.L. Boyd, W. Azeem, H-H. Lee, T-P, Shih, S-H. Hung, and E.S. Davidson, "A Hierarchical Approach to Modeling and Improving the Performance of Scientific Applications on the KSR1," Proceedings of the 1994 International Conference on Parallel Processing, Vol. III, pp. 188-192, August 1994.

A. E. Eichenberger, E.S. Davidson, and S. G. Abraham, "Minimum Register Requirements for a Modulo Schedule," Proceedings of the 27th Annual Int’l. Symposium on Microarchitecture, pp.75-84, November 1994.

T.-P. Shih and E.S. Davidson, "Grouping Array Layout to Reduce Communication and Improve Locality of Parallel Programs," Proceedings of the 1994 Int’l. Conference on Parallel and Distributed Systems, pp. 558-566, December 1994.

A. E. Eichenberger, E.S. Davidson, and S.G. Abraham, "Optimum Modulo Schedules for Minimum Register Requirements," Proceedings of the 1995 Int’l. Conference on Supercomputing, Barcelona, Spain, pp. 31-40, July 1995.

J-D. Wellman and E.S. Davidson, "The Resource Conflict Methodology for Early-Stage Design Space Exploration of Superscalar RISC Processors," Proceedings of the 1995 Int’l. Conference on Computer Design, Austin, TX, pp. 110-115, October 2-4, 1995.

C.H. Chang and E.S. Davidson, "Delay balancing using latches," Proceedings of Tau ‘95: ACM
Int’l. Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp. 66-73, November, 1995.

C.H. Chang, E.S. Davidson, K.A. Sakallah, "Maximum rate single-phase clocking of a closed pipeline including wave pipelining, stoppability and startablity," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no. 12, pp. 1526-1545, December 1995.

A. E. Eichenberger and E. S. Davidson, "Stage Scheduling: A Technique to Reduce the Register Requirements of a Modulo Schedule," Proceedings of the 28th Annual International Symposium on Microarchitecture, pp. 338-349, November 1995.

A. E. Eichenberger and E.S. Davidson, "Register Allocation for Predicated Code," Proceedings of the 28th Annual International Symposium on Microarchitecture, pp. 180-190, November 1995.

A. E. Eichenberger, E.S. Davidson, and S. G. Abraham, "Minimizing Register Requirements of a Modulo Schedule via Optimum Stage Scheduling," Int’l. Journal of Parallel Processing, Vol. 24, No.2, pp. 103-132, April 1996.

G. A. Abandah and E. S. Davidson, "Modeling the Communication Performance of the IBM SP2," Proceedings Int’l. Parallel Processing Symposium, Honolulu, HI, pp. 249-257, April 1996.

K. A. Tomko and E. S. Davidson, "Profile Driven Weighted Decomposition," Proceedings of the 10th ACM Int'l. Conference on Supercomputing, Philadelphia, PA, pp. 165-172, May 25-28, 1996.

A. E. Eichenberger and E.S. Davidson, "A Reduced Multipipeline Machine Description that Preserves Scheduling Constraints," Conference on Programming Language Design and Implementation, Philadelphia, PA, pp. 12-22, May 22-24, 1996.

J. A. Rivers and E.S. Davidson, "Reducing Conflicts in Direct-Mapped Caches with a Temporality-Based Design," Proceedings of the Int’l. Conference on Parallel Processing, Bloomingdale, IL, vol. 1, pp. 151-162, August 1996.

J. A. Rivers and E.S. Davidson, "Performance Issues in Integrating Temporality-Based Caching with Prefetching," Proc. IFIP WG7.3 Int'l. Conf. on Performance Theory, Measurement and Evaluation of Computer and Communication Systems (Performance ‘96), Lausanne, Switzerland, October, 1996 and in special issue of Performance Evaluation, vol. 27-28, pp. 189-207, 1996.

A. E. Eichenberger and E. S. Davidson, "Efficient Formulation for Optimal Modulo Schedulers," Proc. Conf. on Programming Language Design and Implementation (PLDI), pp. 194-205, June 1997.

J. A. Rivers, E. S. Tam, and E. S. Davidson, "On Effective Data Supply for Multi-Issue Processors," Proc. IEEE Int’l. Conference on Computer Design, Austin, TX, pp. 519-528, October, 1997.

J. A. Rivers, G. S. Tyson, T. M. Austin, and E. S. Davidson, "On High-Bandwidth Data Cache Design for Multi-Issue Processors," Proc. 30th IEEE/ACM Int’l. Symposium on Microarchitecture, pp. 46-56, December, 1997.

G. A. Abandah and E. S. Davidson, "Characterizing Shared Memory and Communication Performance: A Case Study of the Convex SPP1000," IEEE Trans. on Parallel and Distributed Systems, vol. 9, no. 2, pp. 206-216, February, 1998.

G. A. Abandah and E. S. Davidson, "Configuration Independent Analysis for Characterizing Shared-Memory Applications," 12th Int’l. Parallel Processing Symposium, pp. 485-491, March 1998.

G. A. Abandah and E. S. Davidson, "A Comparative Study of Cache-Coherent Nonuniform Memory Access Systems," High Performance Computing systems and Applications, Kluwer Academic Publishers, and in 12th Ann. Int'l. Symp. on High Performance Computing Systems and Applications (HPCS'98), pp. 267-282, May 1998.

G. A. Abandah and E. S. Davidson, "Effects of Architectural and Technological Advances on the HP/Convex Exemplar's Memory and Communication Performance," Proc. 25th Int'l. Symp. on Computer Architecture (ISCA'98), pp. 318-329, June 1998.

J. A. Rivers, E. S. Tam, G. S. Tyson, E. S. Davidson, and M. Farrens, "Utilizing Reuse Information in Data Cache Management," Proc. 12th ACM International Conference on Supercomputing, pp. 449-456, July, 1998.

E. S. Tam, J. A. Rivers, G. S. Tyson, and E. S. Davidson "mlcache: A Flexible Multi-Lateral Cache Simulator," Proc. 6th Int'l. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS'98), pp. 19-26, July, 1998.

E. S. Tam, J. A. Rivers, V. Srinivasan, G. S. Tyson, and E. S. Davidson, "Evaluating the Performance of Active Cache Management Schemes," Proceedings of the 1998 International Conference on Computer Design, pp. 368-375, October, 1998.

G. A. Abandah and E. S. Davidson, "Origin 2000 Design Enhancements for Communication Intensive Applications," Proc. Int'l. Conference on Parallel Architecture and Compilation Techniques (PACT'98), pp. 30-39, October, 1998.

E. S. Tam, J. A. Rivers, V. Srinivasan, G.S. Tyson, and E. S. Davidson, "Active Management of Data Caches by Exploiting Reuse Information," IEEE Transactions on Computers, pp. 1244-1259, Nov. 1999.

M. Annavaram, G. S. Tyson and E. S. Davidson, "Instruction Overhead and Data Locality Effects in Superscalar Processors," Proc. of IEEE Int'l Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 95-100, April 2000.

M. Smelyanskiy, G.S. Tyson and E.S. Davidson, "Register Queues: A New Hardware/Software Approach to Efficient Software Pipelining," Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques (PACT'00), pp. 3-12, Oct. 2000.

S. Vlaovic, E.S. Davidson, G.S. Tyson, "Improving BTB Performance in the Presence of DLLs," Proceedings of the 33rd International Symposium on Microarchitecture, pp. 77-86, December 2000.

M. Annavaram, J. M. Patel, and E. S. Davidson, "Call Graph Prefetching for Database Applications," Proc. Int’l Conference on High-Performance Computer Architecture (HPCA-7), pp. 281-290, Jan. 2001.

V. Srinivasan, E. S. Davidson, G. S. Tyson, M. J. Charney, and T. R. Puzak, "Branch History Guided Instruction Prefetching," Proc. Int’l Conference on High-Performance Computer Architecture (HPCA-7), pp. 291-300, Jan. 2001.

M. Annavaram, J. M. Patel, and E. S. Davidson, "Data Prefetching by Dependence Graph Precomputation," Proc. of 28th Int'l Symposium on Computer Architecture (ISCA2001), pp. 52-61, July. 2001.

G. S. Tyson, M. Smelyanskiy, and E. S. Davidson, "Evaluating the Use of Register Queues in Software Pipelined Loops," IEEE Transactions on Computers, pp. 769-783, Aug. 2001.

E. S. Tam, S. A. Vlaovic, G. S. Tyson, and E. S. Davidson, "Allocation By Conflict: A Simple, Effective Cache Management Scheme," Proc. IEEE International Conference on Computer Design, pp. 133 – 140, Sept. 2001.

S. Vlaovic and E. S. Davidson, "Boosting Trace Cache Performance with NonHead Miss Speculation," Proc. International Conference on Supercomputing, pp. 179-188, June 2002.

S. Vlaovic and E. S. Davidson, "TAXI: Trace Analysis for X86 Interpretation," Proc. IEEE International Conference On Computer Design, pp. 508-514, Sept. 2002.

M. Smelyanskiy, S. A. Mahlke, E. S. Davidson, and H-H. S. Lee, "Predicate-aware Scheduling: A Technique for Reducing Resource Constraints," Proc. IEEE/ACM International Symposium on Code Generation and Optimization (CGO), pp. 169-178, March 2003.

M. Annavaram, J. M. Patel, and E. S. Davidson, "Call Graph Prefetching for Database Applications," ACM Transactions on Computer Systems, pp. 412-444, Nov. 2003.

V. Srinivasan, E. S. Davidson and G. S. Tyson, “A Prefetch Taxonomy,” IEEE Transactions on Computers, pp. 126-140, Feb. 2004.

M. Smelyanskiy, S. A. Mahlke, and E. S. Davidson, “Probabilistic Predicate-Aware Modulo Scheduling.” Proc. IEEE/ACM International Symposium on Code Generation and Optimization (CGO), pp. 151-162, March 2004.

Invited Talks and Papers

E. S. Davidson, "The Design and Control of Pipelined Function Generators," Proc. 1971 Int’l. IEEE Conf. on Systems, Networks and Computers, Oaxtepec, Mexico. January 1971.

A. G. Larson and E. S. Davidson, "Cost-Effective Design of Special Purpose Processors: A Fast Fourier Transform Case Study, Proc. Eleventh Ann. Allerton Conf. on Circuit and System Theory, pp. 547-557, October 1973.

A. T. Thomas and E. S. Davidson, "Schedule of Multiconfigurable Pipelines, Proc. Twelfth Ann. Allerton Conf. on Circuit and System Theory, pp. 658-669, October 1974.

E. S. Davidson, L. E. Shar, A. T. Thomas, and J. H. Patel, "Effective Control of Pipelined Computers," Proc. Compcon Spring 1975, pp. 181-184.

E. S. Davidson, "Toward a Multiple Stream Microprocessor System," Proc. Midcon, 1977 paper 16/5.

E. S. Davidson, "The University of Illinois Microcomputer Laboratory," COMPSAC Workshop on Computer Engineering Laboratories, November 1979.

E. S. Davidson, "Microcomputer Laboratories at the University of Illinois in Computer Engineering," Compcon Special Session, September 1980.

A. R. Pleszkun, B. R. Rau, and E. S. Davidson, "An Address Prediction Mechanism for Reducing Processor-Memory Bandwidth," Proc. 1981 IEEE Computer Society Workshop on Computer Architecture for Pattern Analysis and Image Database Management, pp. 141-148, November 1981.

E. S. Davidson, "A Broader Range of Possible Answers to the Issues Raised by RISC," Compcon 86, San Francisco, California, p. 313, March 1986.

E. S. Davidson, "Some Related Problems in Architecture and Fault-Tolerance: Exception Detection, Recovery, and Security," Keynote Address, Symp. on Fault-Tolerant Computing, Chicago, Illinois, June 1989.

E. S. Davidson, "Higher Performance Computing: A Functional Approach," Keynote Address, Int'l. Symp. on Computer Architecture, Chicago, Illinois, April 1994.

E. S. Davidson, "Assessing the Performance Capability of Highly Concurrent Computer
Systems," at IBM Research Conference to commemorate 25 years of RISC technology
research, November 4-5, 1995.

S.-H. Hung, E. S. Davidson, "System Support for Dynamic Optimization of Application Performance," at Int’l. Workshop on Innovative Architecture (IWIA ’98), Oct. 1998, Maui HI.

S.-H. Hung, E. S. Davidson, "System Support for Parallel Application Performance Optimization," at SPEC Wkshp. On Performance Evaluation with Realistic Applications, Jan. 25, 1999, San Jose, CA.

A. W. Burks and E. S. Davidson, "Introduction to ‘The Eniac’," a commemorative reprint of the 1948 classic paper, in Proceedings of the IEEE, Vol. 87, No. 6, pp. 1028-1041, June 1999.

E. S. Davidson, "The Mission of Performance Analysis: a Functional Approach," Keynote Address, Int’l Symp. on Performance Analysis of Systems and Software (ISPASS), Austin, Texas, April 2000.

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